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2020-03-14Implement NT_NETBSDCORE_LWPSTATUS (NetBSD-Core)Kamil Rytarowski2-1/+6
bfd/ChangeLog: * elf.c (elfcore_grok_netbsd_note): Add support for NT_NETBSDCORE_LWPSTATUS notes. binutils/ChangeLog: * readelf.c (get_netbsd_elfcore_note_type): Add support for NT_NETBSDCORE_LWPSTATUS notes. include/ChangeLog: * elf/common.h (NT_NETBSDCORE_LWPSTATUS): New define.
2020-03-13Register NT_NETBSDCORE_AUXV (NetBSD-Core)Kamil Rytarowski2-0/+5
* elf/common.h (NT_NETBSDCORE_AUXV): New define.
2020-03-13Add support for non-contiguous memory regionsChristophe Lyon2-0/+13
2020-01-06 Christophe Lyon <christophe.lyon@linaro.org> bfd/ * bfd-in2.h: Regenerate. * section.c (asection): Add already_assigned field. (BFD_FAKE_SECTION): Add default initializer for it. * ecoff.c (bfd_debug_section): Initialize already_assigned field. * elf32-arm.c (arm_build_one_stub): Add support for non_contiguous_regions. * elf32-csky.c (csky_build_one_stub): Likewise. * elf32-hppa.c (hppa_build_one_stub): Likewise. * elf32-m68hc11.c (m68hc11_elf_build_one_stub): Likewise. * elf32-m68hc12.c (m68hc12_elf_build_one_stub): Likewise. * elf32-metag.c (metag_build_one_stub): Likewise. * elf32-nios2.c (nios2_build_one_stub): Likewise. * elf64-ppc.c (ppc_build_one_stub): Likewise. (ppc_size_one_stub): Likewise. * elfnn-aarch64.c (aarch64_build_one_stub): Likewise. * elflink.c (elf_link_input_bfd): Likewise. include/ * bfdlink.h (bfd_link_info): Add non_contiguous_regions and non_contiguous_regions_warnings fields. ld/ * ldlang.c (lang_add_section): Add support for non_contiguous_regions. (size_input_section): Likewise. (lang_size_sections_1): Likewise. (process_insert_statements): Likewise. * ldlex.h (option_values): Add OPTION_NON_CONTIGUOUS_REGIONS and OPTION_NON_CONTIGUOUS_REGIONS_WARNINGS. * lexsup.c (ld_options): Add entries for --enable-non-contiguous-regions and --enable-non-contiguous-regions-warnings. (parse_args): Handle it. * NEWS: Add --enable-non-contiguous-regions and --enable-non-contiguous-regions-warnings. * ld.texi: Add --enable-non-contiguous-regions and --enable-non-contiguous-regions-warnings documentation. * emultempl/armelf.em (elf32_arm_add_stub_section): Add SEC_LINKER_CREATED flag. * emultempl/xtensaelf.em (ld_build_required_section_dependence): Emit an error when --enable-non-contiguous-regions is used. * testsuite/ld-elf/non-contiguous.d: New. * testsuite/ld-elf/non-contiguous.ld: New. * testsuite/ld-elf/non-contiguous.s: New. * testsuite/ld-arm/arm-elf.exp: Run the new tests. * testsuite/ld-arm/arm-elf/non-contiguous-arm.s: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm.ld: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm2.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm3.ld: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm3.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm3.ld: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm4.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm4.ld: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm5.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm5.ld: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm6.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm6.ld: New. * testsuite/ld-powerpc/powerpc.exp: Run new tests. * testsuite/ld-powerpc/non-contiguous-powerpc.d: New. * testsuite/ld-powerpc/non-contiguous-powerpc.ld: New. * testsuite/ld-powerpc/non-contiguous-powerpc.sd: New. * testsuite/ld-powerpc/non-contiguous-powerpc64.d: New.
2020-03-13Fix several mix up between octets and bytes in ELF program headersChristian Eggers3-5/+15
Fixes additional locations not handled in the first patch. When converting between addresses in ELF headers [octets] and bfd LMA/VMA [bytes], the number of octets per byte needs to be incorporated. include/ * bfdlink.h (struct bfd_link_order): Add unit (bytes/octets) to offset and size members. * elf/internal.h (struct elf_internal_phdr): Likewise for p_align member. (struct elf_segment_map): Likewise for p_paddr and p_size members bfd/ * bfd.c (bfd_record_phdr): New local "opb". Fix assignment of "p_paddr" from "at". * elfcode.h (bfd_from_remote_memory): Add units to several parameters. New local "opb". Fix usage of p_align. Fix calculation of "localbase" from "ehdr_vma" and "p_vaddr". Fix call of target_read_memory. * elflink.c (elf_fixup_link_order): Fix scope of "s" local. Fix calculation of "offset" and "output_offset". (bfd_elf_final_link): New local "opb". Fix calculation of "size" from "offset" and fix calculation of "end" from "vma+size". Fix comparison between "sh_addr" and "vma"/"output_offset". (bfd_elf_discard_info): Fix calculation of "eh_alignment". * elf-bfd.h (struct elf_link_hash_table): Add unit to tls_size member. * elf.c (_bfd_elf_map_sections_to_segments): Add unit (bytes/ octets) to "wrap_to2 and "phdr_size" locals. Fix calculation of "wrap_to" value. Add unit (bytes) to phdr_lma variable. Fix assignment of p_paddr from phdr_lma. Fix comparison between "lma+size" and "next->lma". (elf_sort_segments): Fix assignment from p_paddr to lma. (assign_file_positions_for_load_sections): Add unit (bytes) to local "align". Fix calculation of local "off_adjust". Fix calculation of local "filehdr_vaddr". (assign_file_positions_for_non_load_sections): New local "opb". Fix calculation of "end" from "p_size". Fix comparison between "vma+SECTION_SIZE" and "start". Fix calculation of "p_memsz" from "end" and "p_vaddr". (rewrite_elf_program_header): Fix comparison between p_vaddr and vma. Fix assignment to p_paddr from lma. Fix comparison between p_paddr and lma. Fix assignment to p_paddr from lma. * merge.c (sec_merge_emit): New local "opb". Convert "alignment_power" to octets. (_bfd_add_merge_section): New locals "alignment_power" and "opb". Fix comparison between "alignment_power" and "sizeof(align)". (_bfd_merge_sections): New local "opb". Divide size by opb before checking align mask.
2020-03-13Fix several mix up between octets and bytes in ELF program headersChristian Eggers2-12/+19
When converting between addresses in ELF headers [octets] and bfd LMA/VMA [bytes], the number of octets per byte needs to be incorporated. In ld, the SIZEOF_HEADERS linker script statement must be resolved to bytes instead of octets. include/ * elf/internal.h (struct elf_internal_phdr): Add unit (octets) to several member field comments. (Elf_Internal_Shdr): likewise. bfd/ * elf.c (_bfd_elf_make_section_from_shdr): Introduce new temp opb. Divide Elf_Internal_Shdr::sh_addr by opb when setting section LMA/VMA. (_bfd_elf_make_section_from_phdr): Similarly. (elf_fake_sections): Fix calculation of Elf_Internal_shdr::sh_addr from section VMA. (_bfd_elf_map_sections_to_segments): Fix mixup between octets and bytes. (assign_file_positions_for_load_sections): Fix calculations of Elf_Internal_shdr::p_vaddr and p_paddr from section LMA/VMA. Fix comparison between program header address and section LMA. (assign_file_positions_for_non_load_sections): Likewise. (rewrite_elf_program_header): Likewise. Introduce new temp opb. (IS_CONTAINED_BY_VMA): Add parameter opb. (IS_CONTAINED_BY_LMA,IS_SECTION_IN_INPUT_SEGMENT, INCLUDE_SECTION_IN_SEGMENT): Likewise. (copy_elf_program_header): Update call to ELF_SECTION_IN_SEGMENT. Fix calculations of p_addr_valid and p_vaddr_offset. * elflink.c (elf_link_add_object_symbols): Multiply section VMA with octets per byte when comparing against p_vaddr. ld/ * ldexp.c (fold_name): Return SIZEOF_HEADERS in bytes.
2020-03-10ubsan: som: left shift of 1 by 31 placesAlan Modra3-5/+11
* som/aout.h (SOM_AUX_ID_MANDATORY, SOM_SPACE_IS_LOADABLE), (SOM_SYMBOL_HIDDEN, SOM_SYMBOL_HAS_LONG_RETURN): Use 1u << 31. * som/lst.h (LST_SYMBOL_HIDDEN): Likewise.
2020-03-03Add missing AT tags to the ELF common header.Luis Machado2-0/+22
* elf/common.h (AT_L1I_CACHESIZE, AT_L1I_CACHEGEOMETRY) (AT_L1D_CACHESIZE, AT_L1D_CACHEGEOMETRY, AT_L2_CACHESIZE) (AT_L2_CACHEGEOMETRY, AT_L3_CACHESIZE, AT_L3_CACHEGEOMETRY) (AT_MINSIGSTKSZ): New defines, imported from glibc.
2020-02-25Merge upstream GCC changes for include/ and libiberty/ directoriesAndrew Burgess2-2/+10
This commit pulls in the latest changes for the include/ and libiberty/ directories. The last sync was in commit 533da48302a26885a972e4379eccc26b364e5b53. This commit also removes the file libiberty/rust-demangle.h, this file has been removed in upstream GCC, and should have been deleted as part of the previous sync up, which included this ChangeLog entry: 2019-11-16 Eduard-Mihai Burtescu <eddyb@lyken.rs> .... * rust-demangle.h: Remove. I've grep'd over the binutils-gdb source and can find no reference to the rust-demangle.h file, and everything seems to build fine without it, so I assume its continued existence was a mistake. include/ChangeLog: Import from gcc mainline: 2020-02-05 Andrew Burgess <andrew.burgess@embecosm.com> * hashtab.h (htab_remove_elt): Make a parameter const. (htab_remove_elt_with_hash): Likewise. libiberty/ChangeLog: * rust-demangle.h: Removed. Import from gcc mainline: 2020-02-05 Andrew Burgess <andrew.burgess@embecosm.com> * hashtab.c (htab_remove_elt): Make a parameter const. (htab_remove_elt_with_hash): Likewise. 2020-01-23 Alexandre Oliva <oliva@adacore.com> * argv.c (writeargv): Output empty args as "". 2020-01-18 Iain Sandoe <iain@sandoe.co.uk> * cp-demangle.c (cplus_demangle_operators): Add the co_await operator. * testsuite/demangle-expected: Test co_await operator mangling.
2020-02-20RISC-V: Support the ISA-dependent CSR checking.Nelson Chu2-244/+249
According to the riscv privilege spec, some CSR are only valid when rv32 or the specific extension is set. We extend the DECLARE_CSR and DECLARE_CSR_ALIAS to record more informaton we need, and then check whether the CSR is valid according to these information. We report warning message when the CSR is invalid, so we have a choice between error and warning by --fatal-warnings option. Also, a --no-warn/-W option is used to turn the warnings off, if people don't want the warnings. gas/ * config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide whether or not this CSR is legal in the current ISA string. (struct riscv_csr_extra): New structure to hold all extra information of CSR. (riscv_init_csr_hash): New function. According to the DECLARE_CSR and DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash. Call hash_reg_name to insert CSR address into reg_names_hash. (md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR. (reg_csr_lookup_internal, riscv_csr_class_check): New functions. Decide whether the CSR is valid according to the csr_extra_hash. (init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is not a boolean. This is same as riscv_init_csr_hash, so keep the consistent usage. * testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option. * testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option. * testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the f-ext CSR are not allowed. * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The source file is `priv-reg.s`, and the ISA is rv64if, so the rv32-only CSR are not allowed. * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. include/ * opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to record riscv_csr_class. opcodes/ * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed. gdb/ * riscv-tdep.c: Updated since the DECLARE_CSR is changed. * riscv-tdep.h: Likewise. * features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without rv32-only CSR. * features/riscv/64bit-csr.xml: Regernated. binutils/ * dwarf.c: Updated since the DECLARE_CSR is changed.
2020-02-10[binutils][arm] arm support for ARMv8.m Custom Datapath ExtensionMatthew Malcomson2-0/+22
This patch is part of a series that adds support for the Armv8.m ARMv8.m Custom Datapath Extension to binutils. This patch introduces the Custom Instructions Class 1/2/3 (Single/ Dual, Accumulator/Non-accumulator varianats) to the arm backend. The following Custom Instructions are added: cx1, cx1a, cx1d, cx1da, cx2, cx2a, cx2d, cx2da, cx3, cx3a, cx3d, cx3da. Specification can be found at https://developer.arm.com/docs/ddi0607/latest This patch distinguishes between enabling CDE for different coprocessor numbers by defining multiple architecture flags. This means that the parsing of the architecture extension flags is kept entirely in the existing code path. We introduce a new IT block state to indicate the behaviour of these instructions. This new state allows being used in an IT block or outside an IT block, but does not allow the instruction to be used inside a VPT block. We need this since the CX*A instruction versions can be used in IT blocks, but they aren't to have the conditional suffixes on them. Hence we need to mark an instruction as allowed in either position. We also need a new flag to objdump, in order to determine whether to disassemble an instruction as CDE related or not. Successfully regression tested on arm-none-eabi, and arm-wince-pe. gas/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (arm_ext_cde*): New feature sets for each CDE coprocessor that can be enabled. (enum pred_instruction_type): New pred type. (BAD_NO_VPT): New error message. (BAD_CDE): New error message. (BAD_CDE_COPROC): New error message. (enum operand_parse_code): Add new immediate operands. (parse_operands): Account for new immediate operands. (check_cde_operand): New. (cde_coproc_enabled): New. (cde_coproc_pos): New. (cde_handle_coproc): New. (cxn_handle_predication): New. (do_custom_instruction_1): New. (do_custom_instruction_2): New. (do_custom_instruction_3): New. (do_cx1): New. (do_cx1a): New. (do_cx1d): New. (do_cx1da): New. (do_cx2): New. (do_cx2a): New. (do_cx2d): New. (do_cx2da): New. (do_cx3): New. (do_cx3a): New. (do_cx3d): New. (do_cx3da): New. (handle_pred_state): Define new IT block behaviour. (insns): Add newn CX*{,d}{,a} instructions. (CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table): Define new cdecp extension strings. * doc/c-arm.texi: Document new cdecp extension arguments. * testsuite/gas/arm/cde-scalar.d: New test. * testsuite/gas/arm/cde-scalar.s: New test. * testsuite/gas/arm/cde-warnings.d: New test. * testsuite/gas/arm/cde-warnings.l: New test. * testsuite/gas/arm/cde-warnings.s: New test. * testsuite/gas/arm/cde.d: New test. * testsuite/gas/arm/cde.s: New test. include/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * opcode/arm.h (ARM_EXT2_CDE): New extension macro. (ARM_EXT2_CDE0): New extension macro. (ARM_EXT2_CDE1): New extension macro. (ARM_EXT2_CDE2): New extension macro. (ARM_EXT2_CDE3): New extension macro. (ARM_EXT2_CDE4): New extension macro. (ARM_EXT2_CDE5): New extension macro. (ARM_EXT2_CDE6): New extension macro. (ARM_EXT2_CDE7): New extension macro. opcodes/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (struct cdeopcode32): New. (CDE_OPCODE): New macro. (cde_opcodes): New disassembly table. (regnames): New option to table. (cde_coprocs): New global variable. (print_insn_cde): New (print_insn_thumb32): Use print_insn_cde. (parse_arm_disassembler_options): Parse coprocN args.
2020-02-07Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add ↵Sergey Belyashov3-0/+10
DWARF debug info support to the Z80 assembler. PR 25469 bfd * archures.c: Add GBZ80 and Z80N machine values. * reloc.c: Add BFD_RELOC_Z80_16_BE. * coff-z80.c: Add support for new reloc. * coffcode.h: Add support for new machine values. * cpu-z80.c: Add support for new machine names. * elf32-z80.c: Add support for new reloc. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. binutils* readelf.c (get_machine_flags): Add support for Z80N machine number. gas * config/tc-z80.c: Add -gbz80 command line option to generate code for the GameBoy Z80. Add support for generating DWARF. * config/tc-z80.h: Add support for DWARF debug information generation. * doc/c-z80.texi: Document new command line option. * testsuite/gas/z80/gbz80_all.d: New file. * testsuite/gas/z80/gbz80_all.s: New file. * testsuite/gas/z80/z80.exp: Run the new tests. * testsuite/gas/z80/z80n_all.d: New file. * testsuite/gas/z80/z80n_all.s: New file. * testsuite/gas/z80/z80n_reloc.d: New file. include * coff/internal.h (R_IMM16BE): Define. * elf/z80.h (EF_Z80_MACH_Z80N): Define. (R_Z80_16_BE): New reloc. ld * emulparams/elf32z80.sh: Use z80 emulation. * emultempl/z80.em: Make generic to both COFF and ELF Z80 emulations. * emultempl/z80elf.em: Delete. * testsuite/ld-elf/pr22450.d: Expect to fail for the Z80. * testsuite/ld-elf/sec64k.exp: Fix Z80 assembly. * testsuite/ld-unique/pr21529.s: Avoid register name conflict. * testsuite/ld-unique/unique.s: Likewise. * testsuite/ld-unique/unique_empty.s: Likewise. * testsuite/ld-unique/unique_shared.s: Likewise. * testsuite/ld-unique/unique.d: Updated expected output. * testsuite/ld-z80/arch_z80n.d: New file. * testsuite/ld-z80/comb_arch_z80_z80n.d: New file. * testsuite/ld-z80/labels.s: Add more labels. * testsuite/ld-z80/relocs.s: Add more reloc tests. * testsuite/ld-z80/relocs_f_z80n.d: New file opcodes * z80-dis.c: Add support for GBZ80 opcodes.
2020-02-04ubsan: d30v: negation of -2147483648Alan Modra2-1/+5
include/ * opcode/d30v.h (struct pd_reg): Make value field unsigned. opcodes/ * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2020-01-30Add some new PE_IMAGE_DEBUG_TYPE valuesJon Turney2-0/+11
IMAGE_DEBUG_TYPE_REPRO is defined in the latest version of the PE specification [1]. The others are defined in Windows SDK headers and/or reported by DUMPBIN. [1] https://docs.microsoft.com/en-us/windows/win32/debug/pe-format bfd/ChangeLog: 2020-01-16 Jon Turney <jon.turney@dronecode.org.uk> * peXXigen.c (debug_type_names): Add names for new debug data type values. include/ChangeLog: 2020-01-16 Jon Turney <jon.turney@dronecode.org.uk> * coff/internal.h (PE_IMAGE_DEBUG_TYPE_VC_FEATURE) (PE_IMAGE_DEBUG_TYPE_POGO, PE_IMAGE_DEBUG_TYPE_ILTCG) (PE_IMAGE_DEBUG_TYPE_MPX, PE_IMAGE_DEBUG_TYPE_REPRO): Add.
2020-01-18Add markers for 2.34 branch to the NEWS files and ChangeLogs.Nick Clifton1-0/+4
2020-01-17Update libiberty sources with changes in the gcc mainline.Nick Clifton4-24/+87
+2020-01-01 Jakub Jelinek <jakub@redhat.com> + + Update copyright years. + +2019-12-06 Tim Ruehsen <tim.ruehsen@gmx.de> + + * make-relative-prefix.c (split_directories): + Return early on empty 'name' + +2019-11-16 Tim Ruehsen <tim.ruehsen@gmx.de> + + * cp-demangle.c (d_print_init): Remove const from 4th param. + (cplus_demangle_fill_name): Initialize d->d_counting. + (cplus_demangle_fill_extended_operator): Likewise. + (cplus_demangle_fill_ctor): Likewise. + (cplus_demangle_fill_dtor): Likewise. + (d_make_empty): Likewise. + (d_count_templates_scopes): Remobe const from 3rd param, + Return on dc->d_counting > 1, + Increment dc->d_counting. + * cp-demint.c (cplus_demangle_fill_component): Initialize d->d_counting. + (cplus_demangle_fill_builtin_type): Likewise. + (cplus_demangle_fill_operator): Likewise. + +2019-11-16 Eduard-Mihai Burtescu <eddyb@lyken.rs> + + * cplus-dem.c (cplus_demangle): Use rust_demangle directly. + (rust_demangle): Remove. + * rust-demangle.c (is_prefixed_hash): Rename to is_legacy_prefixed_hash. + (parse_lower_hex_nibble): Rename to decode_lower_hex_nibble. + (parse_legacy_escape): Rename to decode_legacy_escape. + (rust_is_mangled): Remove. + (struct rust_demangler): Add. + (peek): Add. + (next): Add. + (struct rust_mangled_ident): Add. + (parse_ident): Add. + (rust_demangle_sym): Remove. + (print_str): Add. + (PRINT): Add. + (print_ident): Add. + (rust_demangle_callback): Add. + (struct str_buf): Add. + (str_buf_reserve): Add. + (str_buf_append): Add. + (str_buf_demangle_callback): Add. + (rust_demangle): Add. + * rust-demangle.h: Remove. + +2019-11-15 Miguel Saldivar <saldivarcher@gmail.com> + + * testsuite/demangle-expected: Fix test. + +2019-11-04 Kamlesh Kumar <kamleshbhalui@gmail.com> + + * cp-demangle.c (d_expr_primary): Handle + nullptr demangling. + * testsuite/demangle-expected: Added test. + +2019-10-29 Paul Pluzhnikov <ppluzhnikov@google.com> + + * cp-demangle.c (d_number): Avoid signed int overflow. + +2019-10-28 Miguel Saldivar <saldivarcher@gmail.com> + + * cp-demangle.c (d_print_mod): Add a space before printing `complex` + and `imaginary`, as opposed to after. + * testsuite/demangle-expected: Adjust test. + +2019-10-03 Eduard-Mihai Burtescu <eddyb@lyken.rs> + + * rust-demangle.c (looks_like_rust): Remove. + (rust_is_mangled): Don't check escapes. + (is_prefixed_hash): Allow 0-9a-f permutations. + (rust_demangle_sym): Don't bail on unknown escapes. + * testsuite/rust-demangle-expected: Update 'main::$99$' test. + +2019-09-03 Eduard-Mihai Burtescu <eddyb@lyken.rs> + + * rust-demangle.c (unescape): Remove. + (parse_lower_hex_nibble): New function. + (parse_legacy_escape): New function. + (is_prefixed_hash): Use parse_lower_hex_nibble. + (looks_like_rust): Use parse_legacy_escape. + (rust_demangle_sym): Use parse_legacy_escape. + * testsuite/rust-demangle-expected: Add 'llv$u6d$' test. + +2019-08-27 Martin Liska <mliska@suse.cz> + + PR lto/91478 + * simple-object-elf.c (simple_object_elf_copy_lto_debug_sections): + First find a WEAK HIDDEN symbol in symbol table that will be + preserved. Later, use the symbol name for all removed symbols. + +2019-08-12 Martin Liska <mliska@suse.cz> + + * Makefile.in: Add filedescriptor.c. + * filedescriptor.c: New file. + * lrealpath.c (is_valid_fd): Remove. diff --git a/libiberty/Makefile.in b/libiberty/Makefile.in index 0be45b4ae8..fe738d0db4 100644 --- a/libiberty/Makefile.in +++ b/libiberty/Makefile.in @@ -1,7 +1,7 @@ # Makefile for the libiberty library. # Originally written by K. Richard Pixley <rich@cygnus.com>. # -# Copyright (C) 1990-2019 Free Software Foundation, Inc. +# Copyright (C) 1990-2020 Free Software Foundation, Inc. # # This file is part of the libiberty library. # Libiberty is free software; you can redistribute it and/or @@ -127,7 +127,7 @@ CFILES = alloca.c argv.c asprintf.c atexit.c \ calloc.c choose-temp.c clock.c concat.c cp-demangle.c \ cp-demint.c cplus-dem.c crc32.c \ d-demangle.c dwarfnames.c dyn-string.c \ - fdmatch.c ffs.c fibheap.c filename_cmp.c floatformat.c \ + fdmatch.c ffs.c fibheap.c filedescriptor.c filename_cmp.c floatformat.c \ fnmatch.c fopen_unlocked.c \ getcwd.c getopt.c getopt1.c getpagesize.c getpwd.c getruntime.c \ gettimeofday.c \ @@ -171,6 +171,7 @@ REQUIRED_OFILES = \ ./cp-demint.$(objext) ./crc32.$(objext) ./d-demangle.$(objext) \ ./dwarfnames.$(objext) ./dyn-string.$(objext) \ ./fdmatch.$(objext) ./fibheap.$(objext) \ + ./filedescriptor.$(objext) \ ./filename_cmp.$(objext) ./floatformat.$(objext) \ ./fnmatch.$(objext) ./fopen_unlocked.$(objext) \ ./getopt.$(objext) ./getopt1.$(objext) ./getpwd.$(objext) \ @@ -756,6 +757,17 @@ $(CONFIGURED_OFILES): stamp-picdir stamp-noasandir else true; fi $(COMPILE.c) $(srcdir)/fibheap.c $(OUTPUT_OPTION) +./filedescriptor.$(objext): $(srcdir)/filedescriptor.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/filedescriptor.c -o pic/$@; \ + else true; fi + if [ x"$(NOASANFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(NOASANFLAG) $(srcdir)/filedescriptor.c -o noasan/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/filedescriptor.c $(OUTPUT_OPTION) + + ./filename_cmp.$(objext): $(srcdir)/filename_cmp.c config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \ $(INCDIR)/safe-ctype.h diff --git a/libiberty/_doprnt.c b/libiberty/_doprnt.c index d44dc415ed..a739f4304f 100644 --- a/libiberty/_doprnt.c +++ b/libiberty/_doprnt.c @@ -1,5 +1,5 @@ /* Provide a version of _doprnt in terms of fprintf. - Copyright (C) 1998-2019 Free Software Foundation, Inc. + Copyright (C) 1998-2020 Free Software Foundation, Inc. Contributed by Kaveh Ghazi (ghazi@caip.rutgers.edu) 3/29/98 This program is free software; you can redistribute it and/or modify it diff --git a/libiberty/argv.c b/libiberty/argv.c index 6444896f99..8c9794db6a 100644 --- a/libiberty/argv.c +++ b/libiberty/argv.c @@ -1,5 +1,5 @@ /* Create and destroy argument vectors (argv's) - Copyright (C) 1992-2019 Free Software Foundation, Inc. + Copyright (C) 1992-2020 Free Software Foundation, Inc. Written by Fred Fish @ Cygnus Support This file is part of the libiberty library. diff --git a/libiberty/asprintf.c b/libiberty/asprintf.c index 5718682f69..6e38e2234d 100644 --- a/libiberty/asprintf.c +++ b/libiberty/asprintf.c @@ -1,6 +1,6 @@ /* Like sprintf but provides a pointer to malloc'd storage, which must be freed by the caller. - Copyright (C) 1997-2019 Free Software Foundation, Inc. + Copyright (C) 1997-2020 Free Software Foundation, Inc. Contributed by Cygnus Solutions. This file is part of the libiberty library. diff --git a/libiberty/choose-temp.c b/libiberty/choose-temp.c index 72c1b710bd..49a2faaa51 100644 --- a/libiberty/choose-temp.c +++ b/libiberty/choose-temp.c @@ -1,5 +1,5 @@ /* Utility to pick a temporary filename prefix. - Copyright (C) 1996-2019 Free Software Foundation, Inc. + Copyright (C) 1996-2020 Free Software Foundation, Inc. This file is part of the libiberty library. Libiberty is free software; you can redistribute it and/or diff --git a/libiberty/clock.c b/libiberty/clock.c index a3730714bd..0de74657d0 100644 --- a/libiberty/clock.c +++ b/libiberty/clock.c @@ -1,5 +1,5 @@ /* ANSI-compatible clock function. - Copyright (C) 1994-2019 Free Software Foundation, Inc. + Copyright (C) 1994-2020 Free Software Foundation, Inc. This file is part of the libiberty library. This library is free software; you can redistribute it and/or modify it under the diff --git
2020-01-16[binutils][arm] PR25376 Change MVE into a CORE_HIGH featureAndre Vieira2-4/+11
This patch moves MVE feature bits into the CORE_HIGH section. This makes sure .fpu and -mfpu does not reset the bits set by MVE. This is important because .fpu has no option to "set" these same bits and thus, mimic'ing GCC, we choose to define MVE as an architecture extension rather than put it together with other the legacy fpu features. This will enable the following behavior: .arch armv8.1-m.main .arch mve .fpu fpv5-sp-d16 #does not disable mve. vadd.i32 q0, q1, q2 This patch also makes sure MVE is not taken into account during auto-detect. This was already the case, but because we moved the MVE bits to the architecture feature space we must make sure ARM_ANY does not include MVE. gas/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH. (armv8_1m_main_ext_table): Use CORE_HIGH for mve. * testsuite/arm/armv8_1-m-fpu-mve-1.s: New. * testsuite/arm/armv8_1-m-fpu-mve-1.d: New. * testsuite/arm/armv8_1-m-fpu-mve-2.s: New. * testsuite/arm/armv8_1-m-fpu-mve-2.d: New. include/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to... (ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space. (ARM_ANY): Redefine to not include any MVE bits. (ARM_FEATURE_ALL): Removed. opcodes/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits. (neon_opcodes): Likewise. (select_arm_features): Make sure we enable MVE bits when selecting armv8.1-m.main. Make sure we do not enable MVE bits when not selecting any architecture.
2020-01-15MSP430: Fix relocation overflow when using #lo(EXP) macroJozef Lawrynowicz2-0/+20
gas/ChangeLog: 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * config/tc-msp430.c (CHECK_RELOC_MSP430): Always generate 430X relocations when the target is 430X, except when extracting part of an expression. (msp430_srcoperand): Adjust comment. Initialize the expp member of the msp430_operand_s struct as appropriate. (msp430_dstoperand): Likewise. * testsuite/gas/msp430/msp430.exp: Run new test. * testsuite/gas/msp430/reloc-lo-430x.d: New test. * testsuite/gas/msp430/reloc-lo-430x.s: New test. include/ChangeLog: 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * opcode/msp430.h (enum msp430_expp_e): New. (struct msp430_operand_s): Add expp member to struct. ld/ChangeLog: 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * testsuite/ld-msp430-elf/msp430-elf.exp: Run new test. * testsuite/ld-msp430-elf/reloc-lo-430x.s: New test.
2020-01-13[ARC][committed] Update ARC cpu listClaudiu Zissulescu2-0/+8
include/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * elf/arc-cpu.def: Update ARC cpu list.
2020-01-13tic4x: sign extension using shiftsAlan Modra2-5/+13
Don't do that. Especially don't use shift counts that assume the type being shifted is 32 bits when the type is long/unsigned long. Also reverts part of a change I made on 2019-12-11 to tic4x_print_register that on closer inspection turns out to be unnecessary. include/ * opcode/tic4x.h (EXTR): Delete. (EXTRU, EXTRS, INSERTU, INSERTS): Rewrite without zero/sign extension using shifts. Do trim INSERTU value to specified bitfield. opcodes/ * tic4x-dis.c (tic4x_print_register): Remove dead code. gas/ * config/tc-tic4x.c (tic4x_operands_match): Correct tic3x trap insertion.
2020-01-10ubsan: spu: left shift of negative valueAlan Modra2-17/+29
Also fixes a real bug. The DECODE_INSN_I9a and DECODE_INSN_I9b both use UNSIGNED_EXTRACT for 7 low bits of the result, but this was an unsigned value due to "insn" being unsigned. DECODE_INSN_I9* is therefore unsigned too, leading to a zero extension in an expression using a bfd_vma if bfd_vma is 64 bits. * opcode/spu.h: Formatting. (UNSIGNED_EXTRACT): Use 1u. (SIGNED_EXTRACT): Don't sign extend with shifts. (DECODE_INSN_I9a, DECODE_INSN_I9b): Avoid left shift of signed value. Keep result signed. (DECODE_INSN_U9a, DECODE_INSN_U9b): Delete.
2020-01-07[ARC] Add finer details for LLOCK and SCONDShahab Vahedi2-0/+6
This patch changes the "class" of LLOCK/SCOND from "MEMORY" to "LLOCK/SCOND" respectively. Moreover, it corrects the "data_size_mode". These changes are necessary for GDB's atmoic sequence handler. Signed-off-by: Shahab Vahedi <shahab@synopsys.com>
2020-01-02Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. ↵Sergey Belyashov3-0/+62
Add an ELF based target for these as well. PR 25224 bfd * Makefile.am: Add z80-elf target support. * configure.ac: Likewise. * targets.c: Likewise. * config.bfd: Add z80-elf target support and new arches: ez80 and z180. * elf32-z80.c: New file. * archures.c: Add new z80 architectures: eZ80 and Z180. * coffcode.h: Likewise. * cpu-z80.c: Likewise. * bfd-in2.h: Likewise plus additional Z80 relocations. * coff-z80.c: Add new relocations for Z80 target and local label check. gas * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support for assembler code generated by SDCC. Add new relocation types. Add z80-elf target support. * config/tc-z80.h: Add z80-elf target support. Enable dollar local labels. Local labels starts from ".L". * testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict. * testsuite/gas/all/fwdexp.s: Likewise. * testsuite/gas/z80/suffix.d: Fix failure on ELF target. * testsuite/gas/z80/z80.exp: Add new tests * testsuite/gas/z80/dollar.d: New file. * testsuite/gas/z80/dollar.s: New file. * testsuite/gas/z80/ez80_adl_all.d: New file. * testsuite/gas/z80/ez80_adl_all.s: New file. * testsuite/gas/z80/ez80_adl_suf.d: New file. * testsuite/gas/z80/ez80_isuf.s: New file. * testsuite/gas/z80/ez80_z80_all.d: New file. * testsuite/gas/z80/ez80_z80_all.s: New file. * testsuite/gas/z80/ez80_z80_suf.d: New file. * testsuite/gas/z80/r800_extra.d: New file. * testsuite/gas/z80/r800_extra.s: New file. * testsuite/gas/z80/r800_ii8.d: New file. * testsuite/gas/z80/r800_z80_doc.d: New file. * testsuite/gas/z80/z180.d: New file. * testsuite/gas/z80/z180.s: New file. * testsuite/gas/z80/z180_z80_doc.d: New file. * testsuite/gas/z80/z80_doc.d: New file. * testsuite/gas/z80/z80_doc.s: New file. * testsuite/gas/z80/z80_ii8.d: New file. * testsuite/gas/z80/z80_ii8.s: New file. * testsuite/gas/z80/z80_in_f_c.d: New file. * testsuite/gas/z80/z80_in_f_c.s: New file. * testsuite/gas/z80/z80_op_ii_ld.d: New file. * testsuite/gas/z80/z80_op_ii_ld.s: New file. * testsuite/gas/z80/z80_out_c_0.d: New file. * testsuite/gas/z80/z80_out_c_0.s: New file. * testsuite/gas/z80/z80_reloc.d: New file. * testsuite/gas/z80/z80_reloc.s: New file. * testsuite/gas/z80/z80_sli.d: New file. * testsuite/gas/z80/z80_sli.s: New file. ld * Makefile.am: Add new target z80-elf * configure.tgt: Likewise. * emultempl/z80.em: Add support for eZ80 and Z180 architectures. * emulparams/elf32z80.sh: New file. * emultempl/z80elf.em: Likewise. * testsuite/ld-z80/arch_ez80_adl.d: Likewise. * testsuite/ld-z80/arch_ez80_z80.d: Likewise. * testsuite/ld-z80/arch_r800.d: Likewise. * testsuite/ld-z80/arch_z180.d: Likewise. * testsuite/ld-z80/arch_z80.d: Likewise. * testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z180.d: Likewise. * testsuite/ld-z80/labels.s: Likewise. * testsuite/ld-z80/relocs.s: Likewise. * testsuite/ld-z80/relocs_b_ez80.d: Likewise. * testsuite/ld-z80/relocs_b_z80.d: Likewise. * testsuite/ld-z80/relocs_f_z80.d: Likewise. * testsuite/ld-z80/z80.exp: Likewise. opcodes * z80-dis.c: Add support for eZ80 and Z80 instructions.
2020-01-02Enable building the s12z target on Solaris hosts where REG_Y is defined in ↵Nick Clifton2-10/+18
system header files. * opcode/s12z.h: Undef REG_Y.
2020-01-01Re: Update year range in copyright notice of binutils filesAlan Modra1-0/+4
Add the ChangeLog entry.
2020-01-01Update year range in copyright notice of binutils filesAlan Modra283-283/+283
2020-01-01ChangeLog rotationAlan Modra2-761/+775
2020-01-01Update copyright year range in all GDB files.Joel Brobecker22-22/+22
gdb/ChangeLog: Update copyright year range in all GDB files.
2019-12-17Remove tic80 supportAlan Modra3-406/+5
This is one way of fixing ubsan bug reports, just delete the code. The assembler support was removed back in 2005 along with other non-BFD assemblers, but somehow the remainder of the port stayed in. bfd/ * coff-tic80.c: Delete file. * cpu-tic80.c: Delete file. * archures.c: Remove tic80 support. * coffcode.h: Likewise. * coffswap.h: Likewise. * targets.c: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * Makefile.am: Likewise. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. binutils/ * testsuite/binutils-all/objcopy.exp: Remove tic80 support. * testsuite/binutils-all/objdump.exp: Likewise. gas/ * doc/as.texi: Remove mention of tic80. include/ * coff/tic80.h: Delete file. * opcode/tic80.h: Delete file. ld/ * emulparams/tic80coff.sh: Delete file. * scripttempl/tic80coff.sc: Delete file. * configure.tgt: Remove tic80 support. * Makefile.am: Likewise. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate. opcodes/ * tic80-dis.c: Delete file. * tic80-opc.c: Delete file. * disassemble.c: Remove tic80 support. * disassemble.h: Likewise. * Makefile.am: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
2019-12-16ubsan: crx: left shift cannot be represented in type 'int'Alan Modra2-1/+5
The ubsan complaint is fixed by the SBM change, with similar possible complaints fixed by the EXTRACT change. The rest is just cleanup. include/ * opcode/crx.h (inst <match>): Make unsigned int. opcodes/ * crx-dis.c (EXTRACT, SBM): Avoid signed overflow. (get_number_of_operands, getargtype, getbits, getregname), (getcopregname, getprocregname, gettrapstring, getcinvstring), (getregliststring, get_word_at_PC, get_words_at_PC, build_mask), (powerof2, match_opcode, make_instruction, print_arguments), (print_arg): Delete forward declarations, moving static to.. (getregname, getcopregname, getregliststring): ..these definitions. (build_mask): Return unsigned int mask. (match_opcode): Use unsigned int vars.
2019-12-16ubsan: nds32: left shift cannot be represented in type 'int'Alan Modra2-3/+10
Note that using 1u in N32_BIT makes all of N32_BIT, __MASK, __MF, __GF and __SEXT evaluate as unsigned int (the latter three when when their v arg is int or smaller). This would be a problem if assigning the result to a bfd_vma, long, or other type wider than an int since the __SEXT result would be zero extended to the wider type. Fortunately nds32 target code doesn't use wider types unnecessarily. include/ * opcode/nds32.h (N32_BIT): Define using 1u. (__SEXT): Use __MASK and N32_BIT. (N32_IMMS): Remove duplicate mask. opcodes/ * nds32-dis.c (print_insn16, print_insn32): Remove forward decls. (struct objdump_disasm_info): Delete. (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of N32_IMMS to unsigned before shifting left.
2019-12-12Fix unused function errorLuis Machado2-9/+5
Attempting to build GDB in Ubuntu 16.04.6 LTS on x86_64, I ran into warnings that caused the build to fail: binutils-gdb/gdb/gdbsupport/safe-strerror.c:44:1: error: ‘char* select_strerror_r(char*, char*)’ defined but not used [-Werror=unused-function] select_strerror_r (char *res, char *) The diagnostic macro DIAGNOSTIC_IGNORE_UNUSED_FUNCTION seems to expand correctly to its respective pragma, but this doesn't seem to have an effect on the warning. I tried to use the pragma explicitly and got the same result. ATTRIBUTE_UNUSED works fine in this case if you put it in both functions, which should fix warnings for both gdb and gdbserver builds. The compiler version is gcc (Ubuntu 5.4.0-6ubuntu1~16.04.11) 5.4.0 20160609. This is likely the result of PR64079 in GCC, which was fixed by commit 9e96f1e1b9731c4e1ef4fbbbf0997319973f0537. To prevent other developers from attempting to use this macro, only to get confused by it not working as expected, it seems better to not define this particular macro. gdb/ChangeLog: 2019-12-12 Luis Machado <luis.machado@linaro.org> * gdbsupport/safe-strerror.c: Don't include diagnostics.h. (select_strerror_r): Use ATTRIBUTE_UNUSED instead of the diagnostics macros. include/ChangeLog: 2019-12-12 Luis Machado <luis.machado@linaro.org> * diagnostics.h (DIAGNOSTIC_IGNORE_UNUSED_FUNCTION). Remove definitions. Change-Id: Iad6123d61d76d111e3ef8d24aa8c60112304c749
2019-12-11bfd signed overflow fixesAlan Modra2-8/+14
Aimed at quietening ubsan. include/ * opcode/mmix.h (PUSHGO_INSN_BYTE): Make unsigned. (GO_INSN_BYTE, SETL_INSN_BYTE, INCML_INSN_BYTE, INCMH_INSN_BYTE), (INCH_INSN_BYTE, SWYM_INSN_BYTE, JMP_INSN_BYTE): Likewise. bfd/ * elf32-rx.c (elf32_rx_relax_section): Avoid signed overflow. * libaout.h (N_SET_INFO, N_SET_FLAGS): Likewise. * netbsd.h (write_object_contents): Likewise. * elf32-arm.c (bfd_elf32_arm_vfp11_erratum_scan): Likewise. * libhppa.h (HPPA_R_CONSTANT): Don't signed extend with shifts. (stm32l4xx_create_replacing_stub_vldm): Don't truncate high bits with shifts. * elf32-nds32.h (R_NDS32_RELAX_ENTRY_DISABLE_RELAX_FLAG): Define using 1u shifted left. Ditto for other macros. * mmo.c (LOP): Make unsigned.
2019-12-11ubsan: left shift of cannot be represented in type 'int'Alan Modra3-22/+28
* dis-asm.h (INSN_HAS_RELOC, DISASSEMBLE_DATA), (USER_SPECIFIED_MACHINE_TYPE, WIDE_OUTPUT): Make unsigned. * opcode/tic80.h (TIC80_OPERAND_*): Likewise.
2019-12-10PR24960, Memory leak from disassemblerAlan Modra2-1/+9
PR 24960 include/ * dis-asm.h (disassemble_free_target): Declare. opcodes/ * disassemble.c (disassemble_free_target): New function. binutils/ * objdump.c (disassemble_data): Call disassemble_free_target.
2019-12-10Use disassemble_info.private_data in place of insn_setsAlan Modra2-8/+5
No cgen target uses private_data. This patch removes a disassemble_info field that is only used by cgen, and instead uses private_data. It also removes a macro that is no longer used. include/ * dis-asm.h (struct disassemble_info): Delete insn_sets. (INIT_DISASSEMBLE_INFO_NO_ARCH): Don't define. opcodes/ * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data. * disassemble.c (disassemble_init_for_target): Likewise. * bpf-dis.c: Regenerate. * epiphany-dis.c: Regenerate. * fr30-dis.c: Regenerate. * frv-dis.c: Regenerate. * ip2k-dis.c: Regenerate. * iq2000-dis.c: Regenerate. * lm32-dis.c: Regenerate. * m32c-dis.c: Regenerate. * m32r-dis.c: Regenerate. * mep-dis.c: Regenerate. * mt-dis.c: Regenerate. * or1k-dis.c: Regenerate. * xc16x-dis.c: Regenerate. * xstormy16-dis.c: Regenerate.
2019-12-05Arm64: simplify Crypto arch extension handlingJan Beulich2-1/+8
This, at the assembler level, is just a "brace" feature covering both AES and SHA2. Hence there's no need for it to have a separate feature flag, freeing up a bit for future re-use. Along these lines there are also a number of dead definitions/variables in the opcode table file.
2019-11-25Introduce new section flag: SEC_ELF_OCTETSChristian Eggers2-7/+12
All symbols, sizes and relocations in this section are octets instead of bytes. Required for DWARF debug sections as DWARF information is organized in octets, not bytes. bfd/ * section.c (struct bfd_section): New flag SEC_ELF_OCTETS. * archures.c (bfd_octets_per_byte): New parameter sec. If section is not NULL and SEC_ELF_OCTETS is set, one octet es returned [ELF targets only]. * bfd.c (bfd_get_section_limit): Provide section parameter to bfd_octets_per_byte. * bfd-in2.h: regenerate. * binary.c (binary_set_section_contents): Move call to bfd_octets_per_byte into section loop. Provide section parameter to bfd_octets_per_byte. * coff-arm.c (coff_arm_reloc): Provide section parameter to bfd_octets_per_byte. * coff-i386.c (coff_i386_reloc): likewise. * coff-mips.c (mips_reflo_reloc): likewise. * coff-x86_64.c (coff_amd64_reloc): likewise. * cofflink.c (_bfd_coff_link_input_bfd): likewise. (_bfd_coff_reloc_link_order): likewise. * elf.c (_bfd_elf_section_offset): likewise. (_bfd_elf_make_section_from_shdr): likewise. Set SEC_ELF_OCTETS for sections with names .gnu.build.attributes, .debug*, .zdebug* and .note.gnu*. * elf32-msp430.c (rl78_sym_diff_handler): Provide section parameter to bfd_octets_per_byte. * elf32-nds.c (nds32_elf_get_relocated_section_contents): likewise. * elf32-ppc.c (ppc_elf_addr16_ha_reloc): likewise. * elf32-pru.c (pru_elf32_do_ldi32_relocate): likewise. * elf32-s12z.c (opru18_reloc): likewise. * elf32-sh.c (sh_elf_reloc): likewise. * elf32-spu.c (spu_elf_rel9): likewise. * elf32-xtensa.c (bfd_elf_xtensa_reloc): likewise * elf64-ppc.c (ppc64_elf_brtaken_reloc): likewise. (ppc64_elf_addr16_ha_reloc): likewise. (ppc64_elf_toc64_reloc): likewise. * elflink.c (bfd_elf_final_link): likewise. (bfd_elf_perform_complex_relocation): likewise. (elf_fixup_link_order): likewise. (elf_link_input_bfd): likewise. (elf_link_sort_relocs): likewise. (elf_reloc_link_order): likewise. (resolve_section): likewise. * linker.c (_bfd_generic_reloc_link_order): likewise. (bfd_generic_define_common_symbol): likewise. (default_data_link_order): likewise. (default_indirect_link_order): likewise. * srec.c (srec_set_section_contents): likewise. (srec_write_section): likewise. * syms.c (_bfd_stab_section_find_nearest_line): likewise. * reloc.c (_bfd_final_link_relocate): likewise. (bfd_generic_get_relocated_section_contents): likewise. (bfd_install_relocation): likewise. For section which have SEC_ELF_OCTETS set, multiply output_base and output_offset with bfd_octets_per_byte. (bfd_perform_relocation): likewise. include/ * coff/ti.h (GET_SCNHDR_SIZE, PUT_SCNHDR_SIZE, GET_SCN_SCNLEN), (PUT_SCN_SCNLEN): Adjust bfd_octets_per_byte calls. binutils/ * objdump.c (disassemble_data): Provide section parameter to bfd_octets_per_byte. (dump_section): likewise (dump_section_header): likewise. Show SEC_ELF_OCTETS flag if set. gas/ * as.h: Define SEC_OCTETS as SEC_ELF_OCTETS if OBJ_ELF. * dwarf2dbg.c: (dwarf2_finish): Set section flag SEC_OCTETS for .debug_line, .debug_info, .debug_abbrev, .debug_aranges, .debug_str and .debug_ranges sections. * write.c (maybe_generate_build_notes): Set section flag SEC_OCTETS for .gnu.build.attributes section. * frags.c (frag_now_fix): Don't divide by OCTETS_PER_BYTE if SEC_OCTETS is set. * symbols.c (resolve_symbol_value): Likewise. ld/ * ldexp.c (fold_name): Provide section parameter to bfd_octets_per_byte. * ldlang (init_opb): New argument s. Set opb_shift to 0 if SEC_ELF_OCTETS for the current section is set. (print_input_section): Pass current section to init_opb. (print_data_statement,print_reloc_statement, print_padding_statement): Likewise. (lang_check_section_addresses): Call init_opb for each section. (lang_size_sections_1,lang_size_sections_1, lang_do_assignments_1): Likewise. (lang_process): Pass NULL to init_opb.
2019-11-22Arm: Change CRC from fpu feature to archititectural extensionMihail Ionescu2-16/+26
This patch changes the CRC extension to use the core feature bits instead of the coproc/fpu feature bits. CRC is not an fpu feature and it causes issues with the new fpu reset patch (f439988037a589de3798f44e7268301adaec21a9). CRC can be set using the '.arch_extension' directive, which sets bits in the coproc bitfield. When a '.fpu' directive is encountered, the CRC feature bit gets removed and there is no way to set it back using '.fpu'. With this patch, CRC will be marked in the feature core bits, which prevents it from getting removed when setting/changing the fpu options. gas/ChangeLog: * config/tc-arm.c (arm_ext_crc): New. (crc_ext_armv8): Remove. (insns): Rename crc_ext_armv8 to arm_ext_crc. (arm_cpus): Replace CRC_EXT_ARMV8 with ARM_EXT2_CRC. (armv8a_ext_table, armv8r_ext_table, arm_option_extension_value_table): Redefine the crc extension in terms of ARM_EXT2_CRC. * gas/testsuite/gas/arm/crc-ext.s: New. * gas/testsuite/gas/arm/crc-ext.d: New. include/ChangeLog: * opcode/arm.h (ARM_EXT2_CRC): New extension feature to replace CRC_EXT_ARMV8. (CRC_EXT_ARMV8): Remove and mark bit as unused. (ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A, ARM_ARCH_V8_3A, ARM_ARCH_V8_4A, ARM_ARCH_V8_5A, ARM_ARCH_V8_6A): Redefine using ARM_EXT2_CRC instead of CRC_EXT_ARMV8. opcodes/ChangeLog: * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes): Change the coproc CRC conditions to use the extension feature set, second word, base on ARM_EXT2_CRC.
2019-11-18gas: Add --gdwarf-cie-version command line flagAndrew Burgess2-1/+4
Add a flag to control the version of CIE that is generated. By default gas produces CIE version 1, and this continues to be the default after this patch. However, a user can now provide --gdwarf-cie-version=NUMBER to switch to either version 3 or version 4 of CIE, version 2 was never released, and so causes an error as does any number less than 1 or greater than 4. Producing version 4 CIE requires two new fields to be added to the CIE, an address size field, and an segment selector field. For a flat address space the DWARF specification indicates that the segment selector should be 0, and the address size fields just contains the address size in bytes. For now we support 4 or 8 byte addresses, and the segment selector is always produced as 0. At some future time we might need to allow targets to override this. gas/ChangeLog: * as.c (parse_args): Parse --gdwarf-cie-version option. (flag_dwarf_cie_version): New variable. * as.h (flag_dwarf_cie_version): Declare. * dw2gencfi.c (output_cie): Switch from DW_CIE_VERSION to flag_dwarf_cie_version. * doc/as.texi (Overview): Document --gdwarf-cie-version. * NEWS: Likewise. * testsuite/gas/cfi/cfi.exp: Add new tests. * testsuite/gas/cfi/cie-version-0.d: New file. * testsuite/gas/cfi/cie-version-1.d: New file. * testsuite/gas/cfi/cie-version-2.d: New file. * testsuite/gas/cfi/cie-version-3.d: New file. * testsuite/gas/cfi/cie-version-4.d: New file. * testsuite/gas/cfi/cie-version.s: New file. include/ChangeLog: * dwarf2.h (DW_CIE_VERSION): Delete. Change-Id: I9de19461aeb8332b5a57bbfe802953d0725a7ae8
2019-11-07[Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]Matthew Malcomson2-0/+5
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the Matrix Multiply (Int8, F32, F64) extensions to the arm backend. The following Matrix Multiply instructions are added: vummla, vsmmla, vusmmla, vusdot, vsudot[1]. [1]https://developer.arm.com/docs/ddi0597/latest/simd-and-floating-point-instructions-alphabetic-order Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-arm.c (arm_ext_i8mm): New feature set. (do_vusdot): New. (do_vsudot): New. (do_vsmmla): New. (do_vummla): New. (insns): Add vsmmla, vummla, vusmmla, vusdot, vsudot mnemonics. (armv86a_ext_table): Add i8mm extension. (arm_extensions): Move bf16 extension to context sensitive table. (armv82a_ext_table, armv84a_ext_table, armv85a_ext_table): Move bf16 extension to context sensitive table. (armv86a_ext_table): Add i8mm extension. * doc/c-arm.texi: Document i8mm extension. * testsuite/gas/arm/i8mm.s: New test. * testsuite/gas/arm/i8mm.d: New test. * testsuite/gas/arm/bfloat17-cmdline-bad-3.d: Update test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcode/arm.h (ARM_EXT2_I8MM): New feature macro. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions. Regression tested on arm-none-eabi. Is this ok for trunk? Regards, Mihail
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson2-1/+18
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the Matrix Multiply (Int8, F32, F64) extensions to the aarch64 backend. The following instructions are added: {s/u}mmla, usmmla, {us/su}dot, fmmla, ld1rob, ld1roh, d1row, ld1rod, uzip{1/2}, trn{1/2}. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-aarch64.c: Add new arch fetures to suppport the mm extension. (parse_operands): Add new operand. * testsuite/gas/aarch64/i8mm.s: New test. * testsuite/gas/aarch64/i8mm.d: New test. * testsuite/gas/aarch64/f32mm.s: New test. * testsuite/gas/aarch64/f32mm.d: New test. * testsuite/gas/aarch64/f64mm.s: New test. * testsuite/gas/aarch64/f64mm.d: New test. * testsuite/gas/aarch64/sve-movprfx-mm.s: New test. * testsuite/gas/aarch64/sve-movprfx-mm.d: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_I8MM): New. (AARCH64_FEATURE_F32MM): New. (AARCH64_FEATURE_F64MM): New. (AARCH64_OPND_SVE_ADDR_RI_S4x32): New. (enum aarch64_insn_class): Add new instruction class "aarch64_misc" for instructions that do not require special handling. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve, aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm, aarch64_feature_f64mm): New feature sets. (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN, F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply instructions. (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set macros. (QL_MMLA64, OP_SVE_SBB): New qualifiers. (OP_SVE_QQQ): New qualifier. (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC, F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support the movprfx constraint. (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32. (aarch64_opcode_table): Define new instructions smmla, ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod uzip{1/2}, trn{1/2}. * aarch64-opc.c (operand_general_constraint_met_p): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32. (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32. * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode): Account for new instructions. * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new S4x32 operand. * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand. Regression tested on arm-none-eabi. Is it ok for trunk? Regards, Mihail
2019-11-07[binutils][arm] BFloat16 enablement [4/X]Matthew Malcomson2-0/+14
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces BFloat16 instructions to the arm backend. The following BFloat16 instructions are added: vdot, vfma{l/t}, vmmla, vfmal{t/b}, vcvt, vcvt{t/b}. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (arm_archs): Add armv8.6-a option. (cpu_arch_ver): Add TAG_CPU_ARCH_V8 tag for Armv8.6-a. * doc/c-arm.texi (-march): New armv8.6-a arch. * config/tc-arm.c (arm_ext_bf16): New feature set. (enum neon_el_type): Add NT_bfloat value. (B_MNEM_vfmat, B_MNEM_vfmab): New bfloat16 encoder helpers. (BAD_BF16): New message. (parse_neon_type): Add bf16 type specifier. (enum neon_type_mask): Add N_BF16 type. (type_chk_of_el_type): Account for NT_bfloat. (el_type_of_type_chk): Account for N_BF16. (neon_three_args): Split out from neon_three_same. (neon_three_same): Part split out into neon_three_args. (CVT_FLAVOUR_VAR): Add bf16_f32 cvt flavour. (do_neon_cvt_1): Account for vcvt.bf16.f32. (do_bfloat_vmla): New. (do_mve_vfma): New function to deal with the mnemonic clash between the BF16 vfmat and the MVE vfma in a VPT block with a 't'rue condition. (do_neon_cvttb_1): Account for vcvt{t,b}.bf16.f32. (do_vdot): New (do_vmmla): New (insns): Add vdot and vmmla mnemonics. (arm_extensions): Add "bf16" extension. * doc/c-arm.texi: Document "bf16" extension. * testsuite/gas/arm/attr-march-armv8_6-a.d: New test. * testsuite/gas/arm/bfloat16-bad.d: New test. * testsuite/gas/arm/bfloat16-bad.l: New test. * testsuite/gas/arm/bfloat16-bad.s: New test. * testsuite/gas/arm/bfloat16-cmdline-bad-2.d: New test. * testsuite/gas/arm/bfloat16-cmdline-bad-3.d: New test. * testsuite/gas/arm/bfloat16-cmdline-bad.d: New test. * testsuite/gas/arm/bfloat16-neon.s: New test. * testsuite/gas/arm/bfloat16-non-neon.s: New test. * testsuite/gas/arm/bfloat16-thumb-bad.d: New test. * testsuite/gas/arm/bfloat16-thumb-bad.l: New test. * testsuite/gas/arm/bfloat16-thumb.d: New test. * testsuite/gas/arm/bfloat16-vfp.d: New test. * testsuite/gas/arm/bfloat16.d: New test. * testsuite/gas/arm/bfloat16.s: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/arm.h (ARM_EXT2_V8_6A, ARM_AEXT2_V8_6A, ARM_ARCH_V8_6A): New. * opcode/arm.h (ARM_EXT2_BF16): New feature macro. (ARM_AEXT2_V8_6A): Include above macro in definition. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with Armv8.6-A. (coprocessor_opcodes): Add bfloat16 vcvt{t,b}. (neon_opcodes): Add bfloat SIMD instructions. (print_insn_coprocessor): Add new control character %b to print condition code without checking cp_num. (print_insn_neon): Account for BFloat16 instructions that have no special top-byte handling. Regression tested on arm-none-eabi. Is it ok for trunk? Regards, Mihail
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson2-5/+21
Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the following BFloat16 instructions to the aarch64 backend: bfdot, bfmmla, bfcvt, bfcvtnt, bfmlal[t/b], bfcvtn2. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (vectype_to_qualifier): Special case the S_2H operand qualifier. * doc/c-aarch64.texi: Document bf16 and bf16mmla4 extensions. * testsuite/gas/aarch64/bfloat16.d: New test. * testsuite/gas/aarch64/bfloat16.s: New test. * testsuite/gas/aarch64/illegal-bfloat16.d: New test. * testsuite/gas/aarch64/illegal-bfloat16.l: New test. * testsuite/gas/aarch64/illegal-bfloat16.s: New test. * testsuite/gas/aarch64/sve-bfloat-movprfx.s: New test. * testsuite/gas/aarch64/sve-bfloat-movprfx.d: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_BFLOAT16): New feature macros. (AARCH64_ARCH_V8_6): Include BFloat16 feature macros. (enum aarch64_opnd_qualifier): Introduce new operand qualifier AARCH64_OPND_QLF_S_2H. (enum aarch64_insn_class): Introduce new class "bfloat16". (BFLOAT16_SVE_INSNC): New feature set for bfloat16 instructions to support the movprfx constraint. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H in reglane special case. * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode): Account for new instructions. * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H in reglane special case. * aarch64-opc.c (struct operand_qualifier_data): Add data for new AARCH64_OPND_QLF_S_2H qualifier. * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2, QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers. (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve, aarch64_feature_bfloat16_bfmmla4): New feature sets. (BFLOAT_SVE, BFLOAT): New feature set macros. (BFLOAT_SVE_INSN, BFLOAT_BFMMLA4_INSN, BFLOAT_INSN): New macros to define BFloat16 instructions. (aarch64_opcode_table): Define new instructions bfdot, bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t] bfcvtn2, bfcvt. Regression tested on aarch64-elf. Is it ok for trunk? Regards, Mihail
2019-11-07[gas][aarch64] Armv8.6-a option [1/X]Matthew Malcomson2-1/+9
Hi, This patch is part of a series that adds support for Armv8.6-A to binutils. This first patch adds the Armv8.6-A flag to binutils. No instructions are behind it at the moment. Commited on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (armv8.6-a): New arch. * doc/c-aarch64.texi (armv8.6-a): Document new arch. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_V8_6): New. (AARCH64_ARCH_V8_6): New. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-tbl.h (ARMV8_6): New macro. Is it ok for trunk? Regards, Mihail
2019-11-07Remove CR16C supportAlan Modra2-258/+4
I think it is past time to remove CR16C support. CR16C was added in 2004, and only for ld. gas and binutils support is lacking, and there have been no commits to bfd/elf32-cr16c.c other than warning fixes or global maintainers making changes to all targets. I see no maintainer listed for CR16C, and no commits from anyone at NSC supporting the target. Furthermore, at the time the CR16 support was added in 2007, config.sub was changed upstream to no longer recognise cr16c as a valid cpu. That means the CR16C ld support is only available as a secondary target by configuring with, for example, --enable-targets=all or --enable-targets=cr16c-unknown-elf. No testing of the CR16C target is possible. include/ * elf/cr16c.h: Delete. bfd/ * cpu-cr16c.c: Delete. * elf32-cr16c.c: Delete. * Makefile.am, * archures.c, * config.bfd, * configure.ac, * reloc.c, * targets.c: Remove cr16c support. * Makefile.in, * bfd-in2.h, * configure, * libbfd.h, * po/SRC-POTFILES.in: Regenerate. ld/ * emulparams/elf32cr16c.sh: Delete. * scripttempl/elf32cr16c.sc: Delete. * Makefile.am, * configure.tgt: Remove cr16c support. * NEWS: Mention removal of cr16c. * Makefile.in, * po/BLD-POTFILES.in: Regenerate.
2019-10-29Fix the size of the dos_message field in the internal_extra_pe_filehdr ↵Andrew Eikum2-1/+6
structure on hosts where sizeof(long) == 8. * coff/internal.h (struct internal_extra_pe_filehdr): Use ints instead of longs to hold dos_message.
2019-10-25PR4499, assign file positions assumes segment offsets increasingAlan Modra2-2/+13
This rewrites much of assign_file_positions_for_non_load_sections to allow objcopy and strip to handle cases like that in PR4499 where program headers were not in their usual position immediately after the ELF file header, and PT_LOAD headers were not sorted by paddr. PR 4499 include/ * elf/internal.h (struct elf_segment_map): Delete header_size. Add no_sort_lma and idx. bfd/ * elf-nacl.c (nacl_modify_segment_map): Set no_sort_lma for all PT_LOAD segments. * elf32-spu.c (spu_elf_modify_segment_map): Likewise on overlay PT_LOAD segments. * elf.c (elf_sort_segments): New function. (assign_file_positions_except_relocs): Use shortcuts to elfheader and elf_tdata. Seek to e_phoff not sizeof_ehdr to write program headers. Move PT_PHDR check.. (assign_file_positions_for_non_load_sections): ..and code setting PT_PHDR p_vaddr and p_paddr, and code setting __ehdr_start value.. (assign_file_positions_for_load_sections): ..to here. Sort PT_LOAD headers. Delete header_pad code. Use actual number of headers rather than allocated in calculating size for program headers. Don't assume program headers follow ELF file header. Simplify pt_load_count code. Only set "off" for PT_LOAD or PT_NOTE in cores. (rewrite_elf_program_header): Set p_vaddr_offset for segments that include file and program headers. (copy_elf_program_header): Likewise, replacing header_size code.
2019-10-16PR13616, linker should pad executable sections with nops, not zerosAlan Modra2-0/+9
This implements padding of orphan executable sections for PowerPC. Of course, the simple implementation of bfd_arch_ppc_nop_fill and removing the NOP definition didn't work, with powerpc64 hitting a testsuite failure linking to S-records. That's because the srec target is BFD_ENDIAN_UNKNOWN so the test of bfd_big_endian (abfd) in default_data_link_order therefore returned false, resulting in a little-endian nop pattern. The rest of the patch fixes that problem by adding a new field to bfd_link_info that can be used to determine actual endianness on targets like srec. PR 13616 include/ * bfdlink.h (struct bfd_link_info <big_endian>): New field. bfd/ * cpu-powerpc.c (bfd_arch_ppc_nop_fill): New function, use it for all ppc arch info. * linker.c (default_data_link_order): Pass info->big_endian to arch_info->fill function. ld/ * emulparams/elf64lppc.sh (NOP): Don't define. * emulparams/elf64ppc.sh (NOP): Don't define. * ldwrite.c (build_link_order): Use link_info.big_endian. Move code determining endian to use for data_statement to.. * ldemul.c (after_open_default): ..here. Set link_info.big_endian.
2019-10-07Add support for new functionality in the msp430 backend of GCC.Jozef Lawrynowicz2-0/+46
This functionality will generate a new GNU object attribute for the "data region" has been added. This object attribute is used mark whether the compiler has generated code assuming that data could be in the upper or lower memory regions. Code which assumes data is always in the lower memory region is incompatible with code which uses the full memory range for data. The patch also adds a new assembler directive ".mspabi_attribute" to handle the existing MSPABI object attributes. GCC will now emit both .gnu_attribute and .mspabi_attribute directives to indicate what options the source file was compiled with. The assembler will now check the values set in these directives against the options that the it has been invoked with. If there is a discrepancy, the assembler will exit with an error. bfd * elf32-msp430.c (elf32_msp430_merge_mspabi_attributes): Rename to.. (elf32_msp430_merge_msp430_attributes): Add support for merging the GNU object attribute for data region. binutils* readelf.c (display_msp430_gnu_attribute): New. (process_arch_specific): Use msp430 specific handler for GNU attributes. gas * config/tc-msp430.c (md_parse_option): Set lower_data_region_only to FALSE if the data region is set to "upper", "either" or "none". (msp430_object_attribute): New. (md_pseudo_table): Handle .mspabi_attribute and .gnu_attribute. (msp430_md_end): Replace hard-coded attribute values with enums. Handle data region object attribute. * doc/as.texi: Document MSP430 Data Region object attribute. * doc/c-msp430.texi: Document the .mspabi_attribute directive. * testsuite/gas/msp430/attr-430-small-bad.d: New test. * testsuite/gas/msp430/attr-430-small-bad.l: New test. * testsuite/gas/msp430/attr-430-small-good.d: New test. * testsuite/gas/msp430/attr-430-small.s: New test. * testsuite/gas/msp430/attr-430x-large-any-bad.d: New test. * testsuite/gas/msp430/attr-430x-large-any-bad.l: New test. * testsuite/gas/msp430/attr-430x-large-any-good.d: New test. * testsuite/gas/msp430/attr-430x-large-any.s: New test. * testsuite/gas/msp430/attr-430x-large-lower-bad.d: New test. * testsuite/gas/msp430/attr-430x-large-lower-bad.l: New test. * testsuite/gas/msp430/attr-430x-large-lower-good.d: New test. * testsuite/gas/msp430/attr-430x-large-lower.s: New test. * testsuite/gas/msp430/msp430.exp: Run new tests. include * elf/msp430.h: Add enums for MSPABI and GNU object attribute tag names and values. ld * testsuite/ld-msp430-elf/attr-gnu-main.s: New test. * testsuite/ld-msp430-elf/attr-gnu-obj.s: New test. * testsuite/ld-msp430-elf/attr-gnu-region-lower-upper.d: New test. * testsuite/ld-msp430-elf/attr-gnu-region-lower.d: New test. * testsuite/ld-msp430-elf/attr-gnu-region-upper.d: New test. * testsuite/ld-msp430-elf/msp430-elf.exp: Run new tests.
2019-10-03libctf: remove ctf_malloc, ctf_free and ctf_strdupNick Alcock2-2/+7
These just get in the way of auditing for erroneous usage of strdup and add a huge irregular surface of "ctf_malloc or malloc? ctf_free or free? ctf_strdup or strdup?" ctf_malloc and ctf_free usage has not reliably matched up for many years, if ever, making the whole game pointless. Go back to malloc, free, and strdup like everyone else: while we're at it, fix a bunch of places where we weren't properly checking for OOM. This changes the interface of ctf_cuname_set and ctf_parent_name_set, which could strdup but could not return errors (like ENOMEM). New in v4. include/ * ctf-api.h (ctf_cuname_set): Can now fail, returning int. (ctf_parent_name_set): Likewise. libctf/ * ctf-impl.h (ctf_alloc): Remove. (ctf_free): Likewise. (ctf_strdup): Likewise. * ctf-subr.c (ctf_alloc): Remove. (ctf_free): Likewise. * ctf-util.c (ctf_strdup): Remove. * ctf-create.c (ctf_serialize): Use malloc, not ctf_alloc; free, not ctf_free; strdup, not ctf_strdup. (ctf_dtd_delete): Likewise. (ctf_dvd_delete): Likewise. (ctf_add_generic): Likewise. (ctf_add_function): Likewise. (ctf_add_enumerator): Likewise. (ctf_add_member_offset): Likewise. (ctf_add_variable): Likewise. (membadd): Likewise. (ctf_compress_write): Likewise. (ctf_write_mem): Likewise. * ctf-decl.c (ctf_decl_push): Likewise. (ctf_decl_fini): Likewise. (ctf_decl_sprintf): Likewise. Check for OOM. * ctf-dump.c (ctf_dump_append): Use malloc, not ctf_alloc; free, not ctf_free; strdup, not ctf_strdup. (ctf_dump_free): Likewise. (ctf_dump): Likewise. * ctf-open.c (upgrade_types_v1): Likewise. (init_types): Likewise. (ctf_file_close): Likewise. (ctf_bufopen_internal): Likewise. Check for OOM. (ctf_parent_name_set): Likewise: report the OOM to the caller. (ctf_cuname_set): Likewise. (ctf_import): Likewise. * ctf-string.c (ctf_str_purge_atom_refs): Use malloc, not ctf_alloc; free, not ctf_free; strdup, not ctf_strdup. (ctf_str_free_atom): Likewise. (ctf_str_create_atoms): Likewise. (ctf_str_add_ref_internal): Likewise. (ctf_str_remove_ref): Likewise. (ctf_str_write_strtab): Likewise.
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