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AgeCommit message (Expand)AuthorFilesLines
2021-12-04sim: reorder header includesMike Frysinger1-2/+3
2021-12-02aarch64: Add BC instructionRichard Sandiford1-1/+3
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford1-7/+25
2021-12-02aarch64: Add support for +mopsRichard Sandiford1-1/+6
2021-12-02aarch64: Add support for Armv8.8-ARichard Sandiford1-0/+3
2021-12-02aarch64: Tweak insn sequence codeRichard Sandiford1-7/+5
2021-12-02gdb, include: replace pragmas with DIAGNOSTIC macros, fix build with g++ 4.8Simon Marchi1-0/+16
2021-12-01readelf: recognize FDO Packaging Metadata ELF noteLuca Boccassi1-0/+3
2021-12-01Fix the fields in the x_n union inside the the x_file structure so that point...Nick Clifton2-5/+15
2021-11-30RISC-V: The vtype immediate with more than the defined 8 bits are preserved.Nelson Chu1-2/+0
2021-11-26opcodes/riscv: add disassembler options support to libopcodesAndrew Burgess2-0/+6
2021-11-23AArch64: Add support for AArch64 EFI (efi-*-aarch64).Tamar Christina2-0/+64
2021-11-19RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC.Nelson Chu1-0/+6
2021-11-18RISC-V: Add instructions and operand set for z[fdq]inxjiawei1-0/+3
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus1-0/+1
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus1-0/+3
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus1-1/+11
2021-11-17aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus1-0/+1
2021-11-17aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus1-0/+14
2021-11-17aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus1-0/+4
2021-11-17aarch64: [SME] Add +sme option to -marchPrzemyslaw Wirkus1-0/+3
2021-11-17RISC-V: Support rvv extension with released version 1.0.Nelson Chu2-0/+1354
2021-11-16readelf: Support SHT_RELR/DT_RELR for -rFangrui Song3-1/+15
2021-11-16sim: callback: expose argv & environMike Frysinger1-0/+6
2021-11-16RISC-V: Scalar crypto instructions and operand set.jiawei2-0/+93
2021-11-15PowerPC64 @notoc in non-power10 codeAlan Modra1-0/+1
2021-11-10PR 28447: implement multiple parameters for .file on XCOFFClément Chigot3-11/+21
2021-11-06readelf: Support RELR in -S and -d and outputFangrui Song1-0/+4
2021-11-01arm: add armv9-a architecture to -marchPrzemyslaw Wirkus2-12/+25
2021-10-24LoongArch opcodes supportliuzhensong2-0/+240
2021-10-24LoongArch bfd supportliuzhensong2-1/+130
2021-10-07RISC-V: Add support for Zbs instructionsPhilipp Tomsich2-0/+25
2021-09-30aarch64: add armv9-a architecture to -marchPrzemyslaw Wirkus1-0/+5
2021-09-30Add Solaris specific ELF note processingLibor Bukata1-0/+23
2021-09-07Revert: [AArch64] MTE corefile supportLuis Machado2-6/+9
2021-09-02obstack.h __PTR_ALIGN vs. ubsanAlan Modra1-3/+3
2021-08-30RISC-V: PR27916, Support mapping symbols.Nelson Chu1-0/+7
2021-08-17sim: rename ChangeLog files to ChangeLog-2021Mike Frysinger1-0/+0
2021-08-17PATCH [4/4] arm: Add Tag_PACRET_use build attributeAndrea Corallo1-0/+1
2021-08-17PATCH [3/4] arm: Add Tag_BTI_use build attributeAndrea Corallo1-0/+1
2021-08-17PATCH [2/4] arm: Add Tag_BTI_extension build attributeAndrea Corallo1-0/+1
2021-08-17PATCH [1/4] arm: Add Tag_PAC_extension build attributeAndrea Corallo1-0/+1
2021-08-11Add 3 new PAC-related ARM note typesLuis Machado1-0/+9
2021-07-26PATCH [6/10] arm: Add -march=armv8.1-m.main+pacbti flagAndrea Corallo1-0/+7
2021-07-26PATCH [5/10] arm: Extend again arm_feature_set struct to provide more bitsAndrea Corallo1-4/+16
2021-07-08elf: Add GNU_PROPERTY_1_NEEDED checkH.J. Lu1-4/+19
2021-07-08elf: Add GNU_PROPERTY_1_NEEDEDH.J. Lu1-0/+7
2021-07-08ld: Limit cache size and add --max-cache-size=SIZEH.J. Lu1-0/+7
2021-07-06RISC-V: Add PT_RISCV_ATTRIBUTES and add it to PHDR.Kito Cheng1-0/+5
2021-07-03Add markers for 2.37 branchNick Clifton1-0/+4
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