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2020-04-23arc: Add support for ARC HS extra registers in core filesAnton Kolesov2-0/+6
When a coredump is generated, there are a few registers in ARC HS that are put under a special section, namely ".reg-v2". It is for backward compatibility reasons with older tools that we have decided not to extend the generic ".reg" section. This patch makes it possible to display the information better regarding that section. Compare the output of "readelf" without and with these changes: $ readelf -n core # without the patch ... LINUX 0x0000000c Unknown note type: (0x00000600) description data: 78 08 00 00 2f 6c 64 2d 75 43 6c 69 $ readelf -n core # with the patch ... LINUX 0x0000000c NT_ARC_V2 (ARC HS accumulator/extra registers) description data: 78 08 00 00 2f 6c 64 2d 75 43 6c 69 In another commit (soon to be submitted), GDB will makes use of these changes to parse the extra section and its registers. bfd/ChangeLog 2020-03-26 Anton Kolesov <anton.kolesov@synopsys.com> * elf-bfd.h (elfcore_write_arc_v2): Add prototype. * elf.c (elfcore_grok_arc_v2): New function. (elfcore_grok_note): Call the new function to handle the corresponding note. (elfcore_write_arc_v2): New function. (elfcore_write_register_note): Call the new function to handle the corresponding pseudo-sections. binutils/ChangeLog 2020-03-26 Anton Kolesov <anton.kolesov@synopsys.com> * readelf.c (get_note_type): Handle NT_ARC_V2. include/elf/ChangeLog 2020-03-26 Anton Kolesov <anton.kolesov@synopsys.com> * common.h (NT_ARC_V2): New macro definitions.
2020-04-22xtensa: fix PR ld/25861Max Filippov2-0/+12
Introduce new relaxations XTENSA_PDIFF{8,16,32} for positive differences (subtracted symbol precedes diminished symbol) and XTENSA_NDIFF{8,16,32} for negative differences (subtracted symbol follows diminished symbol). Don't generate XTENSA_DIFF relocations in the assembler, generate XTENSA_PDIFF or XTENSA_NDIFF based on relative symbol position. Handle XTENSA_DIFF in BFD for compatibility with old object files. Handle XTENSA_PDIFF and XTENSA_NDIFF in BFD, treating difference value as unsigned. 2020-04-22 Max Filippov <jcmvbkbc@gmail.com> bfd/ * bfd-in2.h: Regenerated. * elf32-xtensa.c (elf_howto_table): New entries for R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}. (elf_xtensa_reloc_type_lookup, elf_xtensa_do_reloc) (relax_section): Add cases for R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}. * libbfd.h (bfd_reloc_code_real_names): Add names for BFD_RELOC_XTENSA_PDIFF{8,16,32} and BFD_RELOC_XTENSA_NDIFF{8,16,32}. * reloc.c: Add documentation for BFD_RELOC_XTENSA_PDIFF{8,16,32} and BFD_RELOC_XTENSA_NDIFF{8,16,32}. binutils/ * readelf.c (is_none_reloc): Recognize BFD_RELOC_XTENSA_PDIFF{8,16,32} and BFD_RELOC_XTENSA_NDIFF{8,16,32}. gas/ * config/tc-xtensa.c (md_apply_fix): Replace BFD_RELOC_XTENSA_DIFF{8,16,32} generation with BFD_RELOC_XTENSA_PDIFF{8,16,32} and BFD_RELOC_XTENSA_NDIFF{8,16,32} generation. * testsuite/gas/xtensa/loc.d: Replace BFD_RELOC_XTENSA_DIFF16 with BFD_RELOC_XTENSA_PDIFF16 in the expected output. include/ * elf/xtensa.h (elf_xtensa_reloc_type): New entries for R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}. ld/ * testsuite/ld-xtensa/relax-loc.d: New test definition. * testsuite/ld-xtensa/relax-loc.s: New test source. * testsuite/ld-xtensa/xtensa.exp (relax-loc): New test.
2020-04-21Remove SH-5 remnantsAlan Modra2-21/+5
git commit 211dc24b87 removed most sh5 and sh64 SuperH support, after they were obsoleted by git commit 2b213129c5. This patch removes a few remaining pieces that should have gone with 211dc24b87. include/ * elf/sh.h (STO_SH5_ISA32, SHF_SH5_ISA32, SHF_SH5_ISA32_MIXED), (SHT_SH5_CR_SORTED, STT_DATALABEL): Delete. bfd/ * elf32-sh.c (sh_elf_relocate_section): Remove STO_SH5_ISA32 processing.
2020-04-15Unify the behaviour of ld.bfd and ld.gold with respect to warning about ↵Fangrui Song2-3/+12
unresolved symbol references. (PR 24613) PR binutils/24613 include * bfdlink.h (enum report_method): Delete RM_GENERATE_WARNING and RM_GENERATE_ERROR. Add RM_DIAGNOSE. (struct bfd_link_info): Add warn_unresolved_syms. ld * lexsup.c (parse_args): Change RM_GENERATE_WARNING and RM_GENERATE_ERROR to RM_DIAGNOSE. * emultempl/aix.em (ld_${EMULATION_NAME}_emulation): Change RM_GENERATE_ERROR to RM_DIAGNOSE. * emultempl/elf.em (ld_${EMULATION_NAME}_emulation): Likewise. bfd * coff-rs6000.c (xcoff_ppc_relocate_section): Change RM_GENERATE_ERROR to RM_DIAGNOSE plus a check of warn_unresolved_syms. * coff64-rs6000.c (xcoff_ppc_relocate_section): Likewise. * elf-bfd.h (_bfd_elf_large_com_section): Likewise. * elf32-m32r.c (m32r_elf_relocate_section): Likewise. * elf32-score.c (s3_bfd_score_elf_relocate_section): Likewise. * elf32-score7.c (s7_bfd_score_elf_relocate_section): Likewise. * elf32-sh.c (sh_elf_relocate_section): Likewise. * elf32-spu.c (spu_elf_relocate_section): Likewise. * elf64-hppa.c (elf64_hppa_relocate_section): Likewise. * elflink.c (elf_link_output_extsym): Likewise. * elfxx-mips.c (mips_elf_calculate_relocation): Likewise.
2020-04-14Fixes for the magic number used in PDP11 AOUT binaries.Stephen Casner2-1/+9
PR ld/25677 include * aout/aout64.h (N_DATADDR): Add IMAGIC case. bfd * pdp11.c: Add implementation of --imagic option. (adjust_o_magic): Fix objcopy --extract-symbol test. * libaout.h (enum aout_magic): Add i_magic. ld * emulparams/pdp11.sh (SCRIPT_NAME): Change to pdp11. (EXTRA_EM_FILE): New, add emulation file pdp11. * scripttempl/pdp11.sc: New, derived from aout.sc without irrelevant input sections. * emultempl/pdp11.em (_add_options, _handle_option) (_list_options): New. Add options -z, --imagic for pdp11-aout. (_before_parse): Make --omagic be default instead of --nmagic. (_get_script): Modify special-case linker script for --imagic. * lexsup.c (parse_args): Explictly set config.text_read_only for -n. * ld.texi (Options): Add documentation of PDP11-specific options. (Options): Fix unrelated typo to --no-compact-branches. * gen-doc.texi: @set PDP11. * testsuite/ld-pdp11/pdp11.exp: New, start pdp11 testing. * testsuite/ld-pdp11/sections.s: New, source for options tests. * testsuite/ld-pdp11/imagic.d: New, test --imagic format. * testsuite/ld-pdp11/imagicz.d: New, test -z (imagic) format. * testsuite/ld-pdp11/nmagic.d: New, test --nmagic format. * testsuite/ld-pdp11/omagic.d: New, test --omagic format.
2020-04-02coff-go32-exe: support variable-length stubsJan W. Jagersma3-48/+7
The stub size in GO32 executables has historically been fixed at 2048 bytes, due to hardcoded limitations in bfd. Recent patches to djgpp by Stas Sergeev (CC'd) have pushed the stub right up to this limit, so if any further expansion is desired, this must first be patched in bfd. This series includes three patches: The first changes the meaning of the bfd->origin field slightly, so that target code can use this to specify an offset into the file where the actual bfd is located. The second patch then uses this to enable support for variable-sized stubs in the coff-go32-exe format. The final patch is only a cleanup, it normalizes function and variable names in coff-stgo32.c so that they all begin with the same prefix. bfd * bfdio.c (bfd_bread, bfd_tell, bfd_seek, bfd_mmap): Always add bfd->origin to file offset. * bfdwin.c (bfd_get_file_window): Likewise. * bfd.c: Clarify the use of the bfd->origin field. * bfd-in2.h: Regenerate. * coff-i386.c: Don't include go32exe.h. Allow overriding coff_write_object_contents via COFF_WRITE_CONTENTS. * coff-stgo32.c (go32exe_cleanup, go32exe_mkobject) (go32exe_write_object_contents): New functions. (go32exe_temp_stub, go32exe_temp_stub_size): New static globals. (COFF_WRITE_CONTENTS, GO32EXE_DEFAULT_STUB_SIZE): Define. (create_go32_stub): Remove check for 2k size limit. Read stub from go32exe_temp_stub if present. (go32_stubbed_coff_bfd_copy_private_bfd_data): Allocate and copy variable-length stub. (go32_check_format): Read stub to go32exe_temp_stub, set origin, return go32exe_cleanup. (adjust_filehdr_in_post, adjust_filehdr_out_pre) (adjust_filehdr_out_post, adjust_scnhdr_in_post) (adjust_scnhdr_out_pre, adjust_scnhdr_out_post) (adjust_aux_in_post, adjust_aux_out_pre, adjust_aux_out_post): Remove functions and their associated #defines. * coffcode.h (coff_mkobject_hook): Remove stub copying code. * libcoff-in.h: (struct coff_tdata): New field stub_size. Rename field go32stub to stub. * libcoff.h: Regenerate. * coff-stgo32.c (go32_check_format): Rename to... (go32exe_check_format): ...this. (go32_stubbed_coff_bfd_copy_private_bfd_data): Rename to... (go32exe_copy_private_bfd_data): ...this. (stub_bytes): Rename to... (go32exe_default_stub): ...this. (create_go32_stub): Rename to... (go32exe_create_stub): ...this. * coff-stgo32.c (go32exe_copy_private_bfd_data): Avoid realloc when possible. include * coff/go32exe.h: Remove file. * coff/internal.h (struct internal_filehdr): Remove field go32stub. Remove flag F_GO32STUB.
2020-04-01include: Sync plugin-api.h with GCCMartin Liska2-1/+7
Fix typo in a macro usage. PR lto/94249 * plugin-api.h: Fix a typo.
2020-03-30RISC-V: Update CSR to privileged spec 1.11.Nelson Chu2-6/+23
gas/ * testsuite/gas/riscv/alias-csr.d: Move this to priv-reg-pseudo. * testsuite/gas/riscv/alias-csr.s: Likewise. * testsuite/gas/riscv/no-aliases-csr.d: Move this to priv-reg-pseudo-noalias. * testsuite/gas/riscv/bad-csr.d: Rename to priv-reg-fail-nonexistent. * testsuite/gas/riscv/bad-csr.l: Likewise. * testsuite/gas/riscv/bad-csr.s: Likewise. * testsuite/gas/riscv/satp.d: Removed. Already included in priv-reg. * testsuite/gas/riscv/satp.s: Likewise. * testsuite/gas/riscv/priv-reg-pseudo.d: New testcase for all pseudo csr instruction, including alias-csr testcase. * testsuite/gas/riscv/priv-reg-pseudo.s: Likewise. * testsuite/gas/riscv/priv-reg-pseudo-noalias.d: New testcase for all pseudo instruction with objdump -Mno-aliases. * testsuite/gas/riscv/priv-reg-fail-nonexistent.d: New testcase. * testsuite/gas/riscv/priv-reg-fail-nonexistent.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-nonexistent.s: Likewise. * testsuite/gas/riscv/priv-reg.d: Update CSR to 1.11. * testsuite/gas/riscv/priv-reg.s: Likewise. * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. include/ * opcode/riscv-opc.h: Update CSR to 1.11. gdb/ * features/riscv/32bit-csr.xml: Regenerated. * features/riscv/64bit-csr.xml: Regenerated.
2020-03-26Support AT_BSDFLAGS on FreeBSD.John Baldwin2-0/+5
FreeBSD's kernel recently added a new ELF auxiliary vector entry holding a mask of software features provided by the kernel. This change fixes 'info auxv' to report the name and description for this vector entry instead of '???'. include/ChangeLog: * elf/common.h (AT_FREEBSD_BSDFLAGS): Define. gdb/ChangeLog: * fbsd-tdep.c (fbsd_print_auxv_entry): Handle AT_FREEBSD_BSDFLAGS.
2020-03-24include: Sync plugin-api.h with GCCMartin Liska2-2/+68
Improve endianess detection. PR lto/94249 * plugin-api.h: Add more robust endianess detection.
2020-03-21include: Sync lto-symtab.h and plugin-api.h with GCCMartin Liska3-2/+8
Fix comma at end of enumerator list seen with -std=c++98. * plugin-api.h (enum ld_plugin_symbol_type): Remove comma after last value of an enum. * lto-symtab.h (enum gcc_plugin_symbol_type): Likewise.
2020-03-19Include: Sync lto-symtab.h and plugin-api.h with GCCMartin Liska3-2/+56
2020-03-19 Martin Liska <mliska@suse.cz> * lto-symtab.h (enum gcc_plugin_symbol_type): New. (enum gcc_plugin_symbol_section_kind): Likewise. 2020-03-19 Martin Liska <mliska@suse.cz> * plugin-api.h (struct ld_plugin_symbol): Split int def into 4 char fields. (enum ld_plugin_symbol_type): New. (enum ld_plugin_symbol_section_kind): New. (enum ld_plugin_tag): Add LDPT_ADD_SYMBOLS_V2.
2020-03-14Implement NT_NETBSDCORE_LWPSTATUS (NetBSD-Core)Kamil Rytarowski2-1/+6
bfd/ChangeLog: * elf.c (elfcore_grok_netbsd_note): Add support for NT_NETBSDCORE_LWPSTATUS notes. binutils/ChangeLog: * readelf.c (get_netbsd_elfcore_note_type): Add support for NT_NETBSDCORE_LWPSTATUS notes. include/ChangeLog: * elf/common.h (NT_NETBSDCORE_LWPSTATUS): New define.
2020-03-13Register NT_NETBSDCORE_AUXV (NetBSD-Core)Kamil Rytarowski2-0/+5
* elf/common.h (NT_NETBSDCORE_AUXV): New define.
2020-03-13Add support for non-contiguous memory regionsChristophe Lyon2-0/+13
2020-01-06 Christophe Lyon <christophe.lyon@linaro.org> bfd/ * bfd-in2.h: Regenerate. * section.c (asection): Add already_assigned field. (BFD_FAKE_SECTION): Add default initializer for it. * ecoff.c (bfd_debug_section): Initialize already_assigned field. * elf32-arm.c (arm_build_one_stub): Add support for non_contiguous_regions. * elf32-csky.c (csky_build_one_stub): Likewise. * elf32-hppa.c (hppa_build_one_stub): Likewise. * elf32-m68hc11.c (m68hc11_elf_build_one_stub): Likewise. * elf32-m68hc12.c (m68hc12_elf_build_one_stub): Likewise. * elf32-metag.c (metag_build_one_stub): Likewise. * elf32-nios2.c (nios2_build_one_stub): Likewise. * elf64-ppc.c (ppc_build_one_stub): Likewise. (ppc_size_one_stub): Likewise. * elfnn-aarch64.c (aarch64_build_one_stub): Likewise. * elflink.c (elf_link_input_bfd): Likewise. include/ * bfdlink.h (bfd_link_info): Add non_contiguous_regions and non_contiguous_regions_warnings fields. ld/ * ldlang.c (lang_add_section): Add support for non_contiguous_regions. (size_input_section): Likewise. (lang_size_sections_1): Likewise. (process_insert_statements): Likewise. * ldlex.h (option_values): Add OPTION_NON_CONTIGUOUS_REGIONS and OPTION_NON_CONTIGUOUS_REGIONS_WARNINGS. * lexsup.c (ld_options): Add entries for --enable-non-contiguous-regions and --enable-non-contiguous-regions-warnings. (parse_args): Handle it. * NEWS: Add --enable-non-contiguous-regions and --enable-non-contiguous-regions-warnings. * ld.texi: Add --enable-non-contiguous-regions and --enable-non-contiguous-regions-warnings documentation. * emultempl/armelf.em (elf32_arm_add_stub_section): Add SEC_LINKER_CREATED flag. * emultempl/xtensaelf.em (ld_build_required_section_dependence): Emit an error when --enable-non-contiguous-regions is used. * testsuite/ld-elf/non-contiguous.d: New. * testsuite/ld-elf/non-contiguous.ld: New. * testsuite/ld-elf/non-contiguous.s: New. * testsuite/ld-arm/arm-elf.exp: Run the new tests. * testsuite/ld-arm/arm-elf/non-contiguous-arm.s: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm.ld: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm2.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm3.ld: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm3.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm3.ld: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm4.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm4.ld: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm5.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm5.ld: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm6.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm6.ld: New. * testsuite/ld-powerpc/powerpc.exp: Run new tests. * testsuite/ld-powerpc/non-contiguous-powerpc.d: New. * testsuite/ld-powerpc/non-contiguous-powerpc.ld: New. * testsuite/ld-powerpc/non-contiguous-powerpc.sd: New. * testsuite/ld-powerpc/non-contiguous-powerpc64.d: New.
2020-03-13Fix several mix up between octets and bytes in ELF program headersChristian Eggers3-5/+15
Fixes additional locations not handled in the first patch. When converting between addresses in ELF headers [octets] and bfd LMA/VMA [bytes], the number of octets per byte needs to be incorporated. include/ * bfdlink.h (struct bfd_link_order): Add unit (bytes/octets) to offset and size members. * elf/internal.h (struct elf_internal_phdr): Likewise for p_align member. (struct elf_segment_map): Likewise for p_paddr and p_size members bfd/ * bfd.c (bfd_record_phdr): New local "opb". Fix assignment of "p_paddr" from "at". * elfcode.h (bfd_from_remote_memory): Add units to several parameters. New local "opb". Fix usage of p_align. Fix calculation of "localbase" from "ehdr_vma" and "p_vaddr". Fix call of target_read_memory. * elflink.c (elf_fixup_link_order): Fix scope of "s" local. Fix calculation of "offset" and "output_offset". (bfd_elf_final_link): New local "opb". Fix calculation of "size" from "offset" and fix calculation of "end" from "vma+size". Fix comparison between "sh_addr" and "vma"/"output_offset". (bfd_elf_discard_info): Fix calculation of "eh_alignment". * elf-bfd.h (struct elf_link_hash_table): Add unit to tls_size member. * elf.c (_bfd_elf_map_sections_to_segments): Add unit (bytes/ octets) to "wrap_to2 and "phdr_size" locals. Fix calculation of "wrap_to" value. Add unit (bytes) to phdr_lma variable. Fix assignment of p_paddr from phdr_lma. Fix comparison between "lma+size" and "next->lma". (elf_sort_segments): Fix assignment from p_paddr to lma. (assign_file_positions_for_load_sections): Add unit (bytes) to local "align". Fix calculation of local "off_adjust". Fix calculation of local "filehdr_vaddr". (assign_file_positions_for_non_load_sections): New local "opb". Fix calculation of "end" from "p_size". Fix comparison between "vma+SECTION_SIZE" and "start". Fix calculation of "p_memsz" from "end" and "p_vaddr". (rewrite_elf_program_header): Fix comparison between p_vaddr and vma. Fix assignment to p_paddr from lma. Fix comparison between p_paddr and lma. Fix assignment to p_paddr from lma. * merge.c (sec_merge_emit): New local "opb". Convert "alignment_power" to octets. (_bfd_add_merge_section): New locals "alignment_power" and "opb". Fix comparison between "alignment_power" and "sizeof(align)". (_bfd_merge_sections): New local "opb". Divide size by opb before checking align mask.
2020-03-13Fix several mix up between octets and bytes in ELF program headersChristian Eggers2-12/+19
When converting between addresses in ELF headers [octets] and bfd LMA/VMA [bytes], the number of octets per byte needs to be incorporated. In ld, the SIZEOF_HEADERS linker script statement must be resolved to bytes instead of octets. include/ * elf/internal.h (struct elf_internal_phdr): Add unit (octets) to several member field comments. (Elf_Internal_Shdr): likewise. bfd/ * elf.c (_bfd_elf_make_section_from_shdr): Introduce new temp opb. Divide Elf_Internal_Shdr::sh_addr by opb when setting section LMA/VMA. (_bfd_elf_make_section_from_phdr): Similarly. (elf_fake_sections): Fix calculation of Elf_Internal_shdr::sh_addr from section VMA. (_bfd_elf_map_sections_to_segments): Fix mixup between octets and bytes. (assign_file_positions_for_load_sections): Fix calculations of Elf_Internal_shdr::p_vaddr and p_paddr from section LMA/VMA. Fix comparison between program header address and section LMA. (assign_file_positions_for_non_load_sections): Likewise. (rewrite_elf_program_header): Likewise. Introduce new temp opb. (IS_CONTAINED_BY_VMA): Add parameter opb. (IS_CONTAINED_BY_LMA,IS_SECTION_IN_INPUT_SEGMENT, INCLUDE_SECTION_IN_SEGMENT): Likewise. (copy_elf_program_header): Update call to ELF_SECTION_IN_SEGMENT. Fix calculations of p_addr_valid and p_vaddr_offset. * elflink.c (elf_link_add_object_symbols): Multiply section VMA with octets per byte when comparing against p_vaddr. ld/ * ldexp.c (fold_name): Return SIZEOF_HEADERS in bytes.
2020-03-10ubsan: som: left shift of 1 by 31 placesAlan Modra3-5/+11
* som/aout.h (SOM_AUX_ID_MANDATORY, SOM_SPACE_IS_LOADABLE), (SOM_SYMBOL_HIDDEN, SOM_SYMBOL_HAS_LONG_RETURN): Use 1u << 31. * som/lst.h (LST_SYMBOL_HIDDEN): Likewise.
2020-03-03Add missing AT tags to the ELF common header.Luis Machado2-0/+22
* elf/common.h (AT_L1I_CACHESIZE, AT_L1I_CACHEGEOMETRY) (AT_L1D_CACHESIZE, AT_L1D_CACHEGEOMETRY, AT_L2_CACHESIZE) (AT_L2_CACHEGEOMETRY, AT_L3_CACHESIZE, AT_L3_CACHEGEOMETRY) (AT_MINSIGSTKSZ): New defines, imported from glibc.
2020-02-25Merge upstream GCC changes for include/ and libiberty/ directoriesAndrew Burgess2-2/+10
This commit pulls in the latest changes for the include/ and libiberty/ directories. The last sync was in commit 533da48302a26885a972e4379eccc26b364e5b53. This commit also removes the file libiberty/rust-demangle.h, this file has been removed in upstream GCC, and should have been deleted as part of the previous sync up, which included this ChangeLog entry: 2019-11-16 Eduard-Mihai Burtescu <eddyb@lyken.rs> .... * rust-demangle.h: Remove. I've grep'd over the binutils-gdb source and can find no reference to the rust-demangle.h file, and everything seems to build fine without it, so I assume its continued existence was a mistake. include/ChangeLog: Import from gcc mainline: 2020-02-05 Andrew Burgess <andrew.burgess@embecosm.com> * hashtab.h (htab_remove_elt): Make a parameter const. (htab_remove_elt_with_hash): Likewise. libiberty/ChangeLog: * rust-demangle.h: Removed. Import from gcc mainline: 2020-02-05 Andrew Burgess <andrew.burgess@embecosm.com> * hashtab.c (htab_remove_elt): Make a parameter const. (htab_remove_elt_with_hash): Likewise. 2020-01-23 Alexandre Oliva <oliva@adacore.com> * argv.c (writeargv): Output empty args as "". 2020-01-18 Iain Sandoe <iain@sandoe.co.uk> * cp-demangle.c (cplus_demangle_operators): Add the co_await operator. * testsuite/demangle-expected: Test co_await operator mangling.
2020-02-20RISC-V: Support the ISA-dependent CSR checking.Nelson Chu2-244/+249
According to the riscv privilege spec, some CSR are only valid when rv32 or the specific extension is set. We extend the DECLARE_CSR and DECLARE_CSR_ALIAS to record more informaton we need, and then check whether the CSR is valid according to these information. We report warning message when the CSR is invalid, so we have a choice between error and warning by --fatal-warnings option. Also, a --no-warn/-W option is used to turn the warnings off, if people don't want the warnings. gas/ * config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide whether or not this CSR is legal in the current ISA string. (struct riscv_csr_extra): New structure to hold all extra information of CSR. (riscv_init_csr_hash): New function. According to the DECLARE_CSR and DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash. Call hash_reg_name to insert CSR address into reg_names_hash. (md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR. (reg_csr_lookup_internal, riscv_csr_class_check): New functions. Decide whether the CSR is valid according to the csr_extra_hash. (init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is not a boolean. This is same as riscv_init_csr_hash, so keep the consistent usage. * testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option. * testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option. * testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the f-ext CSR are not allowed. * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The source file is `priv-reg.s`, and the ISA is rv64if, so the rv32-only CSR are not allowed. * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. include/ * opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to record riscv_csr_class. opcodes/ * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed. gdb/ * riscv-tdep.c: Updated since the DECLARE_CSR is changed. * riscv-tdep.h: Likewise. * features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without rv32-only CSR. * features/riscv/64bit-csr.xml: Regernated. binutils/ * dwarf.c: Updated since the DECLARE_CSR is changed.
2020-02-10[binutils][arm] arm support for ARMv8.m Custom Datapath ExtensionMatthew Malcomson2-0/+22
This patch is part of a series that adds support for the Armv8.m ARMv8.m Custom Datapath Extension to binutils. This patch introduces the Custom Instructions Class 1/2/3 (Single/ Dual, Accumulator/Non-accumulator varianats) to the arm backend. The following Custom Instructions are added: cx1, cx1a, cx1d, cx1da, cx2, cx2a, cx2d, cx2da, cx3, cx3a, cx3d, cx3da. Specification can be found at https://developer.arm.com/docs/ddi0607/latest This patch distinguishes between enabling CDE for different coprocessor numbers by defining multiple architecture flags. This means that the parsing of the architecture extension flags is kept entirely in the existing code path. We introduce a new IT block state to indicate the behaviour of these instructions. This new state allows being used in an IT block or outside an IT block, but does not allow the instruction to be used inside a VPT block. We need this since the CX*A instruction versions can be used in IT blocks, but they aren't to have the conditional suffixes on them. Hence we need to mark an instruction as allowed in either position. We also need a new flag to objdump, in order to determine whether to disassemble an instruction as CDE related or not. Successfully regression tested on arm-none-eabi, and arm-wince-pe. gas/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (arm_ext_cde*): New feature sets for each CDE coprocessor that can be enabled. (enum pred_instruction_type): New pred type. (BAD_NO_VPT): New error message. (BAD_CDE): New error message. (BAD_CDE_COPROC): New error message. (enum operand_parse_code): Add new immediate operands. (parse_operands): Account for new immediate operands. (check_cde_operand): New. (cde_coproc_enabled): New. (cde_coproc_pos): New. (cde_handle_coproc): New. (cxn_handle_predication): New. (do_custom_instruction_1): New. (do_custom_instruction_2): New. (do_custom_instruction_3): New. (do_cx1): New. (do_cx1a): New. (do_cx1d): New. (do_cx1da): New. (do_cx2): New. (do_cx2a): New. (do_cx2d): New. (do_cx2da): New. (do_cx3): New. (do_cx3a): New. (do_cx3d): New. (do_cx3da): New. (handle_pred_state): Define new IT block behaviour. (insns): Add newn CX*{,d}{,a} instructions. (CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table): Define new cdecp extension strings. * doc/c-arm.texi: Document new cdecp extension arguments. * testsuite/gas/arm/cde-scalar.d: New test. * testsuite/gas/arm/cde-scalar.s: New test. * testsuite/gas/arm/cde-warnings.d: New test. * testsuite/gas/arm/cde-warnings.l: New test. * testsuite/gas/arm/cde-warnings.s: New test. * testsuite/gas/arm/cde.d: New test. * testsuite/gas/arm/cde.s: New test. include/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * opcode/arm.h (ARM_EXT2_CDE): New extension macro. (ARM_EXT2_CDE0): New extension macro. (ARM_EXT2_CDE1): New extension macro. (ARM_EXT2_CDE2): New extension macro. (ARM_EXT2_CDE3): New extension macro. (ARM_EXT2_CDE4): New extension macro. (ARM_EXT2_CDE5): New extension macro. (ARM_EXT2_CDE6): New extension macro. (ARM_EXT2_CDE7): New extension macro. opcodes/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (struct cdeopcode32): New. (CDE_OPCODE): New macro. (cde_opcodes): New disassembly table. (regnames): New option to table. (cde_coprocs): New global variable. (print_insn_cde): New (print_insn_thumb32): Use print_insn_cde. (parse_arm_disassembler_options): Parse coprocN args.
2020-02-07Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add ↵Sergey Belyashov3-0/+10
DWARF debug info support to the Z80 assembler. PR 25469 bfd * archures.c: Add GBZ80 and Z80N machine values. * reloc.c: Add BFD_RELOC_Z80_16_BE. * coff-z80.c: Add support for new reloc. * coffcode.h: Add support for new machine values. * cpu-z80.c: Add support for new machine names. * elf32-z80.c: Add support for new reloc. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. binutils* readelf.c (get_machine_flags): Add support for Z80N machine number. gas * config/tc-z80.c: Add -gbz80 command line option to generate code for the GameBoy Z80. Add support for generating DWARF. * config/tc-z80.h: Add support for DWARF debug information generation. * doc/c-z80.texi: Document new command line option. * testsuite/gas/z80/gbz80_all.d: New file. * testsuite/gas/z80/gbz80_all.s: New file. * testsuite/gas/z80/z80.exp: Run the new tests. * testsuite/gas/z80/z80n_all.d: New file. * testsuite/gas/z80/z80n_all.s: New file. * testsuite/gas/z80/z80n_reloc.d: New file. include * coff/internal.h (R_IMM16BE): Define. * elf/z80.h (EF_Z80_MACH_Z80N): Define. (R_Z80_16_BE): New reloc. ld * emulparams/elf32z80.sh: Use z80 emulation. * emultempl/z80.em: Make generic to both COFF and ELF Z80 emulations. * emultempl/z80elf.em: Delete. * testsuite/ld-elf/pr22450.d: Expect to fail for the Z80. * testsuite/ld-elf/sec64k.exp: Fix Z80 assembly. * testsuite/ld-unique/pr21529.s: Avoid register name conflict. * testsuite/ld-unique/unique.s: Likewise. * testsuite/ld-unique/unique_empty.s: Likewise. * testsuite/ld-unique/unique_shared.s: Likewise. * testsuite/ld-unique/unique.d: Updated expected output. * testsuite/ld-z80/arch_z80n.d: New file. * testsuite/ld-z80/comb_arch_z80_z80n.d: New file. * testsuite/ld-z80/labels.s: Add more labels. * testsuite/ld-z80/relocs.s: Add more reloc tests. * testsuite/ld-z80/relocs_f_z80n.d: New file opcodes * z80-dis.c: Add support for GBZ80 opcodes.
2020-02-04ubsan: d30v: negation of -2147483648Alan Modra2-1/+5
include/ * opcode/d30v.h (struct pd_reg): Make value field unsigned. opcodes/ * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2020-01-30Add some new PE_IMAGE_DEBUG_TYPE valuesJon Turney2-0/+11
IMAGE_DEBUG_TYPE_REPRO is defined in the latest version of the PE specification [1]. The others are defined in Windows SDK headers and/or reported by DUMPBIN. [1] https://docs.microsoft.com/en-us/windows/win32/debug/pe-format bfd/ChangeLog: 2020-01-16 Jon Turney <jon.turney@dronecode.org.uk> * peXXigen.c (debug_type_names): Add names for new debug data type values. include/ChangeLog: 2020-01-16 Jon Turney <jon.turney@dronecode.org.uk> * coff/internal.h (PE_IMAGE_DEBUG_TYPE_VC_FEATURE) (PE_IMAGE_DEBUG_TYPE_POGO, PE_IMAGE_DEBUG_TYPE_ILTCG) (PE_IMAGE_DEBUG_TYPE_MPX, PE_IMAGE_DEBUG_TYPE_REPRO): Add.
2020-01-18Add markers for 2.34 branch to the NEWS files and ChangeLogs.Nick Clifton1-0/+4
2020-01-17Update libiberty sources with changes in the gcc mainline.Nick Clifton4-24/+87
+2020-01-01 Jakub Jelinek <jakub@redhat.com> + + Update copyright years. + +2019-12-06 Tim Ruehsen <tim.ruehsen@gmx.de> + + * make-relative-prefix.c (split_directories): + Return early on empty 'name' + +2019-11-16 Tim Ruehsen <tim.ruehsen@gmx.de> + + * cp-demangle.c (d_print_init): Remove const from 4th param. + (cplus_demangle_fill_name): Initialize d->d_counting. + (cplus_demangle_fill_extended_operator): Likewise. + (cplus_demangle_fill_ctor): Likewise. + (cplus_demangle_fill_dtor): Likewise. + (d_make_empty): Likewise. + (d_count_templates_scopes): Remobe const from 3rd param, + Return on dc->d_counting > 1, + Increment dc->d_counting. + * cp-demint.c (cplus_demangle_fill_component): Initialize d->d_counting. + (cplus_demangle_fill_builtin_type): Likewise. + (cplus_demangle_fill_operator): Likewise. + +2019-11-16 Eduard-Mihai Burtescu <eddyb@lyken.rs> + + * cplus-dem.c (cplus_demangle): Use rust_demangle directly. + (rust_demangle): Remove. + * rust-demangle.c (is_prefixed_hash): Rename to is_legacy_prefixed_hash. + (parse_lower_hex_nibble): Rename to decode_lower_hex_nibble. + (parse_legacy_escape): Rename to decode_legacy_escape. + (rust_is_mangled): Remove. + (struct rust_demangler): Add. + (peek): Add. + (next): Add. + (struct rust_mangled_ident): Add. + (parse_ident): Add. + (rust_demangle_sym): Remove. + (print_str): Add. + (PRINT): Add. + (print_ident): Add. + (rust_demangle_callback): Add. + (struct str_buf): Add. + (str_buf_reserve): Add. + (str_buf_append): Add. + (str_buf_demangle_callback): Add. + (rust_demangle): Add. + * rust-demangle.h: Remove. + +2019-11-15 Miguel Saldivar <saldivarcher@gmail.com> + + * testsuite/demangle-expected: Fix test. + +2019-11-04 Kamlesh Kumar <kamleshbhalui@gmail.com> + + * cp-demangle.c (d_expr_primary): Handle + nullptr demangling. + * testsuite/demangle-expected: Added test. + +2019-10-29 Paul Pluzhnikov <ppluzhnikov@google.com> + + * cp-demangle.c (d_number): Avoid signed int overflow. + +2019-10-28 Miguel Saldivar <saldivarcher@gmail.com> + + * cp-demangle.c (d_print_mod): Add a space before printing `complex` + and `imaginary`, as opposed to after. + * testsuite/demangle-expected: Adjust test. + +2019-10-03 Eduard-Mihai Burtescu <eddyb@lyken.rs> + + * rust-demangle.c (looks_like_rust): Remove. + (rust_is_mangled): Don't check escapes. + (is_prefixed_hash): Allow 0-9a-f permutations. + (rust_demangle_sym): Don't bail on unknown escapes. + * testsuite/rust-demangle-expected: Update 'main::$99$' test. + +2019-09-03 Eduard-Mihai Burtescu <eddyb@lyken.rs> + + * rust-demangle.c (unescape): Remove. + (parse_lower_hex_nibble): New function. + (parse_legacy_escape): New function. + (is_prefixed_hash): Use parse_lower_hex_nibble. + (looks_like_rust): Use parse_legacy_escape. + (rust_demangle_sym): Use parse_legacy_escape. + * testsuite/rust-demangle-expected: Add 'llv$u6d$' test. + +2019-08-27 Martin Liska <mliska@suse.cz> + + PR lto/91478 + * simple-object-elf.c (simple_object_elf_copy_lto_debug_sections): + First find a WEAK HIDDEN symbol in symbol table that will be + preserved. Later, use the symbol name for all removed symbols. + +2019-08-12 Martin Liska <mliska@suse.cz> + + * Makefile.in: Add filedescriptor.c. + * filedescriptor.c: New file. + * lrealpath.c (is_valid_fd): Remove. diff --git a/libiberty/Makefile.in b/libiberty/Makefile.in index 0be45b4ae8..fe738d0db4 100644 --- a/libiberty/Makefile.in +++ b/libiberty/Makefile.in @@ -1,7 +1,7 @@ # Makefile for the libiberty library. # Originally written by K. Richard Pixley <rich@cygnus.com>. # -# Copyright (C) 1990-2019 Free Software Foundation, Inc. +# Copyright (C) 1990-2020 Free Software Foundation, Inc. # # This file is part of the libiberty library. # Libiberty is free software; you can redistribute it and/or @@ -127,7 +127,7 @@ CFILES = alloca.c argv.c asprintf.c atexit.c \ calloc.c choose-temp.c clock.c concat.c cp-demangle.c \ cp-demint.c cplus-dem.c crc32.c \ d-demangle.c dwarfnames.c dyn-string.c \ - fdmatch.c ffs.c fibheap.c filename_cmp.c floatformat.c \ + fdmatch.c ffs.c fibheap.c filedescriptor.c filename_cmp.c floatformat.c \ fnmatch.c fopen_unlocked.c \ getcwd.c getopt.c getopt1.c getpagesize.c getpwd.c getruntime.c \ gettimeofday.c \ @@ -171,6 +171,7 @@ REQUIRED_OFILES = \ ./cp-demint.$(objext) ./crc32.$(objext) ./d-demangle.$(objext) \ ./dwarfnames.$(objext) ./dyn-string.$(objext) \ ./fdmatch.$(objext) ./fibheap.$(objext) \ + ./filedescriptor.$(objext) \ ./filename_cmp.$(objext) ./floatformat.$(objext) \ ./fnmatch.$(objext) ./fopen_unlocked.$(objext) \ ./getopt.$(objext) ./getopt1.$(objext) ./getpwd.$(objext) \ @@ -756,6 +757,17 @@ $(CONFIGURED_OFILES): stamp-picdir stamp-noasandir else true; fi $(COMPILE.c) $(srcdir)/fibheap.c $(OUTPUT_OPTION) +./filedescriptor.$(objext): $(srcdir)/filedescriptor.c config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h + if [ x"$(PICFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(srcdir)/filedescriptor.c -o pic/$@; \ + else true; fi + if [ x"$(NOASANFLAG)" != x ]; then \ + $(COMPILE.c) $(PICFLAG) $(NOASANFLAG) $(srcdir)/filedescriptor.c -o noasan/$@; \ + else true; fi + $(COMPILE.c) $(srcdir)/filedescriptor.c $(OUTPUT_OPTION) + + ./filename_cmp.$(objext): $(srcdir)/filename_cmp.c config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \ $(INCDIR)/safe-ctype.h diff --git a/libiberty/_doprnt.c b/libiberty/_doprnt.c index d44dc415ed..a739f4304f 100644 --- a/libiberty/_doprnt.c +++ b/libiberty/_doprnt.c @@ -1,5 +1,5 @@ /* Provide a version of _doprnt in terms of fprintf. - Copyright (C) 1998-2019 Free Software Foundation, Inc. + Copyright (C) 1998-2020 Free Software Foundation, Inc. Contributed by Kaveh Ghazi (ghazi@caip.rutgers.edu) 3/29/98 This program is free software; you can redistribute it and/or modify it diff --git a/libiberty/argv.c b/libiberty/argv.c index 6444896f99..8c9794db6a 100644 --- a/libiberty/argv.c +++ b/libiberty/argv.c @@ -1,5 +1,5 @@ /* Create and destroy argument vectors (argv's) - Copyright (C) 1992-2019 Free Software Foundation, Inc. + Copyright (C) 1992-2020 Free Software Foundation, Inc. Written by Fred Fish @ Cygnus Support This file is part of the libiberty library. diff --git a/libiberty/asprintf.c b/libiberty/asprintf.c index 5718682f69..6e38e2234d 100644 --- a/libiberty/asprintf.c +++ b/libiberty/asprintf.c @@ -1,6 +1,6 @@ /* Like sprintf but provides a pointer to malloc'd storage, which must be freed by the caller. - Copyright (C) 1997-2019 Free Software Foundation, Inc. + Copyright (C) 1997-2020 Free Software Foundation, Inc. Contributed by Cygnus Solutions. This file is part of the libiberty library. diff --git a/libiberty/choose-temp.c b/libiberty/choose-temp.c index 72c1b710bd..49a2faaa51 100644 --- a/libiberty/choose-temp.c +++ b/libiberty/choose-temp.c @@ -1,5 +1,5 @@ /* Utility to pick a temporary filename prefix. - Copyright (C) 1996-2019 Free Software Foundation, Inc. + Copyright (C) 1996-2020 Free Software Foundation, Inc. This file is part of the libiberty library. Libiberty is free software; you can redistribute it and/or diff --git a/libiberty/clock.c b/libiberty/clock.c index a3730714bd..0de74657d0 100644 --- a/libiberty/clock.c +++ b/libiberty/clock.c @@ -1,5 +1,5 @@ /* ANSI-compatible clock function. - Copyright (C) 1994-2019 Free Software Foundation, Inc. + Copyright (C) 1994-2020 Free Software Foundation, Inc. This file is part of the libiberty library. This library is free software; you can redistribute it and/or modify it under the diff --git
2020-01-16[binutils][arm] PR25376 Change MVE into a CORE_HIGH featureAndre Vieira2-4/+11
This patch moves MVE feature bits into the CORE_HIGH section. This makes sure .fpu and -mfpu does not reset the bits set by MVE. This is important because .fpu has no option to "set" these same bits and thus, mimic'ing GCC, we choose to define MVE as an architecture extension rather than put it together with other the legacy fpu features. This will enable the following behavior: .arch armv8.1-m.main .arch mve .fpu fpv5-sp-d16 #does not disable mve. vadd.i32 q0, q1, q2 This patch also makes sure MVE is not taken into account during auto-detect. This was already the case, but because we moved the MVE bits to the architecture feature space we must make sure ARM_ANY does not include MVE. gas/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH. (armv8_1m_main_ext_table): Use CORE_HIGH for mve. * testsuite/arm/armv8_1-m-fpu-mve-1.s: New. * testsuite/arm/armv8_1-m-fpu-mve-1.d: New. * testsuite/arm/armv8_1-m-fpu-mve-2.s: New. * testsuite/arm/armv8_1-m-fpu-mve-2.d: New. include/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to... (ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space. (ARM_ANY): Redefine to not include any MVE bits. (ARM_FEATURE_ALL): Removed. opcodes/ChangeLog: 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25376 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits. (neon_opcodes): Likewise. (select_arm_features): Make sure we enable MVE bits when selecting armv8.1-m.main. Make sure we do not enable MVE bits when not selecting any architecture.
2020-01-15MSP430: Fix relocation overflow when using #lo(EXP) macroJozef Lawrynowicz2-0/+20
gas/ChangeLog: 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * config/tc-msp430.c (CHECK_RELOC_MSP430): Always generate 430X relocations when the target is 430X, except when extracting part of an expression. (msp430_srcoperand): Adjust comment. Initialize the expp member of the msp430_operand_s struct as appropriate. (msp430_dstoperand): Likewise. * testsuite/gas/msp430/msp430.exp: Run new test. * testsuite/gas/msp430/reloc-lo-430x.d: New test. * testsuite/gas/msp430/reloc-lo-430x.s: New test. include/ChangeLog: 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * opcode/msp430.h (enum msp430_expp_e): New. (struct msp430_operand_s): Add expp member to struct. ld/ChangeLog: 2020-01-15 Jozef Lawrynowicz <jozef.l@mittosystems.com> * testsuite/ld-msp430-elf/msp430-elf.exp: Run new test. * testsuite/ld-msp430-elf/reloc-lo-430x.s: New test.
2020-01-13[ARC][committed] Update ARC cpu listClaudiu Zissulescu2-0/+8
include/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * elf/arc-cpu.def: Update ARC cpu list.
2020-01-13tic4x: sign extension using shiftsAlan Modra2-5/+13
Don't do that. Especially don't use shift counts that assume the type being shifted is 32 bits when the type is long/unsigned long. Also reverts part of a change I made on 2019-12-11 to tic4x_print_register that on closer inspection turns out to be unnecessary. include/ * opcode/tic4x.h (EXTR): Delete. (EXTRU, EXTRS, INSERTU, INSERTS): Rewrite without zero/sign extension using shifts. Do trim INSERTU value to specified bitfield. opcodes/ * tic4x-dis.c (tic4x_print_register): Remove dead code. gas/ * config/tc-tic4x.c (tic4x_operands_match): Correct tic3x trap insertion.
2020-01-10ubsan: spu: left shift of negative valueAlan Modra2-17/+29
Also fixes a real bug. The DECODE_INSN_I9a and DECODE_INSN_I9b both use UNSIGNED_EXTRACT for 7 low bits of the result, but this was an unsigned value due to "insn" being unsigned. DECODE_INSN_I9* is therefore unsigned too, leading to a zero extension in an expression using a bfd_vma if bfd_vma is 64 bits. * opcode/spu.h: Formatting. (UNSIGNED_EXTRACT): Use 1u. (SIGNED_EXTRACT): Don't sign extend with shifts. (DECODE_INSN_I9a, DECODE_INSN_I9b): Avoid left shift of signed value. Keep result signed. (DECODE_INSN_U9a, DECODE_INSN_U9b): Delete.
2020-01-07[ARC] Add finer details for LLOCK and SCONDShahab Vahedi2-0/+6
This patch changes the "class" of LLOCK/SCOND from "MEMORY" to "LLOCK/SCOND" respectively. Moreover, it corrects the "data_size_mode". These changes are necessary for GDB's atmoic sequence handler. Signed-off-by: Shahab Vahedi <shahab@synopsys.com>
2020-01-02Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. ↵Sergey Belyashov3-0/+62
Add an ELF based target for these as well. PR 25224 bfd * Makefile.am: Add z80-elf target support. * configure.ac: Likewise. * targets.c: Likewise. * config.bfd: Add z80-elf target support and new arches: ez80 and z180. * elf32-z80.c: New file. * archures.c: Add new z80 architectures: eZ80 and Z180. * coffcode.h: Likewise. * cpu-z80.c: Likewise. * bfd-in2.h: Likewise plus additional Z80 relocations. * coff-z80.c: Add new relocations for Z80 target and local label check. gas * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support for assembler code generated by SDCC. Add new relocation types. Add z80-elf target support. * config/tc-z80.h: Add z80-elf target support. Enable dollar local labels. Local labels starts from ".L". * testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict. * testsuite/gas/all/fwdexp.s: Likewise. * testsuite/gas/z80/suffix.d: Fix failure on ELF target. * testsuite/gas/z80/z80.exp: Add new tests * testsuite/gas/z80/dollar.d: New file. * testsuite/gas/z80/dollar.s: New file. * testsuite/gas/z80/ez80_adl_all.d: New file. * testsuite/gas/z80/ez80_adl_all.s: New file. * testsuite/gas/z80/ez80_adl_suf.d: New file. * testsuite/gas/z80/ez80_isuf.s: New file. * testsuite/gas/z80/ez80_z80_all.d: New file. * testsuite/gas/z80/ez80_z80_all.s: New file. * testsuite/gas/z80/ez80_z80_suf.d: New file. * testsuite/gas/z80/r800_extra.d: New file. * testsuite/gas/z80/r800_extra.s: New file. * testsuite/gas/z80/r800_ii8.d: New file. * testsuite/gas/z80/r800_z80_doc.d: New file. * testsuite/gas/z80/z180.d: New file. * testsuite/gas/z80/z180.s: New file. * testsuite/gas/z80/z180_z80_doc.d: New file. * testsuite/gas/z80/z80_doc.d: New file. * testsuite/gas/z80/z80_doc.s: New file. * testsuite/gas/z80/z80_ii8.d: New file. * testsuite/gas/z80/z80_ii8.s: New file. * testsuite/gas/z80/z80_in_f_c.d: New file. * testsuite/gas/z80/z80_in_f_c.s: New file. * testsuite/gas/z80/z80_op_ii_ld.d: New file. * testsuite/gas/z80/z80_op_ii_ld.s: New file. * testsuite/gas/z80/z80_out_c_0.d: New file. * testsuite/gas/z80/z80_out_c_0.s: New file. * testsuite/gas/z80/z80_reloc.d: New file. * testsuite/gas/z80/z80_reloc.s: New file. * testsuite/gas/z80/z80_sli.d: New file. * testsuite/gas/z80/z80_sli.s: New file. ld * Makefile.am: Add new target z80-elf * configure.tgt: Likewise. * emultempl/z80.em: Add support for eZ80 and Z180 architectures. * emulparams/elf32z80.sh: New file. * emultempl/z80elf.em: Likewise. * testsuite/ld-z80/arch_ez80_adl.d: Likewise. * testsuite/ld-z80/arch_ez80_z80.d: Likewise. * testsuite/ld-z80/arch_r800.d: Likewise. * testsuite/ld-z80/arch_z180.d: Likewise. * testsuite/ld-z80/arch_z80.d: Likewise. * testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z180.d: Likewise. * testsuite/ld-z80/labels.s: Likewise. * testsuite/ld-z80/relocs.s: Likewise. * testsuite/ld-z80/relocs_b_ez80.d: Likewise. * testsuite/ld-z80/relocs_b_z80.d: Likewise. * testsuite/ld-z80/relocs_f_z80.d: Likewise. * testsuite/ld-z80/z80.exp: Likewise. opcodes * z80-dis.c: Add support for eZ80 and Z80 instructions.
2020-01-02Enable building the s12z target on Solaris hosts where REG_Y is defined in ↵Nick Clifton2-10/+18
system header files. * opcode/s12z.h: Undef REG_Y.
2020-01-01Re: Update year range in copyright notice of binutils filesAlan Modra1-0/+4
Add the ChangeLog entry.
2020-01-01Update year range in copyright notice of binutils filesAlan Modra283-283/+283
2020-01-01ChangeLog rotationAlan Modra2-761/+775
2020-01-01Update copyright year range in all GDB files.Joel Brobecker22-22/+22
gdb/ChangeLog: Update copyright year range in all GDB files.
2019-12-17Remove tic80 supportAlan Modra3-406/+5
This is one way of fixing ubsan bug reports, just delete the code. The assembler support was removed back in 2005 along with other non-BFD assemblers, but somehow the remainder of the port stayed in. bfd/ * coff-tic80.c: Delete file. * cpu-tic80.c: Delete file. * archures.c: Remove tic80 support. * coffcode.h: Likewise. * coffswap.h: Likewise. * targets.c: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * Makefile.am: Likewise. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. binutils/ * testsuite/binutils-all/objcopy.exp: Remove tic80 support. * testsuite/binutils-all/objdump.exp: Likewise. gas/ * doc/as.texi: Remove mention of tic80. include/ * coff/tic80.h: Delete file. * opcode/tic80.h: Delete file. ld/ * emulparams/tic80coff.sh: Delete file. * scripttempl/tic80coff.sc: Delete file. * configure.tgt: Remove tic80 support. * Makefile.am: Likewise. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate. opcodes/ * tic80-dis.c: Delete file. * tic80-opc.c: Delete file. * disassemble.c: Remove tic80 support. * disassemble.h: Likewise. * Makefile.am: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
2019-12-16ubsan: crx: left shift cannot be represented in type 'int'Alan Modra2-1/+5
The ubsan complaint is fixed by the SBM change, with similar possible complaints fixed by the EXTRACT change. The rest is just cleanup. include/ * opcode/crx.h (inst <match>): Make unsigned int. opcodes/ * crx-dis.c (EXTRACT, SBM): Avoid signed overflow. (get_number_of_operands, getargtype, getbits, getregname), (getcopregname, getprocregname, gettrapstring, getcinvstring), (getregliststring, get_word_at_PC, get_words_at_PC, build_mask), (powerof2, match_opcode, make_instruction, print_arguments), (print_arg): Delete forward declarations, moving static to.. (getregname, getcopregname, getregliststring): ..these definitions. (build_mask): Return unsigned int mask. (match_opcode): Use unsigned int vars.
2019-12-16ubsan: nds32: left shift cannot be represented in type 'int'Alan Modra2-3/+10
Note that using 1u in N32_BIT makes all of N32_BIT, __MASK, __MF, __GF and __SEXT evaluate as unsigned int (the latter three when when their v arg is int or smaller). This would be a problem if assigning the result to a bfd_vma, long, or other type wider than an int since the __SEXT result would be zero extended to the wider type. Fortunately nds32 target code doesn't use wider types unnecessarily. include/ * opcode/nds32.h (N32_BIT): Define using 1u. (__SEXT): Use __MASK and N32_BIT. (N32_IMMS): Remove duplicate mask. opcodes/ * nds32-dis.c (print_insn16, print_insn32): Remove forward decls. (struct objdump_disasm_info): Delete. (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of N32_IMMS to unsigned before shifting left.
2019-12-12Fix unused function errorLuis Machado2-9/+5
Attempting to build GDB in Ubuntu 16.04.6 LTS on x86_64, I ran into warnings that caused the build to fail: binutils-gdb/gdb/gdbsupport/safe-strerror.c:44:1: error: ‘char* select_strerror_r(char*, char*)’ defined but not used [-Werror=unused-function] select_strerror_r (char *res, char *) The diagnostic macro DIAGNOSTIC_IGNORE_UNUSED_FUNCTION seems to expand correctly to its respective pragma, but this doesn't seem to have an effect on the warning. I tried to use the pragma explicitly and got the same result. ATTRIBUTE_UNUSED works fine in this case if you put it in both functions, which should fix warnings for both gdb and gdbserver builds. The compiler version is gcc (Ubuntu 5.4.0-6ubuntu1~16.04.11) 5.4.0 20160609. This is likely the result of PR64079 in GCC, which was fixed by commit 9e96f1e1b9731c4e1ef4fbbbf0997319973f0537. To prevent other developers from attempting to use this macro, only to get confused by it not working as expected, it seems better to not define this particular macro. gdb/ChangeLog: 2019-12-12 Luis Machado <luis.machado@linaro.org> * gdbsupport/safe-strerror.c: Don't include diagnostics.h. (select_strerror_r): Use ATTRIBUTE_UNUSED instead of the diagnostics macros. include/ChangeLog: 2019-12-12 Luis Machado <luis.machado@linaro.org> * diagnostics.h (DIAGNOSTIC_IGNORE_UNUSED_FUNCTION). Remove definitions. Change-Id: Iad6123d61d76d111e3ef8d24aa8c60112304c749
2019-12-11bfd signed overflow fixesAlan Modra2-8/+14
Aimed at quietening ubsan. include/ * opcode/mmix.h (PUSHGO_INSN_BYTE): Make unsigned. (GO_INSN_BYTE, SETL_INSN_BYTE, INCML_INSN_BYTE, INCMH_INSN_BYTE), (INCH_INSN_BYTE, SWYM_INSN_BYTE, JMP_INSN_BYTE): Likewise. bfd/ * elf32-rx.c (elf32_rx_relax_section): Avoid signed overflow. * libaout.h (N_SET_INFO, N_SET_FLAGS): Likewise. * netbsd.h (write_object_contents): Likewise. * elf32-arm.c (bfd_elf32_arm_vfp11_erratum_scan): Likewise. * libhppa.h (HPPA_R_CONSTANT): Don't signed extend with shifts. (stm32l4xx_create_replacing_stub_vldm): Don't truncate high bits with shifts. * elf32-nds32.h (R_NDS32_RELAX_ENTRY_DISABLE_RELAX_FLAG): Define using 1u shifted left. Ditto for other macros. * mmo.c (LOP): Make unsigned.
2019-12-11ubsan: left shift of cannot be represented in type 'int'Alan Modra3-22/+28
* dis-asm.h (INSN_HAS_RELOC, DISASSEMBLE_DATA), (USER_SPECIFIED_MACHINE_TYPE, WIDE_OUTPUT): Make unsigned. * opcode/tic80.h (TIC80_OPERAND_*): Likewise.
2019-12-10PR24960, Memory leak from disassemblerAlan Modra2-1/+9
PR 24960 include/ * dis-asm.h (disassemble_free_target): Declare. opcodes/ * disassemble.c (disassemble_free_target): New function. binutils/ * objdump.c (disassemble_data): Call disassemble_free_target.
2019-12-10Use disassemble_info.private_data in place of insn_setsAlan Modra2-8/+5
No cgen target uses private_data. This patch removes a disassemble_info field that is only used by cgen, and instead uses private_data. It also removes a macro that is no longer used. include/ * dis-asm.h (struct disassemble_info): Delete insn_sets. (INIT_DISASSEMBLE_INFO_NO_ARCH): Don't define. opcodes/ * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data. * disassemble.c (disassemble_init_for_target): Likewise. * bpf-dis.c: Regenerate. * epiphany-dis.c: Regenerate. * fr30-dis.c: Regenerate. * frv-dis.c: Regenerate. * ip2k-dis.c: Regenerate. * iq2000-dis.c: Regenerate. * lm32-dis.c: Regenerate. * m32c-dis.c: Regenerate. * m32r-dis.c: Regenerate. * mep-dis.c: Regenerate. * mt-dis.c: Regenerate. * or1k-dis.c: Regenerate. * xc16x-dis.c: Regenerate. * xstormy16-dis.c: Regenerate.
2019-12-05Arm64: simplify Crypto arch extension handlingJan Beulich2-1/+8
This, at the assembler level, is just a "brace" feature covering both AES and SHA2. Hence there's no need for it to have a separate feature flag, freeing up a bit for future re-use. Along these lines there are also a number of dead definitions/variables in the opcode table file.
2019-11-25Introduce new section flag: SEC_ELF_OCTETSChristian Eggers2-7/+12
All symbols, sizes and relocations in this section are octets instead of bytes. Required for DWARF debug sections as DWARF information is organized in octets, not bytes. bfd/ * section.c (struct bfd_section): New flag SEC_ELF_OCTETS. * archures.c (bfd_octets_per_byte): New parameter sec. If section is not NULL and SEC_ELF_OCTETS is set, one octet es returned [ELF targets only]. * bfd.c (bfd_get_section_limit): Provide section parameter to bfd_octets_per_byte. * bfd-in2.h: regenerate. * binary.c (binary_set_section_contents): Move call to bfd_octets_per_byte into section loop. Provide section parameter to bfd_octets_per_byte. * coff-arm.c (coff_arm_reloc): Provide section parameter to bfd_octets_per_byte. * coff-i386.c (coff_i386_reloc): likewise. * coff-mips.c (mips_reflo_reloc): likewise. * coff-x86_64.c (coff_amd64_reloc): likewise. * cofflink.c (_bfd_coff_link_input_bfd): likewise. (_bfd_coff_reloc_link_order): likewise. * elf.c (_bfd_elf_section_offset): likewise. (_bfd_elf_make_section_from_shdr): likewise. Set SEC_ELF_OCTETS for sections with names .gnu.build.attributes, .debug*, .zdebug* and .note.gnu*. * elf32-msp430.c (rl78_sym_diff_handler): Provide section parameter to bfd_octets_per_byte. * elf32-nds.c (nds32_elf_get_relocated_section_contents): likewise. * elf32-ppc.c (ppc_elf_addr16_ha_reloc): likewise. * elf32-pru.c (pru_elf32_do_ldi32_relocate): likewise. * elf32-s12z.c (opru18_reloc): likewise. * elf32-sh.c (sh_elf_reloc): likewise. * elf32-spu.c (spu_elf_rel9): likewise. * elf32-xtensa.c (bfd_elf_xtensa_reloc): likewise * elf64-ppc.c (ppc64_elf_brtaken_reloc): likewise. (ppc64_elf_addr16_ha_reloc): likewise. (ppc64_elf_toc64_reloc): likewise. * elflink.c (bfd_elf_final_link): likewise. (bfd_elf_perform_complex_relocation): likewise. (elf_fixup_link_order): likewise. (elf_link_input_bfd): likewise. (elf_link_sort_relocs): likewise. (elf_reloc_link_order): likewise. (resolve_section): likewise. * linker.c (_bfd_generic_reloc_link_order): likewise. (bfd_generic_define_common_symbol): likewise. (default_data_link_order): likewise. (default_indirect_link_order): likewise. * srec.c (srec_set_section_contents): likewise. (srec_write_section): likewise. * syms.c (_bfd_stab_section_find_nearest_line): likewise. * reloc.c (_bfd_final_link_relocate): likewise. (bfd_generic_get_relocated_section_contents): likewise. (bfd_install_relocation): likewise. For section which have SEC_ELF_OCTETS set, multiply output_base and output_offset with bfd_octets_per_byte. (bfd_perform_relocation): likewise. include/ * coff/ti.h (GET_SCNHDR_SIZE, PUT_SCNHDR_SIZE, GET_SCN_SCNLEN), (PUT_SCN_SCNLEN): Adjust bfd_octets_per_byte calls. binutils/ * objdump.c (disassemble_data): Provide section parameter to bfd_octets_per_byte. (dump_section): likewise (dump_section_header): likewise. Show SEC_ELF_OCTETS flag if set. gas/ * as.h: Define SEC_OCTETS as SEC_ELF_OCTETS if OBJ_ELF. * dwarf2dbg.c: (dwarf2_finish): Set section flag SEC_OCTETS for .debug_line, .debug_info, .debug_abbrev, .debug_aranges, .debug_str and .debug_ranges sections. * write.c (maybe_generate_build_notes): Set section flag SEC_OCTETS for .gnu.build.attributes section. * frags.c (frag_now_fix): Don't divide by OCTETS_PER_BYTE if SEC_OCTETS is set. * symbols.c (resolve_symbol_value): Likewise. ld/ * ldexp.c (fold_name): Provide section parameter to bfd_octets_per_byte. * ldlang (init_opb): New argument s. Set opb_shift to 0 if SEC_ELF_OCTETS for the current section is set. (print_input_section): Pass current section to init_opb. (print_data_statement,print_reloc_statement, print_padding_statement): Likewise. (lang_check_section_addresses): Call init_opb for each section. (lang_size_sections_1,lang_size_sections_1, lang_do_assignments_1): Likewise. (lang_process): Pass NULL to init_opb.
2019-11-22Arm: Change CRC from fpu feature to archititectural extensionMihail Ionescu2-16/+26
This patch changes the CRC extension to use the core feature bits instead of the coproc/fpu feature bits. CRC is not an fpu feature and it causes issues with the new fpu reset patch (f439988037a589de3798f44e7268301adaec21a9). CRC can be set using the '.arch_extension' directive, which sets bits in the coproc bitfield. When a '.fpu' directive is encountered, the CRC feature bit gets removed and there is no way to set it back using '.fpu'. With this patch, CRC will be marked in the feature core bits, which prevents it from getting removed when setting/changing the fpu options. gas/ChangeLog: * config/tc-arm.c (arm_ext_crc): New. (crc_ext_armv8): Remove. (insns): Rename crc_ext_armv8 to arm_ext_crc. (arm_cpus): Replace CRC_EXT_ARMV8 with ARM_EXT2_CRC. (armv8a_ext_table, armv8r_ext_table, arm_option_extension_value_table): Redefine the crc extension in terms of ARM_EXT2_CRC. * gas/testsuite/gas/arm/crc-ext.s: New. * gas/testsuite/gas/arm/crc-ext.d: New. include/ChangeLog: * opcode/arm.h (ARM_EXT2_CRC): New extension feature to replace CRC_EXT_ARMV8. (CRC_EXT_ARMV8): Remove and mark bit as unused. (ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A, ARM_ARCH_V8_3A, ARM_ARCH_V8_4A, ARM_ARCH_V8_5A, ARM_ARCH_V8_6A): Redefine using ARM_EXT2_CRC instead of CRC_EXT_ARMV8. opcodes/ChangeLog: * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes): Change the coproc CRC conditions to use the extension feature set, second word, base on ARM_EXT2_CRC.
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