| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2023-10-20 | bfd: microblaze: Add 32_NONE reloc type | Neal Frager | 1 | -0/+1 |
| 2023-10-19 | RISC-V: Remove semicolons from DECLARE_INSN | Tsukasa OI | 1 | -15/+15 |
| 2023-10-17 | RISC-V: Fix typo | Tsukasa OI | 1 | -1/+1 |
| 2023-10-10 | LoongArch/GAS: Add support for branch relaxation | mengqinggang | 1 | -0/+12 |
| 2023-10-08 | as: add option for generate R_LARCH_32/64_PCREL. | cailulu | 1 | -0/+1 |
| 2023-10-07 | Revert "opcodes: microblaze: Add new bit-field instructions" | Michael J. Eager | 1 | -1/+0 |
| 2023-10-06 | gdb: support rseq auxvs | Ilya Leoshkevich | 1 | -0/+2 |
| 2023-10-06 | opcodes: microblaze: Add new bit-field instructions | Neal Frager | 1 | -0/+1 |
| 2023-10-04 | aarch64: system register aliasing detection | Victor Do Nascimento | 1 | -0/+1 |
| 2023-09-29 | x86-64: Add -z mark-plt and -z nomark-plt | H.J. Lu | 1 | -0/+5 |
| 2023-09-28 | Add support to readelf for the PT_OPENBSD_NOBTCFI segment type. | Frederic Cambus | 2 | -0/+5 |
| 2023-09-26 | aarch64: Allow feature flags to occupy >64 bits | Richard Sandiford | 1 | -23/+39 |
| 2023-09-26 | aarch64: Restructure feature flag handling | Richard Sandiford | 1 | -151/+268 |
| 2023-09-25 | Revert "arc: Update opcode related include files for ARCv3." | Claudiu Zissulescu | 6 | -452/+96 |
| 2023-09-25 | arc: Update opcode related include files for ARCv3. | Claudiu Zissulescu | 6 | -96/+452 |
| 2023-09-05 | RISC-V: fold duplicate code in vector_macro() | Jan Beulich | 1 | -1/+0 |
| 2023-09-05 | RISC-V: Add 'Smcntrpmf' extension and its CSRs | Tsukasa OI | 1 | -4/+12 |
| 2023-08-27 | PE dos_message | Alan Modra | 3 | -3/+3 |
| 2023-08-22 | aarch64: Improve naming conventions for A and R-profile architecture | Victor Do Nascimento | 1 | -54/+54 |
| 2023-08-21 | bpf: correct neg and neg32 instruction encoding | David Faust | 1 | -2/+2 |
| 2023-08-21 | aarch64/sme2: Teach binutils/BFD about the NT_ARM_ZT register set | Luis Machado | 1 | -0/+2 |
| 2023-08-16 | kvx: New port. | Paul Iannetta | 4 | -0/+3356 |
| 2023-08-15 | RISC-V: Make "fli.h" available to 'Zvfh' + 'Zfa' | Tsukasa OI | 1 | -0/+1 |
| 2023-08-15 | RISC-V: Add support for the 'Zihintntl' extension | Tsukasa OI | 2 | -0/+28 |
| 2023-08-15 | RISC-V: remove indirection from register tables | Jan Beulich | 1 | -7/+9 |
| 2023-08-12 | gcc: xtensa: add data alignment properties to dynconfig | Max Filippov | 1 | -1/+58 |
| 2023-08-12 | gcc: xtensa: add XCHAL_HAVE_{CLAMPS, DEPBITS, EXCLUSIVE, XEA3} to dynconfig | Max Filippov | 1 | -1/+49 |
| 2023-08-12 | LoongArch: implement count_{leading,trailing}_zeros | Xi Ruoyao | 1 | -0/+12 |
| 2023-08-12 | Updated constants from <https://dwarfstd.org/Languages.php> | Meghan Denny | 1 | -0/+10 |
| 2023-08-12 | c++: source position of lambda captures [PR84471] | Jason Merrill | 1 | -1/+1 |
| 2023-08-12 | Libvtv: Add loongarch support. | Lulu Cheng | 1 | -0/+4 |
| 2023-08-03 | Remove PEI_HEADERS define | Tom Tromey | 4 | -0/+21 |
| 2023-08-02 | Revert "2.41 Release sources" | Sam James | 6 | -3/+92 |
| 2023-08-02 | 2.41 Release sourcesbinutils-2_41-release | Nick Clifton | 6 | -92/+3 |
| 2023-07-30 | bpf: include, bfd, opcodes: add EF_BPF_CPUVER ELF header flags | Jose E. Marchesi | 3 | -1/+12 |
| 2023-07-25 | bpf: Add atomic compare-and-exchange instructions | David Faust | 1 | -1/+5 |
| 2023-07-24 | bpf: gas,include,opcode: add suppor for instructions BSWAP{16,32,64} | Jose E. Marchesi | 2 | -0/+13 |
| 2023-07-24 | bpf: add support for jal/gotol jump instruction with 32-bit target | Jose E. Marchesi | 2 | -1/+7 |
| 2023-07-21 | bpf: opcodes, gas: support for signed load V4 instructions | Jose E. Marchesi | 2 | -0/+9 |
| 2023-07-21 | bpf: opcodes, gas: support for signed register move V4 instructions | Jose E. Marchesi | 2 | -0/+13 |
| 2023-07-21 | DesCGENization of the BPF binutils port | Jose E. Marchesi | 3 | -0/+308 |
| 2023-07-18 | RISC-V: Supports Zcb extension. | Jiawei | 2 | -0/+52 |
| 2023-07-14 | AIX_WEAK_SUPPORT | Alan Modra | 1 | -1/+1 |
| 2023-07-03 | RISC-V: Zvkh[a,b]: Remove individual instruction class | Christoph Müllner | 1 | -2/+0 |
| 2023-07-03 | Add markers for the 2.41 branch | Nick Clifton | 1 | -0/+4 |
| 2023-07-01 | RISC-V: Add support for the Zvksh ISA extension | Christoph Müllner | 2 | -0/+9 |
| 2023-07-01 | RISC-V: Add support for the Zvksed ISA extension | Christoph Müllner | 2 | -0/+12 |
| 2023-07-01 | RISC-V: Add support for the Zvknh[a,b] ISA extensions | Christoph Müllner | 2 | -0/+14 |
| 2023-07-01 | RISC-V: Add support for the Zvkned ISA extension | Christoph Müllner | 2 | -0/+36 |
| 2023-07-01 | RISC-V: Add support for the Zvkg ISA extension | Christoph Müllner | 2 | -0/+9 |
