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2022-09-21RISC-V: Implement Ztso extensionShihua1-0/+3
This patch support ZTSO extension. It will turn on the tso flag for elf_flags once we have enabled Ztso extension. This is intended to implement v0.1 of the proposed specification which can be found in Chapter 25 of, https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf. bfd\ChangeLog: * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Set TSO flag. * elfxx-riscv.c: Add Ztso's arch. binutils\ChangeLog: * readelf.c (get_machine_flags): Set TSO flag. gas\ChangeLog: * config/tc-riscv.c (riscv_set_tso): Ditto. (riscv_set_arch): Ditto. * testsuite/gas/riscv/ztso.d: New test. include\ChangeLog: * elf/riscv.h (EF_RISCV_TSO): Ditto.
2022-09-12ppc: Document the -mfuture and -Mfuture options and make them usablePeter Bergner1-0/+3
The -mfuture and -Mfuture options which are used for adding potential new ISA instructions were not documented. They also lacked a bitmask so new instructions could not be enabled by those options. Fixed. binutils/ * doc/binutils.texi: Document -Mfuture. gas/ * config/tc-ppc.c: Document -mfuture * doc/c-ppc.texi: Likewise. include/ * opcode/ppc.h (PPC_OPCODE_FUTURE): Define. opcodes/ * ppc-dis.c (ppc_opts) <future>: Use it. * ppc-opc.c (FUTURE): Define.
2022-09-06opcodes: Add non-enum disassembler optionsTsukasa OI1-1/+2
This is paired with "gdb: Add non-enum disassembler options". There is a portable mechanism for disassembler options and used on some architectures: - ARC - Arm - MIPS - PowerPC - RISC-V - S/390 However, it only supports following forms: - [NAME] - [NAME]=[ENUM_VALUE] Valid values for [ENUM_VALUE] must be predefined in disasm_option_arg_t.values. For instance, for -M cpu=[CPU] in ARC architecture, opcodes/arc-dis.c builds valid CPU model list from include/elf/arc-cpu.def. In this commit, it adds following format: - [NAME]=[ARBITRARY_VALUE] (cannot contain "," though) This is identified by NULL value of disasm_option_arg_t.values (normally, this is a non-NULL pointer to a NULL-terminated list). include/ChangeLog: * dis-asm.h (disasm_option_arg_t): Update comment of values to allow non-enum disassembler options. opcodes/ChangeLog: * riscv-dis.c (print_riscv_disassembler_options): Support non-enum disassembler options on printing disassembler help. * arc-dis.c (print_arc_disassembler_options): Likewise. * mips-dis.c (print_mips_disassembler_options): Likewise.
2022-08-30RISC-V: Add 'Zmmul' extension in assembler.Tsukasa OI1-0/+1
Three-part patch set from Tsukasa OI to support zmmul in assembler. The 'Zmmul' is a RISC-V extension consisting of only multiply instructions (a subset of 'M' which has multiply and divide instructions). bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Add 'Zmmul' implied by 'M'. (riscv_supported_std_z_ext): Add 'Zmmul' extension. (riscv_multi_subset_supports): Add handling for new instruction class. gas/ * testsuite/gas/riscv/attribute-09.d: Updated implicit 'Zmmul' by 'M'. * testsuite/gas/riscv/option-arch-02.d: Likewise. * testsuite/gas/riscv/m-ext.s: New test. * testsuite/gas/riscv/m-ext-32.d: New test (RV32). * testsuite/gas/riscv/m-ext-64.d: New test (RV64). * testsuite/gas/riscv/zmmul-32.d: New expected output. * testsuite/gas/riscv/zmmul-64.d: Likewise. * testsuite/gas/riscv/m-ext-fail-xlen-32.d: New test (failure by using RV64-only instructions in RV32). * testsuite/gas/riscv/m-ext-fail-xlen-32.l: Likewise. * testsuite/gas/riscv/m-ext-fail-zmmul-32.d: New failure test (RV32 + Zmmul but with no M). * testsuite/gas/riscv/m-ext-fail-zmmul-32.l: Likewise. * testsuite/gas/riscv/m-ext-fail-zmmul-64.d: New failure test (RV64 + Zmmul but with no M). * testsuite/gas/riscv/m-ext-fail-zmmul-64.l: Likewise. * testsuite/gas/riscv/m-ext-fail-noarch-64.d: New failure test (no Zmmul or M). * testsuite/gas/riscv/m-ext-fail-noarch-64.l: Likewise. include/ * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZMMUL. ld/ * testsuite/ld-riscv-elf/attr-merge-arch-01.d: We don't care zmmul in these testcases, so just replaced m by a. * testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-01b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p0.s: Renamed. * testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p1.s: Renamed. opcodes/ * riscv-opc.c (riscv_opcodes): Updated multiply instructions to zmmul.
2022-08-11ppc/svp64: introduce non-zero operand flagDmitry Selyutin1-0/+5
svstep and svshape instructions subtract 1 before encoding some of the operands. Obviously zero is not supported for these operands. Whilst PPC_OPERAND_PLUS1 fits perfectly to mark that maximal value should be incremented, there is no flag which marks the fact that zero values are not allowed. This patch adds a new flag, PPC_OPERAND_NONZERO, for this purpose.
2022-08-11ppc/svp64: support LibreSOC architectureDmitry Selyutin1-0/+3
This patch adds support for LibreSOC machine and SVP64 extension flag for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit Prefixed instruction format implementing SV. Funded by NLnet through EU Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly submitted via the OpenPOWER Foundation ISA Working Group via the newly-created External RFC Process. For more details, visit https://libre-soc.org.
2022-08-10RISC-V: Remove R_RISCV_GNU_VTINHERIT/R_RISCV_GNU_VTENTRYFangrui Song1-2/+0
They were legacy relocation types copied from other ports. The related -fvtable-gc was removed from GCC in 2003. The associated assembler directives (.vtable_inherit and .vtable_entry) have never been supported by the RISC-V port. Remove related ld code. Link: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/323
2022-08-10bfd: Add support for LoongArch64 EFI (efi-*-loongarch64).Youling Tang2-0/+62
This adds support for efi-loongarch64 by virtue of adding a new PEI target pei-loongarch64. This is not a full target and only exists to support EFI at this time. This means that this target does not support relocation processing and is mostly a container format. This format has been added to elf based loongarch64 targets such that efi images can be made natively on Linux. However this target is not valid for use with gas but only with objcopy. We should't limit addresses to 32-bits for 64-bit vma, otherwise there will be "RVA truncated" error when using objcopy on loongarch64. With these changes the resulting file is recognized as an efi image. Any magic number is based on the Microsoft PE specification [1]. The test results are as follows: $ make check-binutils RUNTESTFLAGS='loongarch64.exp' PASS: Check if efi app format is recognized $ objdump -h -f tmpdir/loongarch64copy.o tmpdir/loongarch64copy.o: file format pei-loongarch64 architecture: Loongarch64, flags 0x00000132: EXEC_P, HAS_SYMS, HAS_LOCALS, D_PAGED start address 0x0000000000000000 Sections: Idx Name Size VMA LMA File off Algn 0 .text 0000003c 00000000200000b0 00000000200000b0 00000200 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE [1] https://docs.microsoft.com/en-us/windows/win32/debug/pe-format bfd: * .gitignore (pe-loongarch64igen.c): New. * Makefile.am (pei-loongarch64.lo, pe-loongarch64igen.lo, pei-loongarch64.c, pe-loongarch64igen.c): Add support. * Makefile.in: Likewise. * bfd.c (bfd_get_sign_extend_vma): Add pei-loongarch64. * coff-loongarch64.c: New file. * coffcode.h (coff_set_arch_mach_hook, coff_set_flags, coff_write_object_contents) Add loongarch64 (loongarch64_pei_vec) support. * config.bfd: Likewise. * configure: Likewise. * configure.ac: Likewise. * libpei.h (GET_OPTHDR_IMAGE_BASE, PUT_OPTHDR_IMAGE_BASE, GET_OPTHDR_SIZE_OF_STACK_RESERVE, PUT_OPTHDR_SIZE_OF_STACK_RESERVE, GET_OPTHDR_SIZE_OF_STACK_COMMIT, PUT_OPTHDR_SIZE_OF_STACK_COMMIT, GET_OPTHDR_SIZE_OF_HEAP_RESERVE, PUT_OPTHDR_SIZE_OF_HEAP_RESERVE, GET_OPTHDR_SIZE_OF_HEAP_COMMIT, PUT_OPTHDR_SIZE_OF_HEAP_COMMIT, GET_PDATA_ENTRY, _bfd_peLoongArch64_bfd_copy_private_bfd_data_common, _bfd_peLoongArch64_bfd_copy_private_section_data, _bfd_peLoongArch64_get_symbol_info, _bfd_peLoongArch64_only_swap_filehdr_out, _bfd_peLoongArch64_print_private_bfd_data_common, _bfd_peLoongArch64i_final_link_postscript, _bfd_peLoongArch64i_only_swap_filehdr_out, _bfd_peLoongArch64i_swap_aouthdr_in, _bfd_peLoongArch64i_swap_aouthdr_out, _bfd_peLoongArch64i_swap_aux_in, _bfd_peLoongArch64i_swap_aux_out, _bfd_peLoongArch64i_swap_lineno_in, _bfd_peLoongArch64i_swap_lineno_out, _bfd_peLoongArch64i_swap_scnhdr_out, _bfd_peLoongArch64i_swap_sym_in, _bfd_peLoongArch64i_swap_sym_out, _bfd_peLoongArch64i_swap_debugdir_in, _bfd_peLoongArch64i_swap_debugdir_out, _bfd_peLoongArch64i_write_codeview_record, _bfd_peLoongArch64i_slurp_codeview_record, _bfd_peLoongArch64_print_ce_compressed_pdata): New. * peXXigen.c (_bfd_XXi_swap_aouthdr_in, _bfd_XXi_swap_aouthdr_out, _bfd_XXi_swap_scnhdr_out, pe_print_pdata, _bfd_XX_print_private_bfd_data_common, _bfd_XX_bfd_copy_private_section_data, _bfd_XXi_final_link_postscript): Support COFF_WITH_peLoongArch64, * pei-loongarch64.c: New file. * peicode.h (coff_swap_scnhdr_in, pe_ILF_build_a_bfd, pe_ILF_object_p): Support COFF_WITH_peLoongArch64. (jtab): Add dummy entry that traps. * targets.c (loongarch64_pei_vec): New. binutils * testsuite/binutils-all/loongarch64/loongarch64.exp: New file. * testsuite/binutils-all/loongarch64/pei-loongarch64.d: New test. * testsuite/binutils-all/loongarch64/pei-loongarch64.s: New test. include * coff/loongarch64.h: New file. * coff/pe.h (IMAGE_FILE_MACHINE_LOONGARCH64): New. Signed-off-by: Youling Tang <tangyouling@loongson.cn>
2022-08-02Add ELFCOMPRESS_ZSTD.Cary Coutant1-0/+2
include/elf/ * common.h: Add ELFCOMPRESS_ZSTD.
2022-07-29libopcodes/aarch64: add support for disassembler stylingAndrew Burgess1-1/+27
This commit enables disassembler styling for AArch64. After this commit it is possible to have objdump style AArch64 disassembler output (using --disassembler-color option). Once the required GDB patches are merged, GDB will also style the disassembler output. The changes to support styling are mostly split between two files opcodes/aarch64-dis.c and opcodes/aarch64-opc.c. The entry point for the AArch64 disassembler can be found in aarch64-dis.c, this file handles printing the instruction mnemonics, and assembler directives (e.g. '.byte', '.word', etc). Some operands, mostly relating to assembler directives are also printed from this file. This commit changes all of this to pass through suitable styling information. However, for most "normal" instructions, the instruction operands are printed using a two step process. From aarch64-dis.c, in the print_operands function, the function aarch64_print_operand is called, this function is in aarch64-opc.c, and converts an instruction operand into a string. Then, back in print_operands (aarch64-dis.c), the operand string is printed. Unfortunately, the string returned by aarch64_print_operand can be quite complex, it will include syntax elements, like '[' and ']', in addition to register names and immediate values. In some cases, a single operand will expand into what will appear (to the user) as multiple operands separated with a ','. This makes the task of styling more complex, all these different components need to by styled differently, so we need to get the styling information out of aarch64_print_operand in some way. The solution that I propose here is similar to the solution that I used for the i386 disassembler. Currently, aarch64_print_operand uses snprintf to write the operand text into a buffer provided by the caller. What I propose is that we pass an extra argument to the aarch64_print_operand function, this argument will be a structure, the structure contains a callback function and some state. When aarch64_print_operand needs to format part of its output this can be done by using the callback function within the new structure, this callback returns a string with special embedded markers that indicate which mode should be used for each piece of text. Back in aarch64-dis.c we can spot these special style markers and use this to split the disassembler output up and apply the correct style to each piece. To make aarch64-opc.c clearer a series of new static functions have been added, e.g. 'style_reg', 'style_imm', etc. Each of these functions formats a piece of text in a different style, 'register' and 'immediate' in this case. Here's an example taken from aarch64-opc.c of the new functions in use: snprintf (buf, size, "[%s, %s]!", style_reg (styler, base), style_imm (styler, "#%d", opnd->addr.offset.imm)); The aarch64_print_operand function is also called from the assembler to aid in printing diagnostic messages. Right now I have no plans to add styling to the assembler output, and so, the callback function used in the assembler ignores the styling information and just returns an plain string. I've used the source files in gas/testsuite/gas/aarch64/ for testing, and have manually gone through and checked that the styling looks reasonable, however, I'm not an AArch64 expert, so it is possible that the odd piece is styled incorrectly. Please point out any mistakes I've made. With objdump disassembler color turned off, there should be no change in the output after this commit.
2022-07-25opcodes: add new sub-mnemonic disassembler styleAndrew Burgess1-0/+7
When adding libopcodes disassembler styling support for AArch64, it feels like the results would be improved by having a new sub-mnemonic style. This will be used in cases like: add w16, w7, w1, uxtb #2 ^^^^----- Here And: cinc w0, w1, ne ^^----- Here This commit just adds the new style, and prepares objdump to handle the style. A later commit will add AArch64 styling, and will actually make use of the style. As this style is currently unused, there should be no user visible changes after this commit.
2022-07-25bfd: Delete R_LARCH_NONE from dyn info of LoongArch.liuzhensong1-1/+4
Some R_LARCH_64 in section .eh_frame will to generate R_LARCH_NONE, we change relocation to R_LARCH_32_PCREL from R_LARCH_64 in setction .eh_frame and not generate dynamic relocation for R_LARCH_32_PCREL. Add New relocate type R_LARCH_32_PCREL for .eh_frame. include/elf/ loongarch.h bfd/ bfd/bfd-in2.h libbfd.h reloc.c elfxx-loongarch.c elfnn-loongarch.c gas/config/ tc-loongarch.c binutils/ readelf.c ld/testsuite/ld-elf/ eh5.d
2022-07-25bfd: Add supported for LoongArch new relocations.liuzhensong1-0/+136
Define new reloc types according to linker needs. include/elf/ loongarch.h bfd/ bfd-in2.h libbfd.h reloc.c elfnn-loongarch.c elfxx-loongarch.c elfxx-loongarch.h
2022-07-19[AArch64] Support AArch64 MTE memory tag dumps in core filesLuis Machado1-0/+3
The Linux kernel can dump memory tag segments to a core file, one segment per mapped range. The format and documentation can be found in the Linux kernel tree [1]. The following patch adjusts bfd and binutils so they can handle this new segment type and display it accordingly. It also adds code required so GDB can properly read/dump core file data containing memory tags. Upon reading, each segment that contains memory tags gets mapped to a section named "memtag". These sections will be used by GDB to lookup the tag data. There can be multiple such sections with the same name, and they are not numbered to simplify GDB's handling and lookup. There is another patch for GDB that enables both reading and dumping of memory tag segments. Tested on aarch64-linux Ubuntu 20.04. [1] Documentation/arm64/memory-tagging-extension.rst (Core Dump Support)
2022-07-12LTO plugin: sync header file with GCCMartin Liska1-0/+33
include/ChangeLog: * plugin-api.h (enum ld_plugin_tag): Sync with GCC.
2022-07-08Add markers for 2.39 branchNick Clifton1-0/+4
2022-07-07RISC-V: Added Zfhmin and Zhinxmin.Tsukasa OI1-3/+4
This commit adds Zfhmin and Zhinxmin extensions (subsets of Zfh and Zhinx extensions, respectively). In the process supporting Zfhmin and Zhinxmin extension, this commit also changes how instructions are categorized considering Zfhmin, Zhinx and Zhinxmin extensions. Detailed changes, * From INSN_CLASS_ZFH to INSN_CLASS_ZFHMIN: flh, fsh, fmv.x.h and fmv.h.x. * From INSN_CLASS_ZFH to INSN_CLASS_ZFH_OR_ZHINX: fmv.h. * From INSN_CLASS_ZFH_OR_ZHINX to INSN_CLASS_ZFH_OR_ZHINX: fneg.h, fabs.h, fsgnj.h, fsgnjn.h, fsgnjx.h, fadd.h, fsub.h, fmul.h, fdiv.h, fsqrt.h, fmin.h, fmax.h, fmadd.h, fnmadd.h, fmsub.h, fnmsub.h, fcvt.w.h, fcvt.wu.h, fcvt.h.w, fcvt.h.wu, fcvt.l.h, fcvt.lu.h, fcvt.h.l, fcvt.h.lu, feq.h, flt.h, fle.h, fgt.h, fge.h, fclass.h. * From INSN_CLASS_ZFH_OR_ZHINX to INSN_CLASS_ZFHMIN_OR_ZHINXMIN: fcvt.s.h and fcvt.h.s. * From INSN_CLASS_D_AND_ZFH_INX to INSN_CLASS_ZFHMIN_AND_D: fcvt.d.h and fcvt.h.d. * From INSN_CLASS_Q_AND_ZFH_INX to INSN_CLASS_ZFHMIN_AND_Q: fcvt.q.h and fcvt.h.q. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Change implicit subsets. Zfh->Zicsr is not needed and Zfh->F is replaced with Zfh->Zfhmin and Zfhmin->F. Zhinx->Zicsr is not needed and Zhinx->Zfinx is replaced with Zhinx->Zhinxmin and Zhinxmin->Zfinx. (riscv_supported_std_z_ext): Added zfhmin and zhinxmin. (riscv_multi_subset_supports): Rewrite handling for new instruction classes. (riscv_multi_subset_supports_ext): Updated. (riscv_parse_check_conflicts): Change error message to include zfh and zfhmin extensions. gas/ChangeLog: * testsuite/gas/riscv/zfhmin-d-insn-class-fail.s: New complex error handling test. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l: Likewise. * testsuite/gas/riscv/zhinx.d: Renamed from fp-zhinx-insns.d and refactored. * testsuite/gas/riscv/zhinx.s: Likewise. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Removed INSN_CLASS_ZFH, INSN_CLASS_D_AND_ZFH_INX and INSN_CLASS_Q_AND_ZFH_INX. Added INSN_CLASS_ZFHMIN, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, INSN_CLASS_ZFHMIN_AND_D and INSN_CLASS_ZFHMIN_AND_Q. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Change instruction classes for Zfh and Zfhmin instructions. Fix `fcvt.h.lu' instruction (two operand variant) mask.
2022-06-29opcodes/aarch64: split off creation of comment text in disassemblerAndrew Burgess1-1/+1
The function aarch64_print_operand (aarch64-opc.c) is responsible for converting an instruction operand into the textual representation of that operand. In some cases, a comment is included in the operand representation, though this (currently) only happens for the last operand of the instruction. In a future commit I would like to enable the new libopcodes styling for AArch64, this will allow objdump and GDB[1] to syntax highlight the disassembler output, however, having operands and comments combined in a single string like this makes such styling harder. In this commit, I propose to extend aarch64_print_operand to take a second buffer. Any comments for the instruction are written into this extra buffer. The two callers of aarch64_print_operand are then updated to pass an extra buffer, and print any resulting comment. In this commit no styling is added, that will come later. However, I have adjusted the output slightly. Before this commit some comments would be separated from the instruction operands with a tab character, while in other cases the comment was separated with two single spaces. After this commit I use a single tab character in all cases. This means a few test cases needed updated. If people would prefer me to move everyone to use the two spaces, then just let me know. Or maybe there was a good reason why we used a mix of styles, I could probably figure out a way to maintain the old output exactly if that is critical. Other than that, there should be no user visible changes after this commit. [1] GDB patches have not been merged yet, but have been posted to the GDB mailing list: https://sourceware.org/pipermail/gdb-patches/2022-June/190142.html
2022-06-28RISC-V: Add 'Sstc' extension and its CSRsTsukasa OI1-0/+10
This commit adds "stimecmp / vstimecmp" Extension (Sstc) and its CSRs. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Sstc' extension to valid 'S' extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Sstc' extension. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_STIMECMP, CSR_STIMECMPH, CSR_VSTIMECMP, CSR_VSTIMECMPH): New CSR macros.
2022-06-28RISC-V: Add 'Sscofpmf' extension with its CSRsTsukasa OI1-0/+62
This commit adds Count Overflow and Mode-Based Filtering Extension (Sscofpmf) and its CSRs. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Sscofpmf' extension to valid 'S' extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Sscofpmf' extension. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_SCOUNTOVF, CSR_MHPMEVENT3H, CSR_MHPMEVENT4H, CSR_MHPMEVENT5H, CSR_MHPMEVENT6H, CSR_MHPMEVENT7H, CSR_MHPMEVENT8H, CSR_MHPMEVENT9H, CSR_MHPMEVENT10H, CSR_MHPMEVENT11H, CSR_MHPMEVENT12H, CSR_MHPMEVENT13H, CSR_MHPMEVENT14H, CSR_MHPMEVENT15H, CSR_MHPMEVENT16H, CSR_MHPMEVENT17H, CSR_MHPMEVENT18H, CSR_MHPMEVENT19H, CSR_MHPMEVENT20H, CSR_MHPMEVENT21H, CSR_MHPMEVENT22H, CSR_MHPMEVENT23H, CSR_MHPMEVENT24H, CSR_MHPMEVENT25H, CSR_MHPMEVENT26H, CSR_MHPMEVENT27H, CSR_MHPMEVENT28H, CSR_MHPMEVENT29H, CSR_MHPMEVENT30H, CSR_MHPMEVENT31H): New CSR macros.
2022-06-28RISC-V: Add 'Smstateen' extension and its CSRsTsukasa OI1-0/+42
This commit adds State Enable Extension (Smstateen) and its CSRs. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Smstateen' extension to valid 'S' extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Smstateen' extension. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_MSTATEEN0, CSR_MSTATEEN1, CSR_MSTATEEN2, CSR_MSTATEEN3, CSR_SSTATEEN0, CSR_SSTATEEN1, CSR_SSTATEEN2, CSR_SSTATEEN3, CSR_HSTATEEN0, CSR_HSTATEEN1, CSR_HSTATEEN2, CSR_HSTATEEN3, CSR_MSTATEEN0H, CSR_MSTATEEN1H, CSR_MSTATEEN2H, CSR_MSTATEEN3H, CSR_HSTATEEN0H, CSR_HSTATEEN1H, CSR_HSTATEEN2H, CSR_HSTATEEN3H): New CSR macros.
2022-06-27drop XC16x bitsJan Beulich1-40/+0
Commit 04f096fb9e25 ("Move the xc16x target to the obsolete list") moved the architecture from the "obsolete but still available" to the "obsolete / support removed" list in config.bfd, making the architecture impossible to enable (except maybe via "enable everything" options"). Note that I didn't touch */po/*.po{,t} on the assumption that these would be updated by some (half)automatic means.
2022-06-22RISC-V: Use single h extension to control hypervisor CSRs and instructions.Nelson Chu2-25/+26
According to the picture 28.1 in the current ISA spec, h is no larger the multi-letter extension, it is a single extension after v. Therefore, this patch fix the implementation, and use the single h to control hypervisor CSRs and instructions, which we promised to do before. bfd/ * elfxx-riscv.c (riscv_supported_std_ext): Added h with version 1.0 after v. (riscv_supported_std_h_ext): Removed. (riscv_all_supported_ext): Updated since riscv_supported_std_h_ext is removed. (riscv_prefix_ext_class): Removed RV_ISA_CLASS_H. (parse_config): Updated since riscv_prefix_ext_class is removed. (riscv_recognized_prefixed_ext): Likewise. (riscv_get_default_ext_version): Likewise. (riscv_multi_subset_supports): Handle INSN_CLASS_H for hypervisor instructions. (riscv_multi_subset_supports_ext): Likewise. gas/ * config/tc-riscv.c (riscv_csr_class): Added CSR_CLASS_H and CSR_CLASS_H_32 for hypervisor CSRs. (riscv_csr_address): Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Updated since hypervisor CSRs are controlled by single h extension for now. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/h-ext-32.d: Added h to architecture string. * testsuite/gas/riscv/h-ext-64.d: Likewise. * testsuite/gas/riscv/march-fail-single-prefix-h: Removed since h is no longer multi-letter extension. * testsuite/gas/riscv/march-fail-unknown-h.d: Likewise. include/ * opcode/riscv-opc.h: Control hypervisor CSRs by h extension, rather than the privileged spec verisons. * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_H. opcodes/ * riscv-opc.c (riscv_opcodes): Control hypervisor instructions by h extension.
2022-06-15[gdb/build] Fix build for gcc < 11Tom de Vries1-0/+2
When building trunk on openSUSE Leap 15.3 with system gcc 7.5.0, I run into: ... In file included from ../bfd/bfd.h:46:0, from gdb/defs.h:37, from gdb/debuginfod-support.c:19: gdb/debuginfod-support.c: In function ‘bool debuginfod_is_enabled()’: gdb/../include/diagnostics.h:42:3: error: unknown option after \ ‘#pragma GCC diagnostic’ kind [-Werror=pragmas] _Pragma (DIAGNOSTIC_STRINGIFY (GCC diagnostic ignored option)) ^ gdb/../include/diagnostics.h:80:3: note: in expansion of macro \ ‘DIAGNOSTIC_IGNORE’ DIAGNOSTIC_IGNORE ("-Wstringop-overread") ^~~~~~~~~~~~~~~~~ gdb/debuginfod-support.c:201:4: note: in expansion of macro \ ‘DIAGNOSTIC_IGNORE_STRINGOP_OVERREAD’ DIAGNOSTIC_IGNORE_STRINGOP_OVERREAD ^ ... The problem is that the warning -Wstringop-overread has been introduced for gcc 11, and we can only tell gcc to ignore if it knows about it. Fix this by guarding the DIAGNOSTIC_IGNORE_STRINGOP_OVERREAD definition in diagnostics.c with '#if __GNUC__ >= 11'. Tested on x86_64-linux, by completing a build.
2022-06-08HOWTO size encodingAlan Modra1-69/+69
This changes the HOWTO macro to encode the howto.size field from a value given in bytes. This of course requires editing all target uses of HOWTO, a major pain, but makes it a little nicer to specify new target HOWTOs. Object files before/after this patch are unchanged in .data and .rodata. bfd/ * reloc.c (HOWTO_RSIZE): Encode size in bytes. (EMPTY_HOWTO): Adjust to keep it all zero. * aout-ns32k.c, * aoutx.h, * coff-alpha.c, * coff-arm.c, * coff-i386.c, * coff-mcore.c, * coff-mips.c, * coff-rs6000.c, * coff-sh.c, * coff-tic30.c, * coff-tic4x.c, * coff-tic54x.c, * coff-x86_64.c, * coff-z80.c, * coff-z8k.c, * coff64-rs6000.c, * elf-hppa.h, * elf-m10200.c, * elf-m10300.c, * elf32-arc.c, * elf32-arm.c, * elf32-avr.c, * elf32-bfin.c, * elf32-cr16.c, * elf32-cris.c, * elf32-crx.c, * elf32-csky.c, * elf32-d10v.c, * elf32-d30v.c, * elf32-dlx.c, * elf32-epiphany.c, * elf32-fr30.c, * elf32-frv.c, * elf32-ft32.c, * elf32-gen.c, * elf32-h8300.c, * elf32-i386.c, * elf32-ip2k.c, * elf32-iq2000.c, * elf32-lm32.c, * elf32-m32c.c, * elf32-m32r.c, * elf32-m68hc11.c, * elf32-m68hc12.c, * elf32-m68k.c, * elf32-mcore.c, * elf32-mep.c, * elf32-metag.c, * elf32-microblaze.c, * elf32-mips.c, * elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c, * elf32-nios2.c, * elf32-or1k.c, * elf32-pj.c, * elf32-ppc.c, * elf32-pru.c, * elf32-rl78.c, * elf32-rx.c, * elf32-s12z.c, * elf32-s390.c, * elf32-score.c, * elf32-score7.c, * elf32-sh-relocs.h, * elf32-spu.c, * elf32-tic6x.c, * elf32-tilepro.c, * elf32-v850.c, * elf32-vax.c, * elf32-visium.c, * elf32-wasm32.c, * elf32-xc16x.c, * elf32-xgate.c, * elf32-xstormy16.c, * elf32-xtensa.c, * elf32-z80.c, * elf64-alpha.c, * elf64-bpf.c, * elf64-gen.c, * elf64-mips.c, * elf64-mmix.c, * elf64-nfp.c, * elf64-ppc.c, * elf64-s390.c, * elf64-x86-64.c, * elfn32-mips.c, * elfnn-aarch64.c, * elfxx-ia64.c, * elfxx-loongarch.c, * elfxx-mips.c, * elfxx-riscv.c, * elfxx-sparc.c, * elfxx-tilegx.c, * mach-o-aarch64.c, * mach-o-arm.c, * mach-o-i386.c, * mach-o-x86-64.c, * pdp11.c, * reloc.c, * som.c, * vms-alpha.c: Adjust all uses of HOWTO. * bfd-in2.h: Regenerate. include/ * elf/arc-reloc.def: Adjust all uses of HOWTO.
2022-05-31Import libiberty from gccAlan Modra2-42/+8
PR 29200 include/ * ansidecl.h, * demangle.h: Import from gcc. libiberty/ * cp-demangle.c, * testsuite/demangle-expected: Import from gcc.
2022-05-30RISC-V: Add zhinx extension supports.jiawei1-2/+3
The zhinx extension is a sub-extension in zfinx, corresponding to zfh extension but use GPRs instead of FPRs. This patch expanded the zfh insn class define, since zfh and zhinx use the same opcodes, thanks for Nelson's works. changelog in V2: Add missing classes of 'zfh' and 'zhinx' in "riscv_multi_subset_supports_ext". bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extensions. (riscv_multi_subset_supports_ext): New extensions. gas/ChangeLog: * testsuite/gas/riscv/fp-zhinx-insns.d: New test. * testsuite/gas/riscv/fp-zhinx-insns.s: New test. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): New INSN classes. opcodes/ChangeLog: * riscv-opc.c: Modify INSN_CLASS.
2022-05-27Replace bfd_hostptr_t with uintptr_tAlan Modra1-6/+6
bfd_hostptr_t is defined as a type large enough to hold either a long or a pointer. It mostly appears in the coff backend code in casts. include/coff/internal.h struct internal_syment and union internal_auxent have the only uses in data structures, where comparison with include/coff/external.h and other code reveals that the type only needs to be large enough for a 32-bit integer or a pointer. That should mean replacing with uintptr_t is OK.
2022-05-27Remove use of bfd_uint64_t and similarAlan Modra3-33/+33
Requiring C99 means that uses of bfd_uint64_t can be replaced with uint64_t, and similarly for bfd_int64_t, BFD_HOST_U_64_BIT, and BFD_HOST_64_BIT. This patch does that, removes #ifdef BFD_HOST_* and tidies a few places that print 64-bit values.
2022-05-25ppc: extend opindex to 16 bitsDmitry Selyutin1-1/+7
With the upcoming SVP64 extension[0] to PowerPC architecture, it became evident that PowerPC operand indices no longer fit 8 bits. This patch switches the underlying type to uint16_t, also introducing a special typedef so that any future extension goes even smoother. [0] https://libre-soc.org include/ * opcode/ppc.h (ppc_opindex_t): New typedef. (struct powerpc_opcode): Use it. (PPC_OPINDEX_MAX): Define. gas/ * write.h (struct fix): Increase size of fx_pcrel_adjust. Reorganise. * config/tc-ppc.c (insn_validate): Use ppc_opindex_t for operands. (md_assemble): Likewise. (md_apply_fix): Likewise. Mask fx_pcrel_adjust with PPC_OPINDEX_MAX. (ppc_setup_opcodes): Adjust opcode index assertion. opcodes/ * ppc-dis.c (skip_optional_operands): Use ppc_opindex_t for operand pointer. (lookup_powerpc, lookup_prefix, lookup_vle, lookup_spe2): Likewise. (print_insn_powerpc): Likewise.
2022-05-23ld: use definitions in generate_reloc rather than raw literalsMark Harmstone1-0/+16
2022-05-20RISC-V: Remove RV128-only fmv instructionsTsukasa OI1-6/+0
As fmv.x.q and fmv.q.x instructions are RV128-only (not RV64-only), it should be removed until RV128 support for GNU Binutils is required again. gas/ChangeLog: * testsuite/gas/riscv/fmv.x.q-rv64-fail.d: New failure test. * testsuite/gas/riscv/fmv.x.q-rv64-fail.l: Likewise. * testsuite/gas/riscv/fmv.x.q-rv64-fail.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_FMV_X_Q, MASK_FMV_X_Q, MATCH_FMV_Q_X, MASK_FMV_Q_X): Remove RV128-only instructions. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Remove RV128-only instructions.
2022-05-20Tidy warn-execstack handlingAlan Modra1-6/+3
Make ld and bfd values consistent by swapping values 0 and 2 in link_info.warn_execstack. This has the benefit of making the value an "extended" boolean, with 0 meaning no warning, 1 meaning warn, other values a conditional warning. Yes, this patch introduces fails on arm/aarch64. Not a problem with this patch but an arm/aarch64 before_parse problem. bfd/ * elflink.c (bfd_elf_size_dynamic_sections): Adjust warn_execstack test. include/ * bfdlink.h (warn_execstack): Swap 0 and 2 meaning. ld/ * configure.ac (DEFAULT_LD_WARN_EXECSTACK): Use values of 0, 1, 2 consistent with link_info.warn_execstack. * ld.texi: Typo fixes. * lexsup.c (parse_args): Adjust setting of link_info.warn_execstack. (elf_static_list_options): Adjust help message conditions. * configure: Regenerate.
2022-05-18AArch64: Enable FP16 by default for Armv9-A.Tamar Christina1-0/+1
In Armv9-A SVE is mandatory, and for SVE FP16 is mandatory. This fixes a disconnect between GCC and binutils where GCC has FP16 on by default and gas doesn't. include/ChangeLog: 2022-05-16 Tamar Christina <tamar.christina@arm.com> * opcode/aarch64.h (AARCH64_ARCH_V9_FEATURES): Add AARCH64_FEATURE_F16.
2022-05-17RISC-V: Added half-precision floating-point v1.0 instructions.Nelson Chu2-0/+77
bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Added implicit f and zicsr for zfh. (riscv_supported_std_z_ext): Added default v1.0 version for zfh. (riscv_multi_subset_supports): Handle INSN_CLASS_ZFH, INSN_CLASS_D_AND_ZFH and INSN_CLASS_Q_AND_ZFH. gas/ * config/tc-riscv.c (FLT_CHARS): Added "hH". (macro): Expand Pseudo M_FLH and M_FSH. (riscv_pseudo_table): Added .float16 directive. * testsuite/gas/riscv/float16-be.d: New testcase for .float16. * testsuite/gas/riscv/float16-le.d: Likewise. * testsuite/gas/riscv/float16.s: Likewise. * testsuite/gas/riscv/fp-zfh-insns.d: New testcase for zfh. * testsuite/gas/riscv/fp-zfh-insns.s: Likewise. include/ * opcode/riscv-opc.h: Added MASK and MATCH encodings for zfh. * opcode/riscv.h: Added INSN_CLASS and pseudo macros for zfh. opcodes/ * riscv-opc.c (riscv_opcodes): Added zfh instructions.
2022-05-13Import libiberty from gccAlan Modra3-27/+9
2022-05-10include: remove use of PTRAlan Modra1-2/+2
* hashtab.h (HTAB_EMPTY_ENTRY): Replace PTR with void *. (HTAB_DELETED_ENTRY): Likewise.
2022-05-09ansidecl.h: sync from GCCMartin Liska1-20/+3
include/ChangeLog: * ansidecl.h: Sync from GCC.
2022-05-04LTO: Handle __real_SYM reference in IRH.J. Lu1-0/+3
When an IR symbol SYM is referenced in IR via __real_SYM, its resolution should be LDPR_PREVAILING_DEF, not PREVAILING_DEF_IRONLY, since LTO doesn't know that __real_SYM should be resolved by SYM. bfd/ PR ld/29086 * linker.c (bfd_wrapped_link_hash_lookup): Mark SYM is referenced via __real_SYM. include/ PR ld/29086 * bfdlink.h (bfd_link_hash_entry): Add ref_real. ld/ PR ld/29086 * plugin.c (get_symbols): Resolve SYM definition to LDPR_PREVAILING_DEF for __real_SYM reference. * testsuite/ld-plugin/lto.exp: Run PR ld/29086 test. * testsuite/ld-plugin/pr29086.c: New file.
2022-05-04gdb: Workaround stringop-overread warning in debuginfod-support.c on s390xMark Wielaard1-0/+7
For some reason g++ 11.2.1 on s390x produces a spurious warning for stringop-overread in debuginfod_is_enabled for url_view. Add a new DIAGNOSTIC_IGNORE_STRINGOP_OVERREAD macro to suppress this warning. include/ChangeLog: * diagnostics.h (DIAGNOSTIC_IGNORE_STRINGOP_OVERREAD): New macro. gdb/ChangeLog: * debuginfod-support.c (debuginfod_is_enabled): Use DIAGNOSTIC_IGNORE_STRINGOP_OVERREAD on s390x.
2022-05-04LTO plugin: sync header file with GCCMartin Liska1-34/+34
include/ChangeLog: * plugin-api.h (enum ld_plugin_tag): Sync with GCC.
2022-05-03Add a linker warning when creating potentially dangerous executable ↵Nick Clifton1-2/+17
segments. Add tests, options to disabke and configure switches to choose defaults.
2022-04-28libctf: add a comment explaining how to use ctf_*openNick Alcock1-1/+7
Specifically, tell users what to pass to those functions that accept raw section content, since it's fairly involved and easy to get wrong. (.dynsym / .dynstr when CTF_F_DYNSTR is set, otherwise .symtab / .strtab). include/ChangeLog: * ctf-api.h (ctf_*open): Improve comment.
2022-04-22RISC-V: Add missing DECLARE_INSNs for Zicbo{m,p,z}Christoph Muellner1-0/+9
The recently added support for the Zicbo{m,p,z} extensions did not include DECLARE_INSN() declarations for the instructions. These declarations are needed by GDB's instruction detection code. This patch adds them. Signed-off-by: Christoph Muellner <cmuellner@gcc.gnu.org>
2022-04-20Stubs (added in a later patch) will generate new .loader symbols, once the ↵Cl?ment Chigot2-0/+12
allocations have been done. Thus, the .loader section cannot be layout before that. bfd/ChangeLog: * coff-rs6000.c (_bfd_xcoff_put_ldsymbol_name): Write len in ldinfo->strings instead of directly in the output_bfd. * coff64-rs6000.c (_bfd_xcoff64_put_ldsymbol_name): Likewise. * xcofflink.c (struct xcoff_link_hash_table): Remove ldrel_count field. Add ldinfo field. (xcoff_mark_symbol): Adjust to new ldinfo field. (xcoff_mark): Likewise. (bfd_xcoff_link_count_reloc): Likewise. (xcoff_build_loader_section): Split into two functions: one that build the loader section (this function) and one that only size it... (xcoff_size_loader_section): ... (this function). (bfd_xcoff_size_dynamic_sections): Adapt to new ldinfo field. Move the part where the dynamic sections are build to ... (bfd_xcoff_build_dynamic_sections): ... this function. * xcofflink.h: Add bfd_xcoff_build_dynamic_sections prototype. include/ChangeLog: * coff/xcoff.h (struct xcoff_loader_info): Add ldrel_count and libpath fields. ld/ChangeLog: * emultempl/aix.em (_after_allocation): New function.
2022-04-20Add linker warning for when it creates an executable stack.Nick Clifton1-0/+4
PR 29072
2022-04-07Recognize the NT_ARM_SYSTEM_CALL register setLuis Machado1-0/+2
Update binutils to recognize the NT_ARM_SYSTEM_CALL set that is dumped by Linux to core files.
2022-04-07Add support for COFF secidx relocationsMark Harmstone3-0/+7
bfd * coff-i386.c (in_reloc_p): Add R_SECTION. (howto_table): Add R_SECTION. (coff_pe_i386_relocation_section): Add support for R_SECTION. (coff_i386_reloc_type_lookup): Add support for BFD_RELOC_16_SECCIDX. * coff-x86_64.c (in_reloc_p): Add R_SECTION. (howto_table): Add R_SECTION. (coff_pe_amd64_relocation_section): Add support for R_SECTION. (coff_amd64_reloc_type_lookup): Add support for BFD_RELOC_16_SECCIDX. * reloc.c: Add BFD_RELOC_16_SECIDX. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas * config/tc-i386.c (pe_directive_secidx): New function. (md_pseudo_table): Add support for secidx. (x86_cons_fix_new): Likewise. (tc_gen_reloc): Likewise. * expr.c (op_rank): Add O_secidx. * expr.h (operatorT): Likewise. * symbols.c (resolve_symbol_value): Add support for O_secidx. * testsuite/gas/i386/secidx.s: New test source file. * testsuite/gas/i386/secidx.d: New test driver file. * testsuite/gas/i386/i386.exp: Run new test. include * coff/i386.h: Define R_SECTION. * coff/x86_64.h: Likewise. ld * testsuite/ld-pe/secidx1.s: New test source file. * testsuite/ld-pe/secidx2.s: New test source file. * testsuite/ld-pe/secidx.d: New test driver file. * testsuite/ld-pe/secidx_64.d: New test driver file. * testsuite/ld-pe/pe.exp: Add new tests.
2022-04-04objdump/opcodes: add syntax highlighting to disassembler outputAndrew Burgess1-5/+83
This commit adds the _option_ of having disassembler output syntax highlighted in objdump. This option is _off_ by default. The new command line options are: --disassembler-color=off # The default. --disassembler-color=color --disassembler-color=extended-color I have implemented two colour modes, using the same option names as we use of --visualize-jumps, a basic 8-color mode ("color"), and an extended 8bit color mode ("extended-color"). The syntax highlighting requires that each targets disassembler be updated; each time the disassembler produces some output we now pass through an additional parameter indicating what style should be applied to the text. As updating all target disassemblers is a large task, the old API is maintained. And so, a user of the disassembler (i.e. objdump, gdb) must provide two functions, the current non-styled print function, and a new, styled print function. I don't currently have a plan for converting every single target disassembler, my hope is that interested folk will update the disassemblers they are interested in. But it is possible some might never get updated. In this initial series I intend to convert the RISC-V disassembler completely, and also do a partial conversion of the x86 disassembler. Hopefully having the x86 disassembler at least partial converted will allow more people to try this out easily and provide feedback. In this commit I have focused on objdump. The changes to GDB at this point are the bare minimum required to get things compiling, GDB makes no use of the styling information to provide any colors, that will come later, if this commit is accepted. This first commit in the series doesn't convert any target disassemblers at all (the next two commits will update some targets), so after this commit, the only color you will see in the disassembler output, is that produced from objdump itself, e.g. from objdump_print_addr_with_sym, where we print an address and a symbol name, these are now printed with styling information, and so will have colors applied (if the option is on). Finally, my ability to pick "good" colors is ... well, terrible. I'm in no way committed to the colors I've picked here, so I encourage people to suggest new colors, or wait for this commit to land, and then patch the choice of colors. I do have an idea about using possibly an environment variable to allow the objdump colors to be customised, but I haven't done anything like that in this commit, the color choices are just fixed in the code for now. binutils/ChangeLog: * NEWS: Mention new feature. * doc/binutils.texi (objdump): Describe --disassembler-color option. * objdump.c (disassembler_color): New global. (disassembler_extended_color): Likewise. (disassembler_in_comment): Likewise. (usage): Mention --disassembler-color option. (long_options): Add --disassembler-color option. (objdump_print_value): Use fprintf_styled_func instead of fprintf_func. (objdump_print_symname): Likewise. (objdump_print_addr_with_sym): Likewise. (objdump_color_for_disassembler_style): New function. (objdump_styled_sprintf): New function. (fprintf_styled): New function. (disassemble_jumps): Use disassemble_set_printf, and reset disassembler_in_comment. (null_styled_print): New function. (disassemble_bytes): Use disassemble_set_printf, and reset disassembler_in_comment. (disassemble_data): Update init_disassemble_info call. (main): Handle --disassembler-color option. include/ChangeLog: * dis-asm.h (enum disassembler_style): New enum. (struct disassemble_info): Add fprintf_styled_func field, and created_styled_output field. (disassemble_set_printf): Declare. (init_disassemble_info): Add additional parameter. (INIT_DISASSEMBLE_INFO): Add additional parameter. opcodes/ChangeLog: * dis-init.c (init_disassemble_info): Take extra parameter, initialize the new fprintf_styled_func and created_styled_output fields. * disassembler.c (disassemble_set_printf): New function definition.
2022-04-02gdb: rename floatformats_ia64_quad to floatformats_ieee_quadTiezhu Yang1-3/+3
It is better to rename floatformats_ia64_quad to floatformats_ieee_quad to reflect the reality, and then we can clean up the related code. As Tom Tromey said [1]: These files are maintained in gcc and then imported into the binutils-gdb repository, so any changes to them will have to be proposed there first. the related changes have been merged into gcc master now [2], it is time to do it for gdb. [1] https://sourceware.org/pipermail/gdb-patches/2022-March/186569.html [2] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=b2dff6b2d9d6 Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
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