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2019-03-25AArch64: Fix disassembler bug with out-of-order sectionsTamar Christina2-0/+10
The AArch64 disassembler has an optimization that it uses to reduce the amount it has to search for mapping symbols during disassembly. This optimization assumes that sections are listed in the section header in monotonic increasing VMAs. However this is not a requirement for the ELF specification. Because of this when such "out of order" sections occur the disassembler would pick the wrong mapping symbol to disassemble the section with. This fixes it by explicitly passing along the stop offset for the current disassembly glob and when this changes compared to the previous one we've seen the optimization won't be performed. In effect this restarts the search from a well defined starting point. Usually the symbol's address. The existing stop_vma can't be used for this as it is allowed to be unset and setting this unconditionally would change the semantics of this field. binutils/ChangeLog: * objdump.c (disassemble_bytes): Pass stop_offset. * testsuite/binutils-all/aarch64/out-of-order.T: New test. * testsuite/binutils-all/aarch64/out-of-order.d: New test. * testsuite/binutils-all/aarch64/out-of-order.s: New test. include/ChangeLog: * dis-asm.h (struct disassemble_info): Add stop_offset. opcodes/ChangeLog: * aarch64-dis.c (last_stop_offset): New. (print_insn_aarch64): Use stop_offset.
2019-03-13[BFD, LD, AArch64, 3/3] Add --pac-plt to enable PLTs protected with PAC.Sudakshina Das2-0/+5
This is part of the patch series to add support for BTI and PAC in AArch64 linker. 1) This patch adds new definitions of PAC enabled PLTs and both BTI and PAC enabled PLTs. 2) It also defines the new dynamic tag DT_AARCH64_PAC_PLT for the PAC enabled PLTs. 3) This patch adds a new ld command line option: --pac-plt. In the presence of this option, the linker uses the PAC enabled PLTs and marks with DT_AARCH64_PAC_PLT. 4) In case both BTI and PAC are enabled the linker should pick PLTs enabled with both and also use dynamic tags for both. All these are made according to the new AArch64 ELF ABI https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4 *** bfd/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * elfnn-aarch64.c (PLT_PAC_ENTRY_SIZE, PLT_PAC_SMALL_ENTRY_SIZE): New. (PLT_BTI_PAC_ENTRY_SIZE, PLT_BTI_PAC_SMALL_ENTRY_SIZE): New. (setup_plt_values): Account for PAC or PAC and BTI enabled PLTs. (elfNN_aarch64_size_dynamic_sections): Add checks for PLT_BTI_PAC and PLT_PAC_PLT. (elfNN_aarch64_finish_dynamic_sections): Account for PLT_BTI_PAC. (get_plt_type): Add case for DT_AARCH64_PAC_PLT. (elfNN_aarch64_plt_sym_val): Add cases for PLT_BTI_PAC and PLT_PAC. *** binutils/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * readelf.c (get_aarch64_dynamic_type): Add case for DT_AARCH64_PAC_PLT. (dynamic_section_aarch64_val): Likewise. *** include/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * elf/aarch64.h (DT_AARCH64_PAC_PLT): New. *** ld/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * NEWS: Document --pac-plt. * emultempl/aarch64elf.em (OPTION_PAC_PLT): New. (PARSE_AND_LIST_LONGOPTS, PARSE_AND_LIST_OPTIONS): Add pac-plt. (PARSE_AND_LIST_ARGS_CASES): Handle OPTION_PAC_PLT. * testsuite/ld-aarch64/aarch64-elf.exp: Add the following tests. * testsuite/ld-aarch64/bti-pac-plt-1.d: New test. * testsuite/ld-aarch64/bti-pac-plt-2.d: New test. * testsuite/ld-aarch64/pac-plt-1.d: New test. * testsuite/ld-aarch64/pac-plt-2.d: New test. * testsuite/ld-aarch64/bti-plt-1.s: Add .ifndef directive.
2019-03-13[BFD, LD, AArch64, 2/3] Add --force-bti to enable BTI and to select BTI ↵Sudakshina Das2-0/+7
enabled PLTs This is part of the patch series to add support for BTI and PAC in AArch64 linker. 1) This patch adds a new ld command line option: --force-bti. In the presence of this option, the linker enables BTI with the GNU_PROPERTY_AARCH64_FEATURE_1_BTI feature. This gives out warning in case of missing gnu notes for BTI in inputs. 2) It also defines a new set of BTI enabled PLTs. These are used either when all the inputs are marked with GNU_PROPERTY_AARCH64_FEATURE_1_BTI or when the new --force-bti option is used. This required adding new fields in elf_aarch64_link_hash_table so that we could make the PLT related information more generic. 3) It also defines a dynamic tag DT_AARCH64_BTI_PLT. The linker uses this whenever it picks BTI enabled PLTs. All these are made according to the new AArch64 ELF ABI https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4 *** bfd/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> Szabolcs Nagy <szabolcs.nagy@arm.com> * bfd-in.h (aarch64_plt_type, aarch64_enable_bti_type): New. (aarch64_bti_pac_info): New. (bfd_elf64_aarch64_set_options): Add aarch64_bti_pac_info argument. (bfd_elf32_aarch64_set_options): Likewise. * bfd-in2.h: Regenerate * elfnn-aarch64.c (PLT_BTI_ENTRY_SIZE): New. (PLT_BTI_SMALL_ENTRY_SIZE, PLT_BTI_TLSDESC_ENTRY_SIZE): New. (elfNN_aarch64_small_plt0_bti_entry): New. (elfNN_aarch64_small_plt_bti_entry): New. (elfNN_aarch64_tlsdesc_small_plt_bti_entry): New. (elf_aarch64_obj_tdata): Add no_bti_warn and plt_type fields. (elf_aarch64_link_hash_table): Add plt0_entry, plt_entry and tlsdesc_plt_entry_size fields. (elfNN_aarch64_link_hash_table_create): Initialise the new fields. (setup_plt_values): New helper function. (bfd_elfNN_aarch64_set_options): Use new bp_info to set plt sizes and bti enable type. (elfNN_aarch64_allocate_dynrelocs): Use new size members instead of fixed macros. (elfNN_aarch64_size_dynamic_sections): Likewise and add checks. (elfNN_aarch64_create_small_pltn_entry): Use new generic pointers to plt stubs instead of fixed ones and update filling them according to the need for bti. (elfNN_aarch64_init_small_plt0_entry): Likewise. (elfNN_aarch64_finish_dynamic_sections): Likewise. (get_plt_type, elfNN_aarch64_get_synthetic_symtab): New. (elfNN_aarch64_plt_sym_val): Update size accordingly. (elfNN_aarch64_link_setup_gnu_properties): Set up plts if BTI GNU NOTE is set. (bfd_elfNN_get_synthetic_symtab): Define. (elfNN_aarch64_merge_gnu_properties): Give out warning with --force-bti and mising BTI NOTE SECTION. *** binutils/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> Szabolcs Nagy <szabolcs.nagy@arm.com> * readelf.c (get_aarch64_dynamic_type): New. (get_dynamic_type): Use above for EM_AARCH64. (dynamic_section_aarch64_val): New. (process_dynamic_section): Use above for EM_AARCH64. *** include/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> Szabolcs Nagy <szabolcs.nagy@arm.com> * elf/aarch64.h (DT_AARCH64_BTI_PLT): New. *** ld/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> Szabolcs Nagy <szabolcs.nagy@arm.com> * NEWS: Document --force-bti. * emultempl/aarch64elf.em (plt_type, bti_type, OPTION_FORCE_BTI): New. (PARSE_AND_LIST_SHORTOPTS, PARSE_AND_LIST_OPTIONS): Add force-bti. (PARSE_AND_LIST_ARGS_CASES): Handle OPTION_FORCE_BTI. * testsuite/ld-aarch64/aarch64-elf.exp: Add all the tests below. * testsuite/ld-aarch64/bti-plt-1.d: New test. * testsuite/ld-aarch64/bti-plt-1.s: New test. * testsuite/ld-aarch64/bti-plt-2.s: New test. * testsuite/ld-aarch64/bti-plt-2.d: New test. * testsuite/ld-aarch64/bti-plt-3.d: New test. * testsuite/ld-aarch64/bti-plt-4.d: New test. * testsuite/ld-aarch64/bti-plt-5.d: New test. * testsuite/ld-aarch64/bti-plt-6.d: New test. * testsuite/ld-aarch64/bti-plt-7.d: New test. * testsuite/ld-aarch64/bti-plt-so.s: New test. * testsuite/ld-aarch64/bti-plt.ld: New test.
2019-03-13[BFD, LD, AArch64, 1/3] Add support for GNU PROPERTIES in AArch64 for BTI ↵Sudakshina Das2-0/+12
and PAC This is part of the patch series to add support for BTI and PAC in AArch64 linker. This patch implements the following: 1) This extends in the gnu property support in the linker for AArch64 by defining backend hooks for elf_backend_setup_gnu_properties, elf_backend_merge_gnu_properties and elf_backend_parse_gnu_properties. 2) It defines AArch64 specific GNU property GNU_PROPERTY_AARCH64_FEATURE_1_AND and 2 bit for BTI and PAC in it. 3) It also adds support in readelf.c to read and print these new GNU properties in AArch64. All these are made according to the new AArch64 ELF ABI https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4 *** bfd/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * elf-properties.c (_bfd_elf_link_setup_gnu_properties): Exclude linker created inputs from merge. * elfnn-aarch64.c (struct elf_aarch64_obj_tdata): Add field for GNU_PROPERTY_AARCH64_FEATURE_1_AND properties. (elfNN_aarch64_link_setup_gnu_properties): New. (elfNN_aarch64_merge_gnu_properties): New. (elf_backend_setup_gnu_properties): Define for AArch64. (elf_backend_merge_gnu_properties): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_link_setup_gnu_properties): Define. (_bfd_aarch64_elf_parse_gnu_properties): Define. (_bfd_aarch64_elf_merge_gnu_properties): Define. * elfxx-aarch64.h (_bfd_aarch64_elf_link_setup_gnu_properties): Declare. (_bfd_aarch64_elf_parse_gnu_properties): Declare. (_bfd_aarch64_elf_merge_gnu_properties): Declare. (elf_backend_parse_gnu_properties): Define for AArch64. *** binutils/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * readelf.c (decode_aarch64_feature_1_and): New. (print_gnu_property_note): Add case for AArch64 gnu notes. *** include/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * elf/common.h (GNU_PROPERTY_AARCH64_FEATURE_1_AND): New. (GNU_PROPERTY_AARCH64_FEATURE_1_BTI): New. (GNU_PROPERTY_AARCH64_FEATURE_1_PAC): New. *** ld/ChangeLog *** 2019-03-13 Sudakshina Das <sudi.das@arm.com> * NEWS: Document GNU_PROPERTY_AARCH64_FEATURE_1_BTI and GNU_PROPERTY_AARCH64_FEATURE_1_PAC. * testsuite/ld-aarch64/aarch64-elf.exp: Add run commands for new tests. * testsuite/ld-aarch64/property-bti-pac1.d: New test. * testsuite/ld-aarch64/property-bti-pac1.s: New test. * testsuite/ld-aarch64/property-bti-pac2.d: New test. * testsuite/ld-aarch64/property-bti-pac2.s: New test. * testsuite/ld-aarch64/property-bti-pac3.d: New test.
2019-03-01PR24272, out-of-bounds read in pex64_xdata_print_uwd_codesAlan Modra1-21/+21
The fix here is to use an unsigned comparison for if (a->NumberOfRvaAndSizes > IMAGE_NUMBEROF_DIRECTORY_ENTRIES) include/ PR 24272 * coff/internal.h (struct internal_extra_pe_aouthdr): Change type of SizeOfCode, SizeOfInitializedData, and SizeOfUninitializedData to bfd_vma. Change type of SectionAlignment, FileAlignment, Reserved1, SizeOfImage, SizeOfHeaders, CheckSum, LoaderFlags, and NumberOfRvaAndSizes to uint32_t. bfd/ PR 24272 * peXXigen.c (_bfd_XXi_swap_aouthdr_in): Use unsigned index. (_bfd_XX_print_private_bfd_data_common): Adjust for type changes.
2019-02-20AArch64: Add pauth core file sectionAlan Hayward2-0/+6
Used for the AArch64 pointer authentication code mask registers in Arm v8.3-a. NT_ARM_PAC_MASK matches the value in Linux include/uapi/linux/elf.h include/ChangeLog: * elf/common.h (NT_ARM_PAC_MASK): Add define. bfd/ChangeLog: * elf-bfd.h (elfcore_write_aarch_pauth): Add declaration. * elf.c (elfcore_grok_aarch_pauth): New function. (elfcore_grok_note): Check for NT_ARM_PAC_MASK. (elfcore_write_aarch_pauth): New function. (elfcore_write_register_note): Check for AArch64 pauth section.
2019-02-15Use the correct name for various MACH-O based operating systems in comments.Saagar Jha2-3/+7
include * mach-o/loader.h: Use new OS names in comments.
2019-02-12Fix splay tree KEY leak detected in GDB test gdb.base/macscp.exptromey2-2/+14
When a node is removed from a splay tree, the splay tree was not using the function splay_tree_delete_key_fn to release the key. This was causing a leak, fixed by Tom Tromey. This patch fixes another key leak, that happens when a key equal to a key already present is inserted. In such a case, we have to release the old KEY. Note that this is based on the assumption that the caller always allocates a new KEY when doing an insert. Also, clarify the documentation about when the release functions are called. 2019-02-11 Philippe Waroquiers <philippe.waroquiers@skynet.be> * splay-tree.h (splay_tree_delete_key_fn): Update comment. (splay_tree_delete_value_fn): Likewise. libiberty/ChangeLog 2019-02-11 Philippe Waroquiers <philippe.waroquiers@skynet.be> * splay-tree.c (splay_tree_insert): Also release old KEY in case of insertion of a key equal to an already present key. (splay_tree_new_typed_alloc): Update comment. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@268793 138bc75d-0d04-0410-961f-82ee72b054a4
2019-01-31S/390: Implement instruction set extensionsAndreas Krebbel2-0/+6
opcodes/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * s390-mkopc.c (main): Accept arch13 as cpu string. * s390-opc.c: Add new instruction formats and instruction opcode masks. * s390-opc.txt: Add new arch13 instructions. include/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH13. gas/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * config/tc-s390.c (s390_parse_cpu): New entry for arch13. * doc/c-s390.texi: Document arch13 march option. * testsuite/gas/s390/s390.exp: Run the arch13 related tests. * testsuite/gas/s390/zarch-arch13.d: New test. * testsuite/gas/s390/zarch-arch13.s: New test. * testsuite/gas/s390/zarch-z13.d: Expect the renamed mnemonics also for z13.
2019-01-25AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging ↵Sudi Das2-2/+7
Extension. This patch is part of a series of patches to introduce a few changes to the Armv8.5-A Memory Tagging Extension. This patch removes the LDGV and STGV instructions. These instructions needed special infrastructure to support [base]! style for addressing mode. That is also removed now. Committed on behalf of Sudakshina Das. *** gas/ChangeLog *** * config/tc-aarch64.c (parse_address_main): Remove support for [base]! address expression. (parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2. (warn_unpredictable_ldst): Remove support for ldstgv_indexed. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv and stgv. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** include/ChangeLog *** * opcode/aarch64.h (enum aarch64_opnd): Remove AARCH64_OPND_ADDR_SIMPLE_2. (enum aarch64_insn_class): Remove ldstgv_indexed. *** opcodes/ChangeLog *** * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove. * aarch64-asm.h (ins_addr_simple_2): Likeiwse. * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise. * aarch64-dis.h (ext_addr_simple_2): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): Remove case for ldstgv_indexed. (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2. * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv. (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2019-01-22Include coff/sym.h from coff/ecoff.hTom Tromey2-0/+6
coff/ecoff.h refers to some names defined in coff/sym.h. Include the latter from the former, so that users of the header don't need to know this detail. 2019-01-22 Tom Tromey <tom@tromey.com> * coff/ecoff.h: Include coff/sym.h.
2019-01-19Add markers for 2.32 branch to NEWS and ChangeLog files.Nick Clifton1-0/+4
2019-01-16RISC-V: Support ELF attribute for gas and readelf.Jim Wilson2-0/+26
2019-01-16 Kito Cheng <kito@andestech.com> Nelson Chu <nelson@andestech.com> bfd/ * elfnn-riscv.c (riscv_elf_obj_attrs_arg_type): New. (elf_backend_obj_attrs_vendor): Define. (elf_backend_obj_attrs_section_type): Likewise. (elf_backend_obj_attrs_section): Likewise. (elf_backend_obj_attrs_arg_type): Define as riscv_elf_obj_attrs_arg_type. * elfxx-riscv.c (riscv_estimate_digit): New. (riscv_estimate_arch_strlen1): Likewise. (riscv_estimate_arch_strlen): Likewise. (riscv_arch_str1): Likewise. (riscv_arch_str): Likewise. * elfxx-riscv.h (riscv_arch_str): Declare. binutils/ * readelf.c (get_riscv_section_type_name): New function. (get_section_type_name): Add handler for RISC-V. (riscv_attr_tag_t): Declare. (riscv_attr_tag): New. (display_riscv_attribute): New function. (process_attributes): Add handler for RISC-V. * testsuite/binutils-all/strip-3.d: Remove .riscv.attribute section. gas/ * config/tc-riscv.c (DEFAULT_RISCV_ATTR): Define to 0 if not defined. (riscv_set_options): Add `arch_attr` field. (riscv_opts): Set default value for arch_attr. (riscv_write_out_arch_attr): New. (riscv_set_public_attributes): Likewise. (riscv_md_end): Likewise. (riscv_convert_symbolic_attribute): Likewise. (s_riscv_attribute): Likewise. (explicit_arch_attr): Likewise. (riscv_pseudo_table): Add .attribute to the table. (options): Add OPTION_ARCH_ATTR and OPTION_NO_ARCH_ATTR enumeration constants. (md_longopts): Add `march-attr' and `mno-arch-attr' options. (md_parse_option): Handle the new options. (md_show_usage): Document the `march-attr' option. * config/tc-riscv.h (md_end): Define as riscv_md_end (riscv_md_end): Declare. (CONVERT_SYMBOLIC_ATTRIBUTE): Define as riscv_convert_symbolic_attribute. (riscv_convert_symbolic_attribute): Declare. (start_assemble): Declare. * testsuite/gas/elf/elf.exp: Adjust test case for section2.e. * testsuite/gas/elf/section2.e-riscv: New. * testsuite/gas/riscv/attribute-01.d: New test * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-04.s: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-05.s: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-06.s: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * testsuite/gas/riscv/attribute-07.s: Likewise. * testsuite/gas/riscv/attribute-08.d: Likewise. * testsuite/gas/riscv/attribute-08.s: Likewise. * testsuite/gas/riscv/attribute-unknown.d: Likewise. * testsuite/gas/riscv/attribute-unknown.s: Likewise. * testsuite/gas/riscv/empty.l: Likewise. * doc/c-riscv.texi (.attribute): Add documentation. * configure.ac (--enable-default-riscv-attribute): New options. * configure: Re-generate. * config.in: Re-generate. include/ * elf/riscv.h (SHT_RISCV_ATTRIBUTES): Define. (Tag_RISCV_arch): Likewise. (Tag_RISCV_priv_spec): Likewise. (Tag_RISCV_priv_spec_minor): Likewise. (Tag_RISCV_priv_spec_revision): Likewise. (Tag_RISCV_unaligned_access): Likewise. (Tag_RISCV_stack_align): Likewise.
2019-01-14Include <string.h> to dis-asm.h to get strchr declarationПавел Крюков2-0/+5
Include <string.h> to dis-asm.h to get strchr declaration include/Changelog: 2019-01-11 Pavel I. Kryukov <kryukov@frtk.ru> * dis-asm.h: include <string.h>
2019-01-10Sync libiberty sources with gcc master versions.Nick Clifton2-33/+9
. * libiberty: Sync with gcc. Bring in: 2019-01-09 Sandra Loosemore <sandra@codesourcery.com> PR other/16615 * cp-demangle.c: Mechanically replace "can not" with "cannot". * floatformat.c: Likewise. * strerror.c: Likewise. 2018-12-22 Jason Merrill <jason@redhat.com> Remove support for demangling GCC 2.x era mangling schemes. * cplus-dem.c: Remove cplus_mangle_opname, cplus_demangle_opname, internal_cplus_demangle, and all subroutines. (libiberty_demanglers): Remove entries for ancient GNU (pre-3.0), Lucid, ARM, HP, and EDG demangling styles. (cplus_demangle): Remove 'work' variable. Don't call internal_cplus_demangle. include * Merge from GCC: 2018-12-22 Jason Merrill <jason@redhat.com> * demangle.h: Remove support for ancient GNU (pre-3.0), Lucid, ARM, HP, and EDG demangling styles.
2019-01-09Merge from gcc: use "cannot" instead of "can not" in libiberty and include.Sandra Loosemore3-3/+11
2019-01-09 Sandra Loosemore <sandra@codesourcery.com> Merge from GCC: 2019-01-09 Sandra Loosemore <sandra@codesourcery.com> PR other/16615 [2/5] include/ * libiberty.h: Mechanically replace "can not" with "cannot". * plugin-api.h: Likewise. libiberty/ * cp-demangle.c: Mechanically replace "can not" with "cannot". * floatformat.c: Likewise. * strerror.c: Likewise.
2019-01-05RX: include - Add RXv3 support.Yoshinori Sato3-1/+43
* elf/rx.h (EF_RX_CPU_MASK): Update new bits. (E_FLAG_RX_V3): New RXv3 type. * opcode/rx.h (RX_Size): Add double size. (RX_Operand_Type): Add double FPU registers. (RX_Opcode_ID): Add new instuctions.
2019-01-01Update year range in copyright notice of binutils filesAlan Modra284-283/+287
2019-01-01ChangeLog rotationAlan Modra2-878/+892
2019-01-01Update copyright year range in all GDB files.Joel Brobecker22-22/+22
This commit applies all changes made after running the gdb/copyright.py script. Note that one file was flagged by the script, due to an invalid copyright header (gdb/unittests/basic_string_view/element_access/char/empty.cc). As the file was copied from GCC's libstdc++-v3 testsuite, this commit leaves this file untouched for the time being; a patch to fix the header was sent to gcc-patches first. gdb/ChangeLog: Update copyright year range in all GDB files.
2018-12-28PR24028, PPC_INT_FMTAlan Modra2-8/+5
PPC_INT_FMT is redundant now that bfd.h pulls in inttypes.h if available. Apparently MacOS Mojave defines int64_t as long long even though long is also 64 bits, which confuses the logic selecting PPC_INT_FMT (and BFD_PRI64 too). Hopefully inttypes.h is available on Mojave. PR 24028 include/ * opcode/ppc.h (PPC_INT_FMT): Delete. opcodes/ * ppc-dis.c (print_insn_powerpc): Replace PPC_INT_FMT uses with PRId64/PRIx64.
2018-12-14elf: Add PT_GNU_PROPERTY segment typeH.J. Lu2-3/+7
Linkers group input note sections with the same name into one output note section with the same name. One output note section is placed in one PT_NOTE segment. New linkers merge all input .note.gnu.property sections into one output .note.gnu.property section with a single NT_GNU_PROPERTY_TYPE_0 note in a single PT_NOTE segment. Since older linkers treat input .note.gnu.property section as a generic note section and just concatenate all input .note.gnu.property sections into one output .note.gnu.property section without merging them, we may see one or more NT_GNU_PROPERTY_TYPE_0 notes in PT_NOTE segment, which are invalid. GNU_PROPERTY_X86_UINT32_VALID was defined to address this issue such that linker sets the bit for non-relocatable outputs. But it isn't sufficient: 1. It doesn't cover generic properties. 2. When -mx86-used-note=yes is passed to x86 assembler, the GNU_PROPERTY_X86_UINT32_VALID bit is set in GNU_PROPERTY_X86_ISA_1_USED property in object file and older linkers generate invalid NT_GNU_PROPERTY_TYPE_0 notes with the GNU_PROPERTY_X86_UINT32_VALID bit set. I am proposing the following changes: 1. Add PT_GNU_PROPERTY segment type: # define PT_GNU_PROPERTY (PT_LOOS + 0x474e553) which covers .note.gnu.property section. 2. Remove GNU_PROPERTY_X86_UINT32_VALID. bfd/ PR ld/23900 * elf.c (get_program_header_size): Add a PT_GNU_PROPERTY segment for NOTE_GNU_PROPERTY_SECTION_NAME. (_bfd_elf_map_sections_to_segments): Create a PT_GNU_PROPERTY segment for NOTE_GNU_PROPERTY_SECTION_NAME. * elfxx-x86.c (_bfd_elf_link_setup_gnu_properties): Don't set GNU_PROPERTY_X86_UINT32_VALID. binutils/ PR ld/23900 * readelf.c (get_segment_type): Support PT_GNU_PROPERTY. (decode_x86_isa): Don't check GNU_PROPERTY_X86_UINT32_VALID. (decode_x86_feature_1): Likewise. (decode_x86_feature_2): Likewise. (print_gnu_property_note): Remove GNU_PROPERTY_X86_UINT32_VALID check. * testsuite/binutils-all/i386/empty.d: Updated. * testsuite/binutils-all/x86-64/empty-x32.d: Likewise. * testsuite/binutils-all/x86-64/empty.d: Likewise. * testsuite/binutils-all/i386/pr21231b.s: Change GNU_PROPERTY_X86_ISA_1_USED bits to 0x7fffffff. * testsuite/binutils-all/x86-64/pr21231b.s: Likewise. gas/ PR ld/23900 * config/tc-i386.c (x86_cleanup): Don't set GNU_PROPERTY_X86_UINT32_VALID. * testsuite/gas/i386/property-1.s: Change GNU_PROPERTY_X86_ISA_1_USED bits to 0. include/ PR ld/23900 * elf/common.h (PT_GNU_PROPERTY): New. (GNU_PROPERTY_X86_UINT32_VALID): Removed. ld/ PR ld/23900 * testsuite/ld-elf/elf.exp: Run PR ld/23900 test. * testsuite/ld-elf/pr23900-1-32.rd: New file. * testsuite/ld-elf/pr23900-1-64.rd: Likewise. * testsuite/ld-elf/pr23900-1.d: Likewise. * testsuite/ld-elf/pr23900-1.s: Likewise. * testsuite/ld-elf/pr23900-2.s: Likewise. * testsuite/ld-elf/pr23900-2a.d: Likewise. * testsuite/ld-elf/pr23900-2b.d: Likewise. * testsuite/ld-i386/ibt-plt-1.d: Adjusted. * testsuite/ld-i386/ibt-plt-2c.d: Likewise. * testsuite/ld-i386/ibt-plt-2d.d: Likewise. * testsuite/ld-i386/ibt-plt-3d.d: Likewise. * testsuite/ld-x86-64/ibt-plt-1-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-1.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2c-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2c.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2d-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2c.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3c-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3c.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3d-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3d.d: Likewise. * testsuite/ld-i386/pr23372c.d: Expect <None> for GNU_PROPERTY_X86_ISA_1_USED. * testsuite/ld-x86-64/pr23372c-x32.d: Likewise. * testsuite/ld-x86-64/pr23372c.d: Likewise. * testsuite/ld-x86-64/pr23372d-x32.d: Likewise. * testsuite/ld-x86-64/pr23372d.d: Likewise. * testsuite/ld-x86-64/property-x86-5a.s: Change GNU_PROPERTY_X86_ISA_1_USED bits to 0. * testsuite/ld-x86-64/property-x86-5b.s: Likewise.
2018-12-11Fix a failure in the libiberty testsuite by increasing the recursion limit ↵Nick Clifton2-1/+6
to 2048. PR 88409 include * demangle.h (DEMANGLE_RECURSION_LIMIT): Increase to 2048. binutils* NEWS: Note that recursion limit has increased to 2048. * doc/binutils.texi: Likewise.
2018-12-07elf: Report property change when merging propertiesH.J. Lu2-0/+7
With merging properties, report property change in linker map file, like Merging program properties Removed property 0xc0010000 to merge /usr/lib/gcc/x86_64-redhat-linux/8/../../../../lib64/crt1.o (0x0) and /usr/lib/gcc/x86_64-redhat-linux/8/../../../../lib64/crti.o (0x0) Removed property 0xc0000002 to merge /usr/lib/gcc/x86_64-redhat-linux/8/../../../../lib64/crt1.o (0x3) and x.o (not found) Removed property 0xc0000000 to merge /usr/lib/gcc/x86_64-redhat-linux/8/../../../../lib64/crt1.o (not found) and /usr/lib64/libc_nonshared.a(elf-init.oS) (0x0) Removed property 0xc0000001 to merge /usr/lib/gcc/x86_64-redhat-linux/8/../../../../lib64/crt1.o (not found) and /usr/lib64/libc_nonshared.a(elf-init.oS) (0x0) bfd/ * elf-properties.c (elf_find_and_remove_property): Add a bfd_boolean argument to indicate if the property should be removed. (elf_merge_gnu_property_list): Updated. Report property change in linker map file. (elf_get_gnu_property_section_size): Skip property_remove properties. (elf_write_gnu_properties): Likewise. (_bfd_elf_link_setup_gnu_properties): Report property merge in linker map file. Pass abfd to elf_merge_gnu_property_list. include/ * bfdlink.h (bfd_link_info): Add has_map_file. ld/ * NEWS: Updated for property change report. * ld.texi: Document property change report. * ldmain.c (main): Set link_info.has_map_file to TRUE when linker map file is used. * testsuite/ld-scripts/rgn-over1.d: Updated. * testsuite/ld-scripts/rgn-over2.d: Likewise. * testsuite/ld-scripts/rgn-over3.d: Likewise. * testsuite/ld-scripts/rgn-over4.d: Likewise. * testsuite/ld-scripts/rgn-over5.d: Likewise. * testsuite/ld-scripts/rgn-over6.d: Likewise. * testsuite/ld-scripts/rgn-over7.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1a-x32.d: Check linker map file. * testsuite/ld-x86-64/property-x86-ibt1a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1a.map: New file.
2018-12-07Synchronize libiberty with gcc and add --no-recruse-limit option to tools ↵Nick Clifton2-0/+19
that support name demangling. This patch addresses the multitude of bug reports about resource exhaustion in libiberty's name demangling code. It adds a limit to the amount of recursion that is allowed, before an error is triggered. It also adds a new demangling option to disable this limit. (The limit is enabled by default). PR 87681 PR 87675 PR 87636 PR 87335 libiberty * cp-demangle.h (struct d_info): Add recursion_limit field. * cp-demangle.c (d_function_type): If the recursion limit is enabled and reached, return with a failure result. (d_demangle_callback): If the recursion limit is enabled, check for a mangled string that is so long that there is not enough stack space for the local arrays. * cplus-dem.c (struct work): Add recursion_level field. (demangle_nested_args): If the recursion limit is enabled and reached, return with a failure result. include * demangle.h (DMGL_RECURSE_LIMIT): Define. (DEMANGLE_RECURSION_LIMIT): Prototype. binutuils * addr2line.c (demangle_flags): New static variable. (long_options): Add --recurse-limit and --no-recurse-limit. (translate_address): Pass demangle_flags to bfd_demangle. (main): Handle --recurse-limit and --no-recurse-limit options. * cxxfilt.c (flags): Add DMGL_RECURSE_LIMIT. (long_options): Add --recurse-limit and --no-recurse-limit. (main): Handle new options. * dlltool.c (gen_def_file): Include DMGL_RECURSE_LIMIT in flags passed to cplus_demangle. * nm.c (demangle_flags): New static variable. (long_options): Add --recurse-limit and --no-recurse-limit. (main): Handle new options. * objdump.c (demangle_flags): New static variable. (usage): Add --recurse-limit and --no-recurse-limit. (long_options): Likewise. (objdump_print_symname): Pass demangle_flags to bfd_demangle. (disassemble_section): Likewise. (dump_dymbols): Likewise. (main): Handle new options. * prdbg.c (demangle_flags): New static variable. (tg_variable): Pass demangle_flags to demangler. (tg_start_function): Likewise. * stabs.c (demangle_flags): New static variable. (stab_demangle_template): Pass demangle_flags to demangler. (stab_demangle_v3_argtypes): Likewise. (stab_demangle_v3_arg): Likewise. * doc/binutuls.texi: Document new command line options. * NEWS: Mention the new feature. * testsuite/config/default.exp (CXXFILT): Define if not already defined. (CXXFILTFLAGS): Likewise. * testsuite/binutils-all/cxxfilt.exp: New file. Runs a few simple tests of the cxxfilt program.
2018-12-06PowerPC @l, @h and @ha warnings, plus VLE e_liAlan Modra2-0/+9
This patch started off just adding the warnings in tc-ppc.c about incorrect usage of @l, @h and @ha in instructions that don't have 16-bit D-form fields. That unfortunately showed up three warnings in ld/testsuite/ld-powerpc/vle-multiseg.s on instructions like e_li r3, IV_table@l+0x00 which was being assembled to 8: 70 60 00 00 e_li r3,0 a: R_PPC_ADDR16_LO IV_table The ADDR16_LO reloc is of course completely bogus on e_li, which has a split 20-bit signed integer field in bits 0x1f7fff, the low 11 bit in 0x7ff, the next 5 bits in 0x1f0000, and the high 4 bits in 0x7800. Applying an ADDR16_LO reloc to the instruction potentially changes the e_li instruction to e_add2i., e_add2is, e_cmp16i, e_mull2i, e_cmpl16i, e_cmph16i, e_cmphl16i, e_or2i, e_and2i., e_or2is, e_lis, e_and2is, or some invalid encodings. Now there is a relocation that suits e_li, R_PPC_VLE_ADDR20, which was added 2017-09-05 but I can't see code in gas to generate the relocation. In any case, VLE_ADDR20 probably doesn't have the correct semantics for @l since ideally you'd want an @l to pair with @h or @ha to generate a 32-bit constant. Thus @l should only produce a 16-bit value, I think. So we need some more relocations to handle e_li it seems, or as I do in this patch, modify the behaviour of existing relocations when applied to e_li instructions. include/ * opcode/ppc.h (E_OPCODE_MASK, E_LI_MASK, E_LI_INSN): Define. bfd/ * elf32-ppc.c (ppc_elf_howto_raw <R_PPC_VLE_ADDR20>): Correct mask and shift value. (ppc_elf_vle_split16): Use E_OPCODE_MASK. Handle e_li specially. gas/ * config/tc-ppc.c (md_assemble): Adjust relocs for VLE before TLS tweaks. Handle e_li. Warn on unexpected operand field for lo16/hi16/ha16 relocs.
2018-12-06opcodes/riscv: Hide '.L0 ' fake symbolsAndrew Burgess3-0/+13
The RISC-V assembler generates fake labels with the name '.L0 ' as part of the debug information (see gas/config/tc-riscv.h:FAKE_LABEL_NAME). The problem is that currently, when disassembling an object file, the output looks like this (this is an example from the GDB testsuite, but is pretty representative of anything with debug information): 000000000000001e <main>: 1e: 7179 addi sp,sp,-48 20: f406 sd ra,40(sp) 22: f022 sd s0,32(sp) 24: 1800 addi s0,sp,48 0000000000000026 <.L0 >: 26: 87aa mv a5,a0 28: feb43023 sd a1,-32(s0) 2c: fcc43c23 sd a2,-40(s0) 30: fef42623 sw a5,-20(s0) 0000000000000034 <.L0 >: 34: fec42783 lw a5,-20(s0) 38: 0007871b sext.w a4,a5 3c: 678d lui a5,0x3 3e: 03978793 addi a5,a5,57 # 3039 <.LASF30+0x2a9d> 42: 02f71463 bne a4,a5,6a <.L0 > 0000000000000046 <.L0 >: 46: 000007b7 lui a5,0x0 4a: 0007b783 ld a5,0(a5) # 0 <need_malloc> 4e: 6f9c ld a5,24(a5) 0000000000000050 <.L0 >: 50: 86be mv a3,a5 52: 466d li a2,27 54: 4585 li a1,1 56: 000007b7 lui a5,0x0 5a: 00078513 mv a0,a5 5e: 00000097 auipc ra,0x0 62: 000080e7 jalr ra # 5e <.L0 +0xe> 0000000000000066 <.L0 >: 66: 4785 li a5,1 68: a869 j 102 <.L0 > 000000000000006a <.L0 >: 6a: 000007b7 lui a5,0x0 6e: 00078513 mv a0,a5 72: 00000097 auipc ra,0x0 76: 000080e7 jalr ra # 72 <.L0 +0x8> The frequent repeated '.L0 ' labels are pointless, as they are non-unique there's no way to match a use of '.L0 ' to its appearence in the output, so we'd be better off just not printing it at all. That's what this patch does by defining a 'symbol_is_valid' method for RISC-V. With this commit, the same disassembly now looks like this: 000000000000001e <main>: 1e: 7179 addi sp,sp,-48 20: f406 sd ra,40(sp) 22: f022 sd s0,32(sp) 24: 1800 addi s0,sp,48 26: 87aa mv a5,a0 28: feb43023 sd a1,-32(s0) 2c: fcc43c23 sd a2,-40(s0) 30: fef42623 sw a5,-20(s0) 34: fec42783 lw a5,-20(s0) 38: 0007871b sext.w a4,a5 3c: 678d lui a5,0x3 3e: 03978793 addi a5,a5,57 # 3039 <.LASF30+0x2a9d> 42: 02f71463 bne a4,a5,6a <.L4> 46: 000007b7 lui a5,0x0 4a: 0007b783 ld a5,0(a5) # 0 <need_malloc> 4e: 6f9c ld a5,24(a5) 50: 86be mv a3,a5 52: 466d li a2,27 54: 4585 li a1,1 56: 000007b7 lui a5,0x0 5a: 00078513 mv a0,a5 5e: 00000097 auipc ra,0x0 62: 000080e7 jalr ra # 5e <main+0x40> 66: 4785 li a5,1 68: a869 j 102 <.L5> 000000000000006a <.L4>: 6a: 000007b7 lui a5,0x0 6e: 00078513 mv a0,a5 72: 00000097 auipc ra,0x0 76: 000080e7 jalr ra # 72 <.L4+0x8> In order to share the fake label between the assembler and the libopcodes library, I've added some new defines RISCV_FAKE_LABEL_NAME and RISCV_FAKE_LABEL_CHAR in include/opcode/riscv.h. I could have just moved FAKE_LABEL_NAME to the include file, however, I thnk this would be confusing, someone working on the assembler would likely not expect to find FAKE_LABEL_NAME defined outside of the assembler source tree. By introducing the RISCV_FAKE_LABEL_* defines I can leave the assembler standard FAKE_LABEL_ defines in the assembler source, but still share the RISCV_FAKE_LABEL_* with libopcodes. gas/ChangeLog: * config/tc-riscv.h (FAKE_LABEL_NAME): Define as RISCV_FAKE_LABEL_NAME. (FAKE_LABEL_CHAR): Define as RISCV_FAKE_LABEL_CHAR. include/ChangeLog: * dis-asm.h (riscv_symbol_is_valid): Declare. * opcode/riscv.h (RISCV_FAKE_LABEL_NAME): Define. (RISCV_FAKE_LABEL_CHAR): Define. opcodes/ChangeLog: * disassembler.c (disassemble_init_for_target): Add RISC-V initialisation. * riscv-dis.c (riscv_symbol_is_valid): New function.
2018-12-03RISC-V: Accept version, supervisor ext and more than one NSE for -march.Jim Wilson2-1/+6
This patch moves all -march parsing logic into bfd, because we will use this code in ELF attributes. bfd/ * elfxx-riscv.h (RISCV_DONT_CARE_VERSION): New macro. (struct riscv_subset_t): New structure. (riscv_subset_t): New typedef. (riscv_subset_list_t): New structure. (riscv_release_subset_list): New prototype. (riscv_add_subset): Likewise. (riscv_lookup_subset): Likewise. (riscv_lookup_subset_version): Likewise. (riscv_release_subset_list): Likewise. * elfxx-riscv.c: Include safe-ctype.h. (riscv_parsing_subset_version): New function. (riscv_supported_std_ext): Likewise. (riscv_parse_std_ext): Likewise. (riscv_parse_sv_or_non_std_ext): Likewise. (riscv_parse_subset): Likewise. (riscv_add_subset): Likewise. (riscv_lookup_subset): Likewise. (riscv_lookup_subset_version): Likewise. (riscv_release_subset_list): Likewise. gas/ * config/tc-riscv.c: Include elfxx-riscv.h. (struct riscv_subset): Removed. (riscv_subsets): Change type to riscv_subset_list_t. (riscv_subset_supports): Removed argument: xlen_required and move logic into libbfd. (riscv_multi_subset_supports): Removed argument: xlen_required. (riscv_clear_subsets): Removed. (riscv_add_subset): Ditto. (riscv_set_arch): Extract parsing logic into libbfd. (riscv_ip): Update argument for riscv_multi_subset_supports and riscv_subset_supports. Update riscv_subsets due to struct definition changed. (riscv_after_parse_args): Update riscv_subsets due to struct definition changed, update and argument for riscv_subset_supports. * testsuite/gas/riscv/empty.s: New. * testsuite/gas/riscv/march-fail-rv32ef.d: Likewise. * testsuite/gas/riscv/march-fail-rv32ef.l: Likewise. * testsuite/gas/riscv/march-fail-rv32i.d: Likewise. * testsuite/gas/riscv/march-fail-rv32i.l: Likewise. * testsuite/gas/riscv/march-fail-rv32iam.d: Likewise. * testsuite/gas/riscv/march-fail-rv32iam.l: Likewise. * testsuite/gas/riscv/march-fail-rv32ic.d: Likewise. * testsuite/gas/riscv/march-fail-rv32ic.l: Likewise. * testsuite/gas/riscv/march-fail-rv32icx2p.d: Likewise. * testsuite/gas/riscv/march-fail-rv32icx2p.l: Likewise. * testsuite/gas/riscv/march-fail-rv32imc.d: Likewise. * testsuite/gas/riscv/march-fail-rv32imc.l: Likewise. * testsuite/gas/riscv/march-fail-rv64I.d: Likewise. * testsuite/gas/riscv/march-fail-rv64I.l: Likewise. * testsuite/gas/riscv/march-fail-rv64e.d: Likewise. * testsuite/gas/riscv/march-fail-rv64e.l: Likewise. * testsuite/gas/riscv/march-ok-g2.d: Likewise. * testsuite/gas/riscv/march-ok-g2p0.d: Likewise. * testsuite/gas/riscv/march-ok-i2p0.d: Likewise. * testsuite/gas/riscv/march-ok-nse-with-version.: Likewise.d * testsuite/gas/riscv/march-ok-s-with-version.d: Likewise. * testsuite/gas/riscv/march-ok-s.d: Likewise. * testsuite/gas/riscv/march-ok-sx.d: Likewise. * testsuite/gas/riscv/march-ok-two-nse.d: Likewise. * testsuite/gas/riscv/march-ok-g2_p1.d: Likewise. * testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise. include/ * opcode/riscv.h (riscv_opcode): Change type of xlen_requirement to unsigned. opcodes/ * riscv-opc.c: Change the type of xlen, because type of xlen_requirement changed.
2018-11-27RISC-V: Add .insn CA support.Jim Wilson2-0/+9
gas/ * config/tc-riscv.c (validate_riscv_insn) <'F'>: Add support for CF6 and CF2 operands. (riscv_ip) <'F'>: Likewise. * doc/c-riscv.texi (RISC-V-Formats): Add func6 abbreviation. Use rs2 instead of rs1 in CR description. Add CA docs. * gas/testsuite/riscv/insn.s: Add use of .insn ca. * gas/testsuite/riscv/insn.d: Update to match. include/ * opcode/riscv.h (OP_MASK_CFUNCT6, OP_SH_CFUNCT6): New. (OP_MASK_CFUNCT2, OP_SH_CFUNCT2): New. opcodes/ * riscv-opc.c (ciw): Fix whitespace to align columns. (ca): New.
2018-11-13[ARM] Improve indentation of ARM architecture declarationsThomas Preud'homme2-254/+340
This commit cleans up indentation of ARM architecture declaration, namely entries of arm_archs and definition of macros ARM_EXT_*, ARM_AEXT_*, ARM_AEXT2_*, FPU_EXT_*, FPU_ARCH_* and ARM_ARCH_*. It also gets rid of unused ARM_ARCH_V6M-ONLY and merge AEM_AEXT_V6M_ONLY in ARM_AEXT_V6M now sole user. gas/ 2018-11-13 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (arm_archs): Reindent. include/ 2018-11-13 Thomas Preud'homme <thomas.preudhomme@arm.com> * opcode/arm.h (ARM_AEXT_V6M_ONLY): Merge into its use in ARM_AEXT_V6M. (ARM_ARCH_V6M_ONLY): Remove. (ARM_EXT_V1, ARM_EXT_V2, ARM_EXT_V2S, ARM_EXT_V3, ARM_EXT_V3M, ARM_EXT_V4, ARM_EXT_V4T, ARM_EXT_V5, ARM_EXT_V5T, ARM_EXT_V5ExP, ARM_EXT_V5E, ARM_EXT_V5J, ARM_EXT_V6, ARM_EXT_V6K, ARM_EXT_V8, ARM_EXT_V6T2, ARM_EXT_DIV, ARM_EXT_V5E_NOTM, ARM_EXT_V6_NOTM, ARM_EXT_V7, ARM_EXT_V7A, ARM_EXT_V7R, ARM_EXT_V7M, ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR, ARM_EXT_V6_DSP, ARM_EXT_MP, ARM_EXT_SEC, ARM_EXT_OS, ARM_EXT_ADIV, ARM_EXT_VIRT, ARM_EXT2_PAN, ARM_EXT2_V8_2A, ARM_EXT2_V8M, ARM_EXT2_ATOMICS, ARM_EXT2_V6T2_V8M, ARM_EXT2_FP16_INST, ARM_EXT2_V8M_MAIN, ARM_EXT2_RAS, ARM_EXT2_V8_3A, ARM_EXT2_V8A, ARM_EXT2_V8_4A, ARM_EXT2_FP16_FML, ARM_EXT2_V8_5A, ARM_EXT2_SB, ARM_EXT2_PREDRES, ARM_CEXT_XSCALE, ARM_CEXT_MAVERICK, ARM_CEXT_IWMMXT, ARM_CEXT_IWMMXT2, FPU_ENDIAN_PURE, FPU_ENDIAN_BIG, FPU_FPA_EXT_V1, FPU_FPA_EXT_V2, FPU_MAVERICK, FPU_VFP_EXT_V1xD, FPU_VFP_EXT_V1, FPU_VFP_EXT_V2, FPU_VFP_EXT_V3xD, FPU_VFP_EXT_V3, FPU_NEON_EXT_V1, FPU_VFP_EXT_D32, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA, FPU_VFP_EXT_FMA, FPU_VFP_EXT_ARMV8, FPU_NEON_EXT_ARMV8, FPU_CRYPTO_EXT_ARMV8, CRC_EXT_ARMV8, FPU_VFP_EXT_ARMV8xD, FPU_NEON_EXT_RDMA, FPU_NEON_EXT_DOTPROD, ARM_AEXT_V1, ARM_AEXT_V2, ARM_AEXT_V2S, ARM_AEXT_V3, ARM_AEXT_V3M, ARM_AEXT_V4xM, ARM_AEXT_V4, ARM_AEXT_V4TxM, ARM_AEXT_V4T, ARM_AEXT_V5xM, ARM_AEXT_V5, ARM_AEXT_V5TxM, ARM_AEXT_V5T, ARM_AEXT_V5TExP, ARM_AEXT_V5TE, ARM_AEXT_V5TEJ, ARM_AEXT_V6, ARM_AEXT_V6K, ARM_AEXT_V6Z, ARM_AEXT_V6KZ, ARM_AEXT_V6T2, ARM_AEXT_V6KT2, ARM_AEXT_V6ZT2, ARM_AEXT_V6KZT2, ARM_AEXT_V7_ARM, ARM_AEXT_V7A, ARM_AEXT_V7VE, ARM_AEXT_V7R, ARM_AEXT_NOTM, ARM_AEXT_V6M_ONLY, ARM_AEXT_V6M, ARM_AEXT_V6SM, ARM_AEXT_V7M, ARM_AEXT_V7, ARM_AEXT_V7EM, ARM_AEXT_V8A, ARM_AEXT2_V8A, ARM_AEXT2_V8_1A, ARM_AEXT2_V8_2A, ARM_AEXT2_V8_3A, ARM_AEXT2_V8_4A, ARM_AEXT2_V8_5A, ARM_AEXT_V8M_BASE, ARM_AEXT_V8M_MAIN, ARM_AEXT_V8M_MAIN_DSP, ARM_AEXT2_V8M, ARM_AEXT2_V8M_BASE, ARM_AEXT2_V8M_MAIN, ARM_AEXT2_V8M_MAIN_DSP, ARM_AEXT_V8R, ARM_AEXT2_V8R, FPU_VFP_V1xD, FPU_VFP_V1, FPU_VFP_V2, FPU_VFP_V3D16, FPU_VFP_V3, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4, FPU_VFP_V4_SP_D16, FPU_VFP_V5D16, FPU_VFP_ARMV8, FPU_NEON_ARMV8, FPU_CRYPTO_ARMV8, FPU_VFP_HARD, FPU_FPA, FPU_ARCH_VFP, FPU_ARCH_FPE, FPU_ARCH_FPA, FPU_ARCH_VFP_V1xD, FPU_ARCH_VFP_V1, FPU_ARCH_VFP_V2, FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_NEON_V1, FPU_ARCH_VFP_V3_PLUS_NEON_V1, FPU_ARCH_NEON_FP16, FPU_ARCH_VFP_HARD, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16, FPU_ARCH_VFP_V4_SP_D16, FPU_ARCH_VFP_V5D16, FPU_ARCH_VFP_V5_SP_D16, FPU_ARCH_NEON_VFP_V4, FPU_ARCH_VFP_ARMV8, FPU_ARCH_NEON_VFP_ARMV8, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD, ARCH_CRC_ARMV8, FPU_ARCH_NEON_VFP_ARMV8_1, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1, FPU_ARCH_DOTPROD_NEON_VFP_ARMV8, ARM_ARCH_V1, ARM_ARCH_V2, ARM_ARCH_V2S, ARM_ARCH_V3, ARM_ARCH_V3M, ARM_ARCH_V4xM, ARM_ARCH_V4, ARM_ARCH_V4TxM, ARM_ARCH_V4T, ARM_ARCH_V5xM, ARM_ARCH_V5, ARM_ARCH_V5TxM, ARM_ARCH_V5T, ARM_ARCH_V5TExP, ARM_ARCH_V5TE, ARM_ARCH_V5TEJ, ARM_ARCH_V6, ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6KZ, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, ARM_ARCH_V6KZT2, ARM_ARCH_V6M, ARM_ARCH_V6SM, ARM_ARCH_V7, ARM_ARCH_V7A, ARM_ARCH_V7VE, ARM_ARCH_V7R, ARM_ARCH_V7M, ARM_ARCH_V7EM, ARM_ARCH_V8A, ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A, ARM_ARCH_V8_3A, ARM_ARCH_V8_4A, ARM_ARCH_V8_5A, ARM_ARCH_V8M_BASE, ARM_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN_DSP, ARM_ARCH_V8R): Reindent.
2018-11-12[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das2-0/+7
This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Bulk Allocation Tag instructions from MTE. These are the following instructions added in this patch: - LDGV <Xt>, [<Xn|SP>]! - STGV <Xt>, [<Xn|SP>]! This needed a new kind of operand for the new addressing [<Xn|SP>]! since this has no offset and only takes a pre-indexed version. Hence AARCH64_OPND_ADDR_SIMPLE_2 and ldtdgv_indexed are introduced. (AARCH64_OPND_ADDR_SIMPLE fulfilled the no offset criteria but does not allow writeback). We also needed new encoding and decoding functions to be able to do the same. where <Xt> : Is the 64-bit destination GPR. <Xn|SP> : Is the 64-bit first source GPR or Stack pointer. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2. (aarch64_insn_class): Add ldstgv_indexed. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-asm.c (aarch64_ins_addr_simple_2): New. * aarch64-asm.h (ins_addr_simple_2): Declare the above. * aarch64-dis.c (aarch64_ext_addr_simple_2): New. * aarch64-dis.h (ext_addr_simple_2): Declare the above. * aarch64-opc.c (operand_general_constraint_met_p): Add case for AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed. (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2. * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv. (AARCH64_OPERANDS): Define ADDR_SIMPLE_2. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add switch case for AARCH64_OPND_ADDR_SIMPLE_2 and allow [base]! for it. (warn_unpredictable_ldst): Exempt ldstgv_indexed for ldgv. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldgv and stgv. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
2018-11-12[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging ↵Sudakshina Das2-0/+14
Extension This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Tag setting instructions from MTE which consists of the following instructions: - STG [<Xn|SP>, #<simm>] - STG [<Xn|SP>, #<simm>]! - STG [<Xn|SP>], #<simm> - STZG [<Xn|SP>, #<simm>] - STZG [<Xn|SP>, #<simm>]! - STZG [<Xn|SP>], #<simm> - ST2G [<Xn|SP>, #<simm>] - ST2G [<Xn|SP>, #<simm>]! - ST2G [<Xn|SP>], #<simm> - STZ2G [<Xn|SP>, #<simm>] - STZ2G [<Xn|SP>, #<simm>]! - STZ2G [<Xn|SP>], #<simm> - STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>] - STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]! - STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm> where <Xn|SP> : Is the 64-bit GPR or Stack pointer. <simm> : Is the optional signed immediate offset, a multiple of 16 in the range -4096 to 4080, defaulting to 0. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. (aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data for AARCH64_OPND_QLF_imm_tag. (operand_general_constraint_met_p): Add case for AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. (aarch64_print_operand): Likewise. * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New. (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp for both offset and pre/post indexed versions. (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add switch case for AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. (fix_insn): Likewise. (warn_unpredictable_ldst): Exempt STGP. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g, stzg, stz2g and stgp. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
2018-11-12[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging ↵Sudakshina Das2-0/+7
Extension This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Tag generation instructions from MTE. These are the following instructions added in this patch: - IRG <Xd|SP>, <Xn|SP>{, Xm} - ADDG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2> - SUBG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2> - GMI <Xd>, <Xn|SP>, <Xm> where <Xd|SP> : Is the 64-bit destination GPR or Stack pointer. <Xn|SP> : Is the 64-bit source GPR or Stack pointer. <uimm6> : Is the unsigned immediate, a multiple of 16 in the range 0 to 1008. <uimm4> : Is the unsigned immediate, in the range 0 to 15. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3. (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New. * aarch64-opc.c (fields): Add entry for imm4_3. (operand_general_constraint_met_p): Add cases for AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10. (aarch64_print_operand): Likewise. * aarch64-tbl.h (QL_ADDG): New. (aarch64_opcode_table): Add addg, subg, irg and gmi. (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10. * aarch64-asm.c (aarch64_ins_imm): Add case for operand_need_shift_by_four. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add switch case for AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10. * testsuite/gas/aarch64/armv8_5-a-memtag.s: New. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.d: Likewise.
2018-11-12[BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-ASudakshina Das2-0/+6
This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions. Memory Tagging Extension is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch adds the new command line option and the new feature macros. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_MEMTAG): New. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-tbl.h (aarch64_feature_memtag): New. (MEMTAG, MEMTAG_INSN): New. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (aarch64_features): Add "memtag" as a new option. * doc/c-aarch64.texi: Document the same.
2018-11-07Add support for new load commands added by Apple to the MACH-O file format.Roman Bolshakov3-28/+55
bfd * mach-o.h: Add new enums for BFD_MACH_O_PLATFORM_MACOS, BFD_MACH_O_PLATFORM_IOS, BFD_MACH_O_PLATFORM_TVOS, BFD_MACH_O_PLATFORM_WATCHOS, BFD_MACH_O_PLATFORM_BRIDGEOS, BFD_MACH_O_TOOL_CLANG, BFD_MACH_O_TOOL_SWIFT, BFD_MACH_O_TOOL_LD. (struct bfd_mach_o_note_command): New. (struct bfd_mach_o_build_version_tool): New. (struct bfd_mach_o_build_version_command): New. (bfd_mach_o_read_version_min): Don't split version into a few fields. Rename reserved to sdk. * mach-o.c (bfd_mach_o_read_version_min): Don't split version into a few fields. Rename reserved to sdk. (bfd_mach_o_read_command): Handle LC_VERSION_MIN_TVOS, LC_NOTE, LC_BUILD_VERSION. (bfd_mach_o_read_note): New. (bfd_mach_o_read_build_version): New. PR 23728 binutils* od-macho.c (printf_version): New. (dump_load_command): Use it to print version. Print sdk version. Print version info for watchOS and tvOS. Print LC_NOTE, LC_BUILD_VERSION. (dump_buld_version): New. (bfd_mach_o_platform_name): New (bfd_mach_o_tool_name): New * mach-o/external.h (mach_o_nversion_min_command_external): Rename reserved to sdk. (mach_o_note_command_external): New. (mach_o_build_version_command_external): New. * mach-o/loader.h (BFD_MACH_O_LC_VERSION_MIN_TVOS): Define. (BFD_MACH_O_LC_NOTE): Define.
2018-11-06Add support for a couple of new Mach-O commands.Nick Clifton2-1/+7
PR 23742 * mach-o.c (bfd_mach_o_read_command): Accept and ignore BFD_MACH_O_LC_LINKER_OPTIONS and BFD_MACH_O_LC_BUILD_VERSION commands. * mach-o/loader.h: Add BFD_MACH_O_LC_BUILD_VERSION.
2018-11-06[BINUTILS, ARM] Add Armv8.5-A to select_arm_features and update macros.Sudakshina Das2-4/+9
This patch addresses the following 1) Adding ARMv8.5-A in select_arm_features. 2) Updating the feature macro so that the new ARM_EXT2_* features for Armv8.5-A are moved to ARM_AEXT2_V8_5A. *** opcodes/ChangeLog *** 2018-11-06 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (select_arm_features): Update bfd_mach_arm_8 with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML. *** include/ChangeLog *** 2018-11-06 Sudakshina Das <sudi.das@arm.com> * opcode/arm.h (ARM_ARCH_V8_5A): Move ARM_EXT2_PREDRES and ARM_EXT2_SB to ... (ARM_AEXT2_V8_5A): Here.
2018-10-26Support AT_HWCAP2 on FreeBSD.John Baldwin2-0/+5
include/ChangeLog: * elf/common.h (AT_FREEBSD_HWCAP2): Define. gdb/ChangeLog: * fbsd-tdep.c (fbsd_print_auxv_entry): Handle AT_FREEBSD_HWCAP2.
2018-10-23S12Z: New 32 bit Reloc.John Darrington1-1/+2
Third party tools produce 32 bit relocs at index 6 with strange properties. This change moves the existing 32 bit reloc (R_S12Z_EXT32) to index 7 and introduces a new one (R_S12Z_CW32) at index 6 to try to support code generated by these tools. * bfd/elf32-s12z.c (elf_s12z_howto_table) [R_S12Z_CW32]: New member. * binutils/readelf.c (is_32bit_abs_reloc): Reloc type 7 is also 32 bit. * include/elf/s12z.h (elf_s12z_reloc_tpe) [RELOC_NUMBER (R_S12Z_CW32)]: New enum.
2018-10-09[PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRSSudakshina Das2-1/+9
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) The encodings can be found in the System Register XML. This patch adds support for the mitigation for Spectre Variant 4 by adding the PSTATE bit SSBS which are accessible using MSR and MRS instructions. Although this is a mandatory addition to the ARMv8.5-A, it is permitted to be added to any version of the ARMv8 architecture. This is enabled using the command line option of +ssbs for older versions. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_SSBS): New. (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SSBS by default. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (operand_general_constraint_met_p): Add SSBS in the check for one-bit immediate. (aarch64_sys_regs): New entry for SSBS. (aarch64_sys_reg_supported_p): New check for above. (aarch64_pstatefields): New entry for SSBS. (aarch64_pstatefield_supported_p): New check for above. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (aarch64_features): Add new "ssbs". * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/ssbs-illegal1.d: New test. * testsuite/gas/aarch64/ssbs-illegal1.l: New test. * testsuite/gas/aarch64/ssbs-illegal2.d: New test. * testsuite/gas/aarch64/ssbs-illegal2.l: New test. * testsuite/gas/aarch64/ssbs.s: New test. * testsuite/gas/aarch64/ssbs1.d: Test with +ssbs * testsuite/gas/aarch64/ssbs2.d: Test with armv8.5-a.
2018-10-09[PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registersSudakshina Das2-1/+14
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) The encodings can be found in the System Register XML. This patch adds the new system registers SCXTNUM_ELx and ID_PFR2_EL1. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New. (AARCH64_FEATURE_ID_PFR2): New. (AARCH64_ARCH_V8_5): Add both by default. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_sys_regs): New entries for scxtnum_el[0,1,2,3,12] and id_pfr2_el1. (aarch64_sys_reg_supported_p): New checks for above. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/sysreg-4.s: Test registers scxtnum_el[0,1,2,3,12] and id_pfr2_el1. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
2018-10-09[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instructionSudakshina Das2-1/+21
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/bti-branch-target-identification) The Branch Target Identification instructions (BTI) are allocated to existing HINT space, using HINT numbers 32, 34, 36, 38, such that bits[7:6] of the instruction identify the compatibility of the BTI instruction to different branches. BTI {<targets>} where <targets> one of the following, specifying which type of indirection is allowed: j : Can be a target of any BR Xn isntruction. c : Can be a target of any BLR Xn and BR {X16|X17}. jc: Can be a target of any free branch. A BTI instruction without any <targets> is the strictest of all and can not be a target of nay free branch. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_BTI): New. (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default. (aarch64_opnd): Add AARCH64_OPND_BTI_TARGET. (HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to define HINT #imm values. (HINT_OPD_JC, HINT_OPD_NULL): Likewise. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New. (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag with the hint immediate. * aarch64-opc.c (aarch64_hint_options): New entries for c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI. (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET while checking for HINT_OPD_F_NOPRINT flag. * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to extract value. * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New. (aarch64_opcode_table): Add entry for BTI. (AARCH64_OPERANDS): Add new description for BTI targets. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_bti_operand): New. (process_omitted_operand): Add case for AARCH64_OPND_BTI_TARGET. (parse_operands): Likewise. * testsuite/gas/aarch64/system.d: Update for BTI. * testsuite/gas/aarch64/bti.s: New. * testsuite/gas/aarch64/bti.d: New. * testsuite/gas/aarch64/illegal-bti.d: New. * testsuite/gas/aarch64/illegal-bti.l: New.
2018-10-09[PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructionsSudakshina Das2-0/+6
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) The encodings can be found in the System Register XML. This patch adds the following: MSR Xn, RNDR MSR Xn, RNDRRS These are optional instructions in ARMv8.5-A and hence the new +rng is added. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_RNG): New. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_sys_regs): New entries for rndr and rndrrs. (aarch64_sys_reg_supported_p): New check for above. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (aarch64_features): New "rng" option. * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/sysreg-4.s: Test both instructions. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
2018-10-09[PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instructionSudakshina Das2-1/+8
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/dc-data-cache-operation-an-alias-of-sys) This patch adds the DC CVADP instruction. Since this has a separate identification mechanism a new feature bit is added. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_CVADP): New. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp. (aarch64_sys_ins_reg_supported_p): New check for above. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/sysreg-4.s: Test instruction. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
2018-10-09[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructionsSudakshina Das2-1/+13
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order) This patch adds the prediction restriction instructions (that is, cfp, dvp, cpp). These instructions are retrospectively made optional for all versions of the architecture from ARMv8.0 to ARMv8.4 and is mandatory from ARMv8.5. Hence adding a new +predres which can be used by the older architectures. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New. (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default. (aarch64_opnd): Add AARCH64_OPND_SYSREG_SR. (aarch64_sys_regs_sr): Declare new table. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-dis.c (aarch64_ext_sysins_op): Add case for AARCH64_OPND_SYSREG_SR. * aarch64-opc.c (aarch64_print_operand): Likewise. (aarch64_sys_regs_sr): Define table. (aarch64_sys_ins_reg_supported_p): Check for RCTX with AARCH64_FEATURE_PREDRES. * aarch64-tbl.h (aarch64_feature_predres): New. (PREDRES, PREDRES_INSN): New. (aarch64_opcode_table): Add entries for cfp, dvp and cpp. (AARCH64_OPERANDS): Add new description for SYSREG_SR. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New. (parse_operands): Add entry for AARCH64_OPND_SYSREG_SR. (md_begin): Allocate and initialize aarch64_sys_regs_sr_hsh with aarch64_sys_regs_sr. (aarch64_features): Add new "predres" option for older architectures. * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/sysreg-4.s: New. * testsuite/gas/aarch64/sysreg-4.d: New. * testsuite/gas/aarch64/illegal-sysreg-4.d: New. * testsuite/gas/aarch64/illegal-sysreg-4.l: New. * testsuite/gas/aarch64/predres.s: New. * testsuite/gas/aarch64/predres.d: New.
2018-10-09[PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-ASudakshina Das2-1/+9
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order) This instruction is retrospectively made optional for all versions of the architecture from ARMv8.0 to ARMv8.4 and is mandatory from ARMv8.5. Hence a new command line option of "+sb" is added for older architectures. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_SB): New. (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SB by default. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-tbl.h (aarch64_feature_sb): New. (SB, SB_INSN): New. (aarch64_opcode_table): Add entry for sb. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (aarch64_features): Add new "sb" option for older architectures. * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/sb.s: New. * testsuite/gas/aarch64/sb.d: New.
2018-10-09[PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-ASudakshina Das2-1/+14
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order) This patch adds the data processing instructions that are new to ARMv8.5-A. 1) There are 2 instructions: xaflag, axflag, that are added to manipulate the states of the flag and are used to convert between the Arm representation and the fcmp representation. 2) The other instructions are rounding instructions which have 8 versions based on whether the floating-point number is a Single-Precision or Double-Precision number, whether the target integer is a 32-bit or 64-bit integer and whether the rounding mode is the ambient rounding mode or to zero. Each of these instruction is available in both Scalar and Vector forms. Since both 1) and 2) have separate identification mechanism and it is permissible that a ARMv8.4 compliant implementation may include any arbitrary subset of the ARMv8.5 features unless otherwise specified, new feature bits are added. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_FLAGMANIP): New. (AARCH64_FEATURE_FRINTTS): New. (AARCH64_ARCH_V8_5): Add both by default. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-tbl.h (aarch64_feature_flagmanip): New. (aarch64_feature_frintts): New. (FLAGMANIP, FRINTTS): New. (aarch64_opcode_table): Add entries for xaflag, axflag and frint[32,64][x,z] instructions. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/armv8_5-a-dp.s: New. * testsuite/gas/aarch64/armv8_5-a-dp.d: New.
2018-10-09[PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal ↵Sudakshina Das2-0/+9
feature macros This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) This is the first of the patch series and adds -march=armv8.5-a and other internal feature marcos needed for it. 2018-10-09 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (aarch64_archs): New entry for armv8.5-a. * doc/c-aarch64.texi: Add documentation for the same. *** include/ChnageLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_V8_5): New. (AARCH64_ARCH_V8_5): New. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New. (ARMV8_5, V8_5_INSN): New.
2018-10-08Separate header PT_LOAD for -z separate-codeAlan Modra2-0/+7
This patch, along with previous patches in the series, supports putting the ELF file header and program headers in a PT_LOAD without sections. Logic governing whether headers a loaded has changed a little: The primary reason to include headers is now the presence of SIZEOF_HEADERS in a linker script. However, to support scripts that may have reserved space for headers by hand, we continue to add headers whenever the first section address is past the end of headers modulo page size. include/ * bfdlink.h (struct bfd_link_info): Add load_phdrs field. bfd/ * elf-nacl.c (nacl_modify_segment_map): Cope with header PT_LOAD lacking sections. * elf.c (_bfd_elf_map_sections_to_segments): Assume file and program headers are required when info->load_phdrs. Reorganize code handling program headers. Generate a mapping without sections just for file and program headers when -z separate-code would indicate they should be on a different page to the first section. ld/ * ldexp.c (fold_name <SIZEOF_HEADERS>): Set link_info.load_phdrs. * testsuite/ld-elf/loadaddr1.d: Pass -z noseparate-code. * testsuite/ld-elf/loadaddr2.d: Likewise. * testsuite/ld-i386/vxworks2.sd: Adjust expected output. * testsuite/ld-powerpc/vxworks2.sd: Likewise. * testsuite/ld-elf/overlay.d: Remove spu xfail. * testsuite/ld-spu/ovl.lnk: Don't use SIZEOF_HEADERS. * testsuite/ld-tic6x/dsbt-be.ld: Likewise. * testsuite/ld-tic6x/dsbt-inrange.ld: Likewise. * testsuite/ld-tic6x/dsbt-overflow.ld: Likewise. * testsuite/ld-tic6x/dsbt.ld: Likewise.
2018-10-05[Arm, 3/3] Add Execution and Data Prediction instructions for AArch32Sudakshina Das2-1/+8
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) This patch adds the Execution and Data Prediction Restriction instructions (that is, cfprctx, dvprxtc, cpprctx). These are all aliases to MCR and are disassembled as such. This instruction is retrospectively made optional for all versions of the architecture from ARMv8.0 to ARMv8.4 and is mandatory from ARMv8.5. Hence adding a new +predres for older versions of the architecture. *** include/ChangeLog *** 2018-10-05 Sudakshina Das <sudi.das@arm.com> * opcode/arm.h (ARM_EXT2_PREDRES): New. (ARM_ARCH_V8_5A): Add ARM_EXT2_PREDRES by default. *** gas/ChangeLog *** 2018-10-05 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (arm_ext_predres): New. (insns): Add new cfprctx, dvprctx and cpprctx instructions. (arm_extensions): Add "predres". * doc/c-arm.texi: Document the above. * testsuite/gas/arm/predres-bad.d: New test. * testsuite/gas/arm/predres-bad.l: New test. * testsuite/gas/arm/predres.s: New test. * testsuite/gas/arm/predres1.d: New test. * testsuite/gas/arm/predres2.d: New test.
generated by cgit v1.1 at 2024-12-13 01:20:32 +0000