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2013-07-12 include/elf/Maciej W. Rozycki2-0/+7
* mips.h (EF_MIPS_NAN2008): New macro. bfd/ * elfxx-mips.c (_bfd_mips_elf_merge_private_bfd_data): Handle EF_MIPS_NAN2008. (_bfd_mips_elf_print_private_bfd_data): Likewise. binutils/ * readelf.c (get_machine_flags): Handle EF_MIPS_NAN2008. gas/ * config/tc-mips.c (mips_flag_nan2008): New variable. (options): Add OPTION_NAN enum value. (md_longopts): Handle it. (md_parse_option): Likewise. (s_nan): New function. (mips_elf_final_processing): Handle EF_MIPS_NAN2008. (md_show_usage): Add -mnan. * doc/as.texinfo (Overview): Add -mnan. * doc/c-mips.texi (MIPS Opts): Document -mnan. (MIPS NaN Encodings): New node. Document .nan directive. (MIPS-Dependent): List the new node. gas/testsuite/ * gas/mips/nan-2008-1.d: New test. * gas/mips/nan-2008-2.d: New test. * gas/mips/nan-2008-3.d: New test. * gas/mips/nan-2008-4.d: New test. * gas/mips/nan-legacy-1.d: New test. * gas/mips/nan-legacy-2.d: New test. * gas/mips/nan-legacy-3.d: New test. * gas/mips/nan-legacy-4.d: New test. * gas/mips/nan-legacy-5.d: New test. * gas/mips/nan-error-1.l: New list test. * gas/mips/nan-error-2.l: New list test. * gas/mips/nan-2008-override.s: New test source. * gas/mips/nan-2008.s: New test source. * gas/mips/nan-legacy-override.s: New test source. * gas/mips/nan-legacy.s: New test source. * gas/mips/nan-error-1.s: New test source. * gas/mips/nan-error-2.s: New test source. * gas/mips/mips.exp: Run the new tests. ld/testsuite/ * ld-mips-elf/nan-2008.d: New test. * ld-mips-elf/nan-legacy.d: New test. * ld-mips-elf/nan-mixed-1.d: New test. * ld-mips-elf/nan-mixed-2.d: New test. * ld-mips-elf/nan-2008.s: New test source. * ld-mips-elf/nan-legacy.s: New test source.
2013-07-10include/coff/Tristan Gingold2-3/+68
2013-07-10 Tristan Gingold <gingold@adacore.com> * rs6000.h (external_core_dumpx): New structure. (external_ld_info32): Ditto. binutils/ 2013-07-10 Tristan Gingold <gingold@adacore.com> * od-xcoff.c (OPT_LDINFO): Define. (options): Add ldinfo. (xcoff_help): Mention ldinfo. (xcoff_dump): Rename to ... (xcoff_dump_obj): ... this. Add a break. (dump_dumpx_core): New function. (xcoff_dump_core): Likewise. (xcoff_dump): Likewise. * doc/binutils.texi (objdump): Mention ldinfo.
2013-07-082013-07-08 Tristan Gingold <gingold@adacore.com>Tristan Gingold2-0/+8
* ia64.h (STB_VMS_WEAK, STB_VMS_SYSTEM): Add.
2013-07-07include/opcode/Richard Sandiford2-90/+28
* mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB) (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB) (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A) (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB) (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB) (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB) (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB) (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB) (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A) (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A) (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB) (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete. (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A): Rename to... (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB) (M_USD_AB): ...these. opcodes/ * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD and SD A(B) macros up. * micromips-opc.c (micromips_opcodes): Likewise. gas/ * config/tc-mips.c (gprel16_reloc_p): New function. (macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are BFD_RELOC_UNUSED. (offset_high_part, small_offset_p): New functions. (nacro): Use them. Remove *_OB and *_DOB cases. For single- register load and store macros, handle the 16-bit offset case first. If a 16-bit offset is not suitable for the instruction we're generating, load it into the temporary register using ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the M_L_DAB code once the address has been constructed. For double load and store macros, again handle the 16-bit offset case first. If the second register cannot be accessed from the same high part as the first, load it into AT using ADDRESS_ADDI_INSN. Fix the handling of LD in cases where the first register is the same as the base. Also handle the case where the offset is not 16 bits and the second register cannot be accessed from the same high part as the first. For unaligned loads and stores, fuse the offbits == 12 and old "ab" handling. Apply this handling whenever the second offset needs a different high part from the first. Construct the offset using ADDRESS_ADDI_INSN where possible, for offbits == 16 as well as offbits == 12. Use offset_reloc when constructing the individual loads and stores. (mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc and offset_reloc before matching against a particular opcode. Handle elided 'A' constants. Allow 'A' constants to use relocation operators. gas/testsuite/ * gas/mips/ldstla-32.d: Avoid "lui at,0x0" sequences for truncated constants. * gas/mips/ldstla-32-shared.d: Likewise. * gas/mips/mcu.d: Use ADDIU in preference to LI+ADDU when adding 16-bit constants to the base. * gas/mips/micromips@mcu.d: Likewise. * gas/mips/micromips@cache.d: Likewise. * gas/mips/micromips@pref.d: Likewise. * gas/mips/micromips.d, gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d: Likewise. Allow the full 16-bit offset range to be used for SB, LB and LBU in USH and ULH sequences. Fix the expected output for LD and SD when the two LW and SW offsets need different high parts. * gas/mips/eva.s: Test PREFE with relocation operators. * gas/mips/eva.d: Use ADDIU in preference to LI+ADDU for 16-bit constants. Update after eva.s change. * gas/mips/micromips@eva.d: Likewise. * gas/mips/ld-reloc.s, gas/mips/ld-reloc.d, gas/mips/l_d-reloc.s, gas/mips/l_d-reloc.d, gas/mips/ulw-reloc.s, gas/mips/ulw-reloc.d, gas/mips/micromips@ulw-reloc.d, gas/mips/ulh-reloc.s, gas/mips/ulh-reloc.d: New tests. * gas/mips/mips.exp: Run them.
2013-07-07include/opcode/Richard Sandiford2-10/+13
* mips.h: Remove documentation of "[" and "]". Update documentation of "k" and the MDMX formats. opcodes/ * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400 MDMX-like instructions. * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when printing "Q" operands for INSN_5400 instructions. gas/ * config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling. (mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions. Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions. gas/testsuite/ * gas/mips/vr5400-ill.s, gas/mips/vr5400-ill.l: New test. * gas/mips/mips.exp: Run it.
2013-07-07include/opcode/Richard Sandiford2-5/+8
* mips.h: Update documentation of "+s" and "+S". opcodes/ * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and "+S" for "cins". * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments. Combine cases. gas/ * config/tc-mips.c (mips_ip): Preserve the real bit number for "+p". Require the msb to be <= 31 for "+s". Check that the size is <= 31 for both "+s" and "+S".
2013-07-07include/opcode/Richard Sandiford2-3/+10
* mips.h: Document "+i". opcodes/ * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for "jalx". * mips16-opc.c (mips16_opcodes): Likewise. * micromips-opc.c (micromips_opcodes): Likewise. * mips-dis.c (print_insn_args, print_mips16_insn_arg) (print_insn_mips16): Handle "+i". (print_insn_micromips): Likewise. Conditionally preserve the ISA bit for "a" but not for "+i". gas/ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn): (mips_ip, mips16_ip): Handle "+i".
2013-07-07include/opcode/Richard Sandiford2-9/+11
* mips.h: Remove "mi" documentation. Update "mh" documentation. (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI): Delete. (INSN2_WRITE_GPR_MHI): Rename to... (INSN2_WRITE_GPR_MH): ...this. opcodes/ * micromips-opc.c (WR_mhi): Rename to.. (WR_mh): ...this. (micromips_opcodes): Update "movep" entry accordingly. Replace "mh,mi" with "mh". * mips-dis.c (micromips_to_32_reg_h_map): Rename to... (micromips_to_32_reg_h_map1): ...this. (micromips_to_32_reg_i_map): Rename to... (micromips_to_32_reg_h_map2): ...this. (print_micromips_insn): Remove "mi" case. Print both registers in the pair for "mh". gas/ * config/tc-mips.c (mips32_to_micromips_reg_h_map): Delete. (micromips_to_32_reg_h_map): Rename to... (micromips_to_32_reg_h_map1): ...this. (micromips_to_32_reg_i_map): Rename to... (micromips_to_32_reg_h_map2): ...this. (mips_lookup_reg_pair): New function. (gpr_write_mask, macro): Adjust after above renaming. (validate_micromips_insn): Remove "mi" handling. (mips_ip): Likewise. Parse both registers in a pair for "mh".
2013-07-07include/opcode/Richard Sandiford2-7/+6
* mips.h: Remove documentation of "+D" and "+T". opcodes/ * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries. * micromips-opc.c (micromips_opcodes): Likewise. * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D" and "+T" handling. Check for a "0" suffix when deciding whether to use coprocessor 0 names. In that case, also check for ",H" selectors. gas/ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn) (mips_ip): Remove "+D" and "+T" handling. gas/testsuite/ * gas/mips/lb.d, gas/mips/sb.d: Use coprocessor register names for LWC0 and SWC0.
2013-07-052013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>Andreas Krebbel2-0/+9
opcodes/ * s390-opc.c (J12_12, J24_24): New macros. (INSTR_MII_UPI): Rename to INSTR_MII_UPP. (MASK_MII_UPI): Rename to MASK_MII_UPP. * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction. include/elf/ * s390.h: Add new relocs R_390_PC12DBL, R_390_PLT12DBL, R_390_PC24DBL, and R_390_PLT24DBL. gas/testsuite/ * gas/s390/zarch-zEC12.s: Change bprp second operand and add variants requiring relocations. * gas/s390/zarch-zEC12.d: Likewise. gas/ * config/tc-s390.c (md_gather_operands, md_apply_fix): Support new relocs. bfd/ * elf32-s390.c: Add new relocation definitions R_390_PC12DBL, R_390_PLT12DBL, R_390_PC24DBL, and R_390_PLT24DBL. (elf_s390_reloc_type_lookup, elf_s390_check_relocs) (elf_s390_gc_sweep_hook, elf_s390_relocate_section): Support new relocations. * elf64-s390.c: See elf32-s390.c * bfd-in2.h: Add new relocs to enum bfd_reloc_code_real. * libbfd.h: Add new reloc strings.
2013-07-022013-07-02 Tristan Gingold <gingold@adacore.com>Tristan Gingold3-0/+11
* internal.h (C_STTLS, C_GTLS): Define. * xcoff.h (XMC_TL, XMC_TU, XMC_TE): Define.
2013-06-26[AArch64, ILP32] 3/6 Support for ELF32 relocs and refactor reloc handlingYufeng Zhang2-12/+128
bfd/ * bfd-in2.h: Re-generated. * elfnn-aarch64.c (HOWTO64, HOWTO32): New define. (IS_AARCH64_TLS_RELOC): Change to be based on the bfd reloc enumerators. (IS_AARCH64_TLSDESC_RELOC): Likewise. (PG, PG_OFFSET): Cast literal to bfd_vma. (elf64_aarch64_howto_table): Removed. (elf64_aarch64_howto_dynrelocs): Removed. (elf64_aarch64_tls_howto_table): Removed. (elf64_aarch64_tlsdesc_howto_table): Removed. (elfNN_aarch64_howto_table): New table to host all howto entires.. (R_AARCH64_*): Replaced by AARCH64_R (*) and AARCH64_R_STR (*). (elfNN_aarch64_bfd_reloc_from_howto): New function. (elfNN_aarch64_bfd_reloc_from_type): Ditto. (struct elf_aarch64_reloc_map): New. (elf_aarch64_reloc_map): New table. (elfNN_aarch64_howto_from_bfd_reloc): New function. (elfNN_aarch64_howto_from_type): Update to look up the new table elfNN_aarch64_howto_table. (struct elf64_aarch64_reloc_map): Remove. (elf64_aarch64_reloc_map): Remove. (elfNN_aarch64_reloc_type_lookup): Change to call elfNN_aarch64_howto_from_bfd_reloc. (elfNN_aarch64_reloc_name_lookup): Change to look up the new table elfNN_aarch64_howto_table. (aarch64_resolve_relocation): Refactor to switch on the bfd reloc enumerators. (bfd_elf_aarch64_put_addend): Likewise. (elfNN_aarch64_final_link_relocate): Likewise. (aarch64_tls_transition_without_check): Likewise. (aarch64_reloc_got_type): Likewise. (aarch64_can_relax_tls): Likewise. (aarch64_tls_transition): Likewise. (elfNN_aarch64_tls_relax): Likewise. (elfNN_aarch64_final_link_relocate): Likewise. (elfNN_aarch64_relocate_section): Likewise. (elfNN_aarch64_gc_sweep_hook): Likewise. (elfNN_aarch64_check_relocs): Likewise. (aarch64_tls_transition): Change to return a bfd reloc enumerator. * libbfd.h: Re-generated. * reloc.c: Re-order the AArch64 bfd reloc enumerators. (BFD_RELOC_AARCH64_RELOC_START) (BFD_RELOC_AARCH64_RELOC_END) (BFD_RELOC_AARCH64_LD_GOT_LO12_NC) (BFD_RELOC_AARCH64_LD32_GOT_LO12_NC) (BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC) (BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC) (BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC) (BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC) (BFD_RELOC_AARCH64_IRELATIVE): New relocs. gas/ * config/tc-aarch64.c (reloc_table): Replace BFD_RELOC_AARCH64_LD64_GOT_LO12_NC with BFD_RELOC_AARCH64_LD_GOT_LO12_NC; likewise to BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC and BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC. (md_apply_fix): Handle BFD_RELOC_AARCH64_LD_GOT_LO12_NC, BFD_RELOC_AARCH64_LD32_GOT_LO12_NC, BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC, BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC, BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC and BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC. (aarch64_force_relocation): Likewise. gas/testsuite/ * gas/aarch64/ilp32-basic.d: New file. * gas/aarch64/ilp32-basic.s: New file. include/elf/ * aarch64.h: Add ELF32 reloc codes and remove fake ELF64 ones. (R_AARCH64_IRELATIVE): New reloc.
2013-06-26include/opcode/Richard Sandiford2-4/+9
* mips.h: Fix comment for "1": it is now STYPE rather than SHAMT. Use "source" rather than "destination" for microMIPS "G". gas/ * config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT.
2013-06-25 bfd/Maciej W. Rozycki2-0/+8
* elfxx-mips.h (_bfd_mips_elf_insn32): New prototype. * elfxx-mips.c (mips_elf_link_hash_table): Add insn32 member. (STUB_MOVE32_MICROMIPS, STUB_JALR32_MICROMIPS): New macros. (MICROMIPS_INSN32_FUNCTION_STUB_NORMAL_SIZE): Likewise. (MICROMIPS_INSN32_FUNCTION_STUB_BIG_SIZE): Likewise. (micromips_insn32_o32_exec_plt0_entry): New variable. (micromips_insn32_o32_exec_plt_entry): Likewise. (_bfd_mips_elf_adjust_dynamic_symbol): Handle insn32 mode. (mips_elf_estimate_stub_size): Likewise. (_bfd_mips_elf_size_dynamic_sections): Likewise. (_bfd_mips_elf_finish_dynamic_symbol): Likewise. (mips_finish_exec_plt): Likewise. (_bfd_mips_elf_relax_section): Likewise. (_bfd_mips_elf_insn32): New function. (_bfd_mips_elf_get_synthetic_symtab): Handle insn32 PLT. gas/ * config/tc-mips.c (mips_set_options): Add insn32 member. (mips_opts): Initialize it. (NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode. (options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values. (md_longopts): Add "minsn32" and "mno-insn32" options. (is_size_valid): Handle insn32 mode. (md_assemble): Pass instruction string down to macro. (brk_fmt): Add second dimension and insn32 mode initializers. (mfhl_fmt): Likewise. (BRK_FMT, MFHL_FMT): Handle insn32 mode. (macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding. (macro_build_jalr, move_register): Handle insn32 mode. (macro_build_branch_rs): Likewise. (macro): Handle insn32 mode. <M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases. (mips_ip): Handle insn32 mode. (md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32. (s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops. (mips_handle_align): Handle insn32 mode. (md_show_usage): Add -minsn32 and -mno-insn32. * doc/as.texinfo (Target MIPS options): Add -minsn32 and -mno-insn32 options. (-minsn32, -mno-insn32): New options. * doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32 options. (MIPS assembly options): New node. Document .set insn32 and .set noinsn32. (MIPS-Dependent): List the new node. gas/testsuite/ * gas/mips/micromips-insn32.d: New test. * gas/mips/micromips-noinsn32.d: Likewise. * gas/mips/micromips.l: Rename to... * gas/mips/micromips-warn.l: ... this. * gas/mips/micromips.d: Update accordingly. * gas/mips/micromips-trap.d: Likewise. * gas/mips/micromips.l: New list test. * gas/mips/micromips.s: Add conditionals. * gas/mips/mips.exp: Run the new tests. include/opcode/ * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum values. ld/ * emultempl/mipself.em (insn32): New variable. (mips_create_output_section_statements): Handle insn32 mode. (PARSE_AND_LIST_PROLOGUE): New macro. (PARSE_AND_LIST_LONGOPTS): Likewise. (PARSE_AND_LIST_OPTIONS): Likewise. * gen-doc.texi: Set MIPS. * ld.texinfo: Likewise. (Options specific to MIPS targets): New section. (ld and MIPS family): New node. (Top, Machine Dependent): List the new node. opcodes/ * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc" and "movep" macros.
2013-06-24 bfd/Maciej W. Rozycki2-2/+13
* elfxx-mips.h (_bfd_mips_elf_get_synthetic_symtab): New prototype. * elf32-mips.c (elf_backend_plt_sym_val): Remove macro. (bfd_elf32_get_synthetic_symtab): New macro. * elfxx-mips.c (plt_entry): New structure. (mips_elf_link_hash_entry): Add use_plt_entry member. (mips_elf_link_hash_table): Rename plt_entry_size member to plt_mips_entry_size. Add plt_comp_entry_size, plt_mips_offset, plt_comp_offset, plt_got_index entries and plt_header_is_comp members. (STUB_LW_MICROMIPS, STUB_MOVE_MICROMIPS): New macros. (STUB_LUI_MICROMIPS, STUB_JALR_MICROMIPS): Likewise. (STUB_ORI_MICROMIPS, STUB_LI16U_MICROMIPS): Likewise. (STUB_LI16S_MICROMIPS): Likewise. (MICROMIPS_FUNCTION_STUB_NORMAL_SIZE): Likewise. (MICROMIPS_FUNCTION_STUB_BIG_SIZE): Likewise. (micromips_o32_exec_plt0_entry): New variable. (mips16_o32_exec_plt_entry): Likewise. (micromips_o32_exec_plt_entry): Likewise. (mips_elf_link_hash_newfunc): Initialize use_plt_entry. (mips_elf_output_extsym): Update to use gotplt_union's plist member rather than offset. (mips_elf_gotplt_index): Likewise. Remove the VxWorks restriction. Use MIPS_ELF_GOT_SIZE to calculate GOT address. (mips_elf_count_got_symbols): Update to use gotplt_union's plist member rather than offset. (mips_elf_calculate_relocation): Handle MIPS16/microMIPS PLT entries. (_bfd_mips_elf_create_dynamic_sections): Don't set PLT sizes here. (mips_elf_make_plt_record): New function. (_bfd_mips_elf_check_relocs): Update comment. Record occurences of JAL relocations that might need a PLT entry. (_bfd_mips_elf_adjust_dynamic_symbol): Update to use gotplt_union's plist member rather than offset. Set individual PLT entry sizes here. Handle MIPS16/microMIPS PLT entries. Don't set the symbol's value in the symbol table for PLT references here. Don't set the PLT or PLT GOT section sizes here. (mips_elf_estimate_stub_size): Handle microMIPS stubs. (mips_elf_allocate_lazy_stub): Likewise. (mips_elf_lay_out_lazy_stubs): Likewise. Define a _MIPS_STUBS_ magic symbol. (mips_elf_set_plt_sym_value): New function. (_bfd_mips_elf_size_dynamic_sections): Set PLT header size and PLT and PLT GOT section sizes here. Set the symbol values in the symbol table for PLT references here. Handle microMIPS annotation of the _PROCEDURE_LINKAGE_TABLE_ magic symbol. (_bfd_mips_elf_finish_dynamic_symbol): Update to use gotplt_union's plist member rather than offset. Handle MIPS16/microMIPS PLT entries. Handle microMIPS stubs. (_bfd_mips_vxworks_finish_dynamic_symbol): Update to use gotplt_union's plist member rather than offset. Use MIPS_ELF_GOT_SIZE to calculate GOT address. (mips_finish_exec_plt): Handle microMIPS PLT. Return status. (_bfd_mips_elf_finish_dynamic_sections): Handle result from mips_finish_exec_plt. (_bfd_mips_elf_link_hash_table_create): Update to use gotplt_union's plist member rather than offset. (_bfd_mips_elf_get_synthetic_symtab): New function. include/elf/ * mips.h (ELF_ST_IS_MIPS_PLT): Respect STO_MIPS16 setting. (ELF_ST_SET_MIPS_PLT): Likewise. gdb/ * mips-tdep.c (mips_elf_make_msymbol_special): Handle MIPS16 and microMIPS synthetic symbols. ld/ * emulparams/elf32btsmip.sh: Arrange for .got.plt to be placed as close to .plt as possible. * scripttempl/elf.sc: Handle $INITIAL_READWRITE_SECTIONS and $PLT_NEXT_DATA variables. ld/testsuite/ * ld-mips-elf/jalx-2.dd: Update for microMIPS PLT support. * ld-mips-elf/pic-and-nonpic-3a.dd: Update for the _MIPS_STUBS_ magic symbol. * ld-mips-elf/pic-and-nonpic-3b.dd: Likewise. * ld-mips-elf/pic-and-nonpic-6-n32.dd: Likewise. * ld-mips-elf/pic-and-nonpic-6-n64.dd: Likewise. * ld-mips-elf/pic-and-nonpic-6-o32.dd: Likewise. * ld-mips-elf/stub-dynsym-1-10000.d: Likewise. * ld-mips-elf/stub-dynsym-1-2fe80.d: Likewise. * ld-mips-elf/stub-dynsym-1-7fff.d: Likewise. * ld-mips-elf/stub-dynsym-1-8000.d: Likewise. * ld-mips-elf/stub-dynsym-1-fff0.d: Likewise. * ld-mips-elf/tlslib-o32.d: Likewise. opcodes/ * mips-dis.c (is_mips16_plt_tail): New function. (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address word. (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
2013-06-23include/opcode/Richard Sandiford2-1/+5
* mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS. gas/ * config/tc-mips.c (mips_ip): Fix swapped bit numbers in comments.
2013-06-21 * msp430-decode.opc: New.Nick Clifton1-0/+130
* msp430-decode.c: New/generated. * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c. (MAINTAINER_CLEANFILES): Likewise. Add rule to build msp430-decode.c frommsp430decode.opc using the opc2c program. * Makefile.in: Regenerate. * configure.in: Add msp430-decode.lo to msp430 architecture files. * configure: Regenerate. * msp430-decode.h: New.
2013-06-19aarch64: Revert AArch64 ifunc changes.Will Newton2-2/+5
The AArch64 ifunc patch introduced a regression caused by incorrect PLT layout. Revert it until a fix is verified. bfd/ChangeLog: 2013-06-19 Will Newton <will.newton@linaro.org> * configure: Regenerated. * configure.in: Remove aarch64 dependency on elf-ifunc.c. * elf64-aarch64.c: Remove objalloc.h include. (elf64_aarch64_howto_dynrelocs): Remove R_AARCH64_IRELATIVE howto. (struct elf64_aarch64_link_hash_table): Remove ifunc related members. (elf_aarch64_local_htab_hash): Remove function. (elf_aarch64_local_htab_eq): Remove function. (elf_aarch64_get_local_sym_hash): Remove function. (elf64_aarch64_link_hash_table_create): Remove local hash table initialization. (elf64_aarch64_final_link_relocate): Remove sym argument and handling of ifunc symbols. (elf64_aarch64_relocate_section): Don't pass sym argument to elf64_aarch64_final_link_relocate. (elf64_aarch64_gc_sweep_hook): Remove handling of ifunc symbols. (elf64_aarch64_adjust_dynamic_symbol): Likewise. (elf64_aarch64_check_relocs): Likewise. (elf64_aarch64_post_process_headers): Remove call to _bfd_elf_set_osabi. (elf64_aarch64_is_function_type): New function. (elf64_aarch64_allocate_dynrelocs): Remove handling of ifunc symbols. (elf_aarch64_allocate_local_dynrelocs): Remove function. (elf64_aarch64_size_dynamic_sections): Remove call to elf_aarch64_allocate_local_dynrelocs. (elf64_aarch64_create_small_pltn_entry): Remove info argument. Remove creation of R_AARCH64_IRELATIVE dynamic relocs. (elf64_aarch64_finish_dynamic_symbol): Remove handling of ifunc symbols. (elf_aarch64_finish_local_dynamic_symbol): Remove function. (elf64_aarch64_finish_dynamic_sections): Remove call to elf_aarch64_finish_local_dynamic_symbol. (elf64_aarch64_add_symbol_hook): Remove function. include/elf/ChangeLog: 2013-06-19 Will Newton <will.newton@linaro.org> * aarch64.h: Remove R_AARCH64_IRELATIVE. ld/ChangeLog: 2013-06-19 Will Newton <will.newton@linaro.org> * emulparams/aarch64elf.sh: Remove IREL_IN_PLT. ld/testsuite/ChangeLog: 2013-06-19 Will Newton <will.newton@linaro.org> * ld-aarch64/aarch64-elf.exp: Remove ifunc tests. * ld-ifunc/ifunc.exp: Disable ifunc tests on AArch64. * ld-aarch64/ifunc-1-local.d: Remove. * ld-aarch64/ifunc-1-local.s: Likewise. * ld-aarch64/ifunc-1.d: Likewise. * ld-aarch64/ifunc-1.s: Likewise. * ld-aarch64/ifunc-10.d: Likewise. * ld-aarch64/ifunc-10.s: Likewise. * ld-aarch64/ifunc-11.d: Likewise. * ld-aarch64/ifunc-11.s: Likewise. * ld-aarch64/ifunc-12.d: Likewise. * ld-aarch64/ifunc-12.s: Likewise. * ld-aarch64/ifunc-13.d: Likewise. * ld-aarch64/ifunc-13a.s: Likewise. * ld-aarch64/ifunc-13b.s: Likewise. * ld-aarch64/ifunc-14a.d: Likewise. * ld-aarch64/ifunc-14a.s: Likewise. * ld-aarch64/ifunc-14b.d: Likewise. * ld-aarch64/ifunc-14b.s: Likewise. * ld-aarch64/ifunc-14c.d: Likewise. * ld-aarch64/ifunc-14c.s: Likewise. * ld-aarch64/ifunc-14d.d: Likewise. * ld-aarch64/ifunc-14e.d: Likewise. * ld-aarch64/ifunc-14f.d: Likewise. * ld-aarch64/ifunc-15.d: Likewise. * ld-aarch64/ifunc-15.s: Likewise. * ld-aarch64/ifunc-16.d: Likewise. * ld-aarch64/ifunc-16.s: Likewise. * ld-aarch64/ifunc-17a.d: Likewise. * ld-aarch64/ifunc-17a.s: Likewise. * ld-aarch64/ifunc-17b.d: Likewise. * ld-aarch64/ifunc-17b.s: Likewise. * ld-aarch64/ifunc-18a.d: Likewise. * ld-aarch64/ifunc-18a.s: Likewise. * ld-aarch64/ifunc-18b.d: Likewise. * ld-aarch64/ifunc-18b.s: Likewise. * ld-aarch64/ifunc-19a.d: Likewise. * ld-aarch64/ifunc-19a.s: Likewise. * ld-aarch64/ifunc-19b.d: Likewise. * ld-aarch64/ifunc-19b.s: Likewise. * ld-aarch64/ifunc-2-local.d: Likewise. * ld-aarch64/ifunc-2-local.s: Likewise. * ld-aarch64/ifunc-2.d: Likewise. * ld-aarch64/ifunc-2.s: Likewise. * ld-aarch64/ifunc-20.d: Likewise. * ld-aarch64/ifunc-20.s: Likewise. * ld-aarch64/ifunc-3.s: Likewise. * ld-aarch64/ifunc-3a.d: Likewise. * ld-aarch64/ifunc-3b.d: Likewise. * ld-aarch64/ifunc-4.d: Likewise. * ld-aarch64/ifunc-4.s: Likewise. * ld-aarch64/ifunc-4a.d: Likewise. * ld-aarch64/ifunc-5-local.s: Likewise. * ld-aarch64/ifunc-5.s: Likewise. * ld-aarch64/ifunc-5a-local.d: Likewise. * ld-aarch64/ifunc-5a.d: Likewise. * ld-aarch64/ifunc-5b-local.d: Likewise. * ld-aarch64/ifunc-5b.d: Likewise. * ld-aarch64/ifunc-5r-local.d: Likewise. * ld-aarch64/ifunc-6.s: Likewise. * ld-aarch64/ifunc-6a.d: Likewise. * ld-aarch64/ifunc-6b.d: Likewise. * ld-aarch64/ifunc-7.s: Likewise. * ld-aarch64/ifunc-7a.d: Likewise. * ld-aarch64/ifunc-7b.d: Likewise. * ld-aarch64/ifunc-7c.d: Likewise. * ld-aarch64/ifunc-8.d: Likewise. * ld-aarch64/ifunc-8a.s: Likewise. * ld-aarch64/ifunc-8b.s: Likewise. * ld-aarch64/ifunc-9.d: Likewise. * ld-aarch64/ifunc-9.s: Likewise.
2013-06-172013-06-17 Catherine Moore <clm@codesourcery.com>Catherine Moore2-5/+77
Maciej W. Rozycki <macro@codesourcery.com> Chao-Ying Fu <fu@mips.com> gas/testsuite/ * gas/mips/mips.exp: Run new tests. * gas/mips/eva.d: New. * gas/mips/eva.s: New. * gas/mips/micromips@eva.d: New. gas/ * config/tc-mips.c (mips_set_options): Add ase_eva. (mips_set_options mips_opts): Add ase_eva. (file_ase_eva): Declare. (ISA_SUPPORTS_EVA_ASE): Define. (IS_SEXT_9BIT_NUM): Define. (MIPS_CPU_ASE_EVA): Define. (is_opcode_valid): Add support for ase_eva. (macro_build): Likewise. (macro): Likewise. (validate_mips_insn): Likewise. (validate_micromips_insn): Likewise. (mips_ip): Likewise. (options): Add OPTION_EVA and OPTION_NO_EVA. (md_longopts): Add -meva and -mno-eva. (md_parse_option): Process new options. (mips_after_parse_args): Check for valid EVA combinations. (s_mipsset): Likewise. include/ * opcode/mips.h (OP_SH_EVAOFFSET): Define. (OP_MASK_EVAOFFSET): Define. (INSN_ASE_MASK): Delete. (ASE_EVA): Define. (M_CACHEE_AB, M_CACHEE_OB): New. (M_LBE_OB, M_LBE_AB): New. (M_LBUE_OB, M_LBUE_AB): New. (M_LHE_OB, M_LHE_AB): New. (M_LHUE_OB, M_LHUE_AB): New. (M_LLE_AB, M_LLE_OB): New. (M_LWE_OB, M_LWE_AB): New. (M_LWLE_AB, M_LWLE_OB): New. (M_LWRE_AB, M_LWRE_OB): New. (M_PREFE_AB, M_PREFE_OB): New. (M_SCE_AB, M_SCE_OB): New. (M_SBE_OB, M_SBE_AB): New. (M_SHE_OB, M_SHE_AB): New. (M_SWE_OB, M_SWE_AB): New. (M_SWLE_AB, M_SWLE_OB): New. (M_SWRE_AB, M_SWRE_OB): New. (MICROMIPSOP_SH_EVAOFFSET): Define. (MICROMIPSOP_MASK_EVAOFFSET): Define. opcodes/ * micromips-opc.c (EVA): Define. (TLBINV): Define. (micromips_opcodes): Add EVA opcodes. * mips-dis.c (mips_arch_choices): Update for ASE_EVA. (print_insn_args): Handle EVA offsets. (print_insn_micromips): Likewise. * mips-opc.c (EVA): Define. (TLBINV): Define. (mips_builtin_opcodes): Add EVA opcodes.
2013-06-122013-06-12 Sandra Loosemore <sandra@codesourcery.com>Sandra Loosemore2-1/+5
include/opcode/ * nios2.h (OP_MATCH_ERET): Correct eret encoding. gas/testsuite/ * gas/nios2/tret.d: Correct eret encoding.
2013-06-08gas/Richard Sandiford2-23/+38
2013-06-08 Catherine Moore <clm@codesourcery.com> * config/tc-mips.c (is_opcode_valid): Build ASE mask. (is_opcode_valid_16): Pass ase value to opcode_is_member. (append_insn): Change INSN_xxxx to ASE_xxxx. include/ 2013-06-08 Catherine Moore <clm@codesourcery.com> * opcode/mips.h (mips_opcode): Add ase field. (INSN_ASE_MASK): Delete. (INSN_DSP): Rename to ASE_DSP. Provide new value. (INSN_DSPR2): Rename to ASE_DSPR2. Provide new value. (INSN_MCU): Rename to ASE_MCU. Provide new value. (INSN_MDMX): Rename to ASE_MDMX. Provide new value. (INSN_MIPS3d): Rename to ASE_MIPS3D. Provide new value. (INSN_MT): Rename to ASE_MT. Provide new value. (INSN_SMARTMIPS): Rename to ASE_SMARTMIPS. Provide new value. (INSN_VIRT): Rename to ASE_VIRT. Provide new value. (INSN_VIRT64): Rename to ASE_VIRT64. Provide new value. (opcode_is_member): Add ase argument. Check ase. opcodes/ 2013-06-08 Catherine Moore <clm@codesourcery.com> Richard Sandiford <rdsandiford@googlemail.com> * micromips-opc.c (D32, D33, MC): Update definitions. (micromips_opcodes): Initialize ase field. * mips-dis.c (mips_arch_choice): Add ase field. (mips_arch_choices): Initialize ase field. (set_default_mips_dis_options): Declare and setup mips_ase. * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64, MT32, MC): Update definitions. (mips_builtin_opcodes): Initialize ase field.
2013-06-07aarch64: Add support for GNU indirect functions.Will Newton2-1/+6
Add support for STT_GNU_IFUNC symbols to the AArch64 bfd backend. The tests are ported from the ld-ifunc tests but are enabled for cross builds so can be run easily without hardware or a simulator. bfd/ChangeLog: 2013-06-07 Will Newton <will.newton@linaro.org> * configure: Regenerate. * configure.in: Build elf-ifunc.o for AArch64. * elf64-aarch64.c: Include objalloc.h. (elf64_aarch64_howto_dynrelocs): Add R_AARCH64_IRELATIVE howto. (struct elf64_aarch64_link_hash_table): Add members for handling R_AARCH64_IRELATIVE relocations. (elf_aarch64_local_htab_hash): New function. (elf_aarch64_local_htab_eq): New function. (elf_aarch64_get_local_sym_hash): New function. (elf64_aarch64_link_hash_table_create): Initialize local STT_GNU_IFUNC symbol hash. (elf64_aarch64_hash_table_free): Free local STT_GNU_IFUNC symbol hash. (elf64_aarch64_final_link_relocate): Add sym argument. Add support for handling STT_GNU_IFUNC symbols. (elf64_aarch64_gc_sweep_hook): Add support for garbage collecting references to STT_GNU_IFUNC symbols. (elf64_aarch64_adjust_dynamic_symbol): Add support for handling STT_GNU_IFUNC symbols. (elf64_aarch64_check_relocs): Add support for handling STT_GNU_IFUNC symbols. Ensure we don't increase plt.refcount from -1 to 0. (elf64_aarch64_post_process_headers): Call _bfd_elf_set_osabi. (elf64_aarch64_is_function_type): Remove function. (elf64_aarch64_allocate_dynrelocs): Call _bfd_elf_allocate_ifunc_dyn_relocs for STT_GNU_IFUNC symbols. (elf_aarch64_allocate_local_dynrelocs): New function. (elf64_aarch64_size_dynamic_sections): Call elf_aarch64_allocate_local_dynrelocs. Initialize next_irelative_index. (elf64_aarch64_create_small_pltn_entry): Add info argument. Add support for creating .iplt entries for STT_GNU_IFUNC symbols. (elf64_aarch64_finish_dynamic_symbol): Add support for handling STT_GNU_IFUNC symbols and .iplt. (elf_aarch64_finish_local_dynamic_symbol): New function. (elf64_aarch64_finish_dynamic_sections): Call elf_aarch64_finish_local_dynamic_symbol. (elf64_aarch64_add_symbol_hook): New function. include/elf/ChangeLog: 2013-06-07 Will Newton <will.newton@linaro.org> * aarch64.h: Add R_AARCH64_IRELATIVE reloc. ld/ChangeLog: 2013-06-07 Will Newton <will.newton@linaro.org> * emulparams/aarch64elf.sh: Add IREL_IN_PLT. ld/testsuite/ChangeLog: 2013-06-07 Will Newton <will.newton@linaro.org> * ld-ifunc/ifunc.exp: Enable ifunc tests for AArch64. * ld-aarch64/aarch64-elf.exp: Add ifunc tests. * ld-aarch64/ifunc-1-local.d: New file. * ld-aarch64/ifunc-1-local.s: Likewise. * ld-aarch64/ifunc-1.d: Likewise. * ld-aarch64/ifunc-1.s: Likewise. * ld-aarch64/ifunc-10.d: Likewise. * ld-aarch64/ifunc-10.s: Likewise. * ld-aarch64/ifunc-11.d: Likewise. * ld-aarch64/ifunc-11.s: Likewise. * ld-aarch64/ifunc-12.d: Likewise. * ld-aarch64/ifunc-12.s: Likewise. * ld-aarch64/ifunc-13.d: Likewise. * ld-aarch64/ifunc-13a.s: Likewise. * ld-aarch64/ifunc-13b.s: Likewise. * ld-aarch64/ifunc-14a.d: Likewise. * ld-aarch64/ifunc-14a.s: Likewise. * ld-aarch64/ifunc-14b.d: Likewise. * ld-aarch64/ifunc-14b.s: Likewise. * ld-aarch64/ifunc-14c.d: Likewise. * ld-aarch64/ifunc-14c.s: Likewise. * ld-aarch64/ifunc-14d.d: Likewise. * ld-aarch64/ifunc-14e.d: Likewise. * ld-aarch64/ifunc-14f.d: Likewise. * ld-aarch64/ifunc-15.d: Likewise. * ld-aarch64/ifunc-15.s: Likewise. * ld-aarch64/ifunc-16.d: Likewise. * ld-aarch64/ifunc-16.s: Likewise. * ld-aarch64/ifunc-17a.d: Likewise. * ld-aarch64/ifunc-17a.s: Likewise. * ld-aarch64/ifunc-17b.d: Likewise. * ld-aarch64/ifunc-17b.s: Likewise. * ld-aarch64/ifunc-18a.d: Likewise. * ld-aarch64/ifunc-18a.s: Likewise. * ld-aarch64/ifunc-18b.d: Likewise. * ld-aarch64/ifunc-18b.s: Likewise. * ld-aarch64/ifunc-19a.d: Likewise. * ld-aarch64/ifunc-19a.s: Likewise. * ld-aarch64/ifunc-19b.d: Likewise. * ld-aarch64/ifunc-19b.s: Likewise. * ld-aarch64/ifunc-2-local.d: Likewise. * ld-aarch64/ifunc-2-local.s: Likewise. * ld-aarch64/ifunc-2.d: Likewise. * ld-aarch64/ifunc-2.s: Likewise. * ld-aarch64/ifunc-20.d: Likewise. * ld-aarch64/ifunc-20.s: Likewise. * ld-aarch64/ifunc-3.s: Likewise. * ld-aarch64/ifunc-3a.d: Likewise. * ld-aarch64/ifunc-3b.d: Likewise. * ld-aarch64/ifunc-4.d: Likewise. * ld-aarch64/ifunc-4.s: Likewise. * ld-aarch64/ifunc-4a.d: Likewise. * ld-aarch64/ifunc-5-local.s: Likewise. * ld-aarch64/ifunc-5.s: Likewise. * ld-aarch64/ifunc-5a-local.d: Likewise. * ld-aarch64/ifunc-5a.d: Likewise. * ld-aarch64/ifunc-5b-local.d: Likewise. * ld-aarch64/ifunc-5b.d: Likewise. * ld-aarch64/ifunc-5r-local.d: Likewise. * ld-aarch64/ifunc-6.s: Likewise. * ld-aarch64/ifunc-6a.d: Likewise. * ld-aarch64/ifunc-6b.d: Likewise. * ld-aarch64/ifunc-7.s: Likewise. * ld-aarch64/ifunc-7a.d: Likewise. * ld-aarch64/ifunc-7b.d: Likewise. * ld-aarch64/ifunc-8.d: Likewise. * ld-aarch64/ifunc-8a.s: Likewise. * ld-aarch64/ifunc-8b.s: Likewise. * ld-aarch64/ifunc-9.d: Likewise. * ld-aarch64/ifunc-9.s: Likewise.
2013-06-06 * mips.h (ELF_ST_SET_MIPS_PIC): Clear any STO_MIPS16 setting.Maciej W. Rozycki2-1/+8
2013-06-01 * gas/config/tc-avr.c: Change ISA for devices with USB support toDenis Chertykov1-6/+7
AVR_ISA_XMEGAU * include/opcode/avr.h: Rename AVR_ISA_XCH to AVR_ISA_RMW. Remove from AVR_ISA_XMEGA and add new AVR_ISA_XMEGAU
2013-05-302013-05-30 Paul Brook <paul@codesourcery.com>Catherine Moore2-0/+5
bfd/ * bfd-in2.h: Regenerate. * elf32-mips.c (elf_mips_eh_howto): New. (bfd_elf32_bfd_reloc_type_lookup ): Support BFD_RELOC_MIPS_EH. (bfd_elf32_bfd_reloc_name_lookup): Likewise. (mips_elf32_rtype_to_howto): Support R_MIPS_EH. * elf64-mips.c (elf_mips_eh_howto): New. (bfd_elf64_bfd_reloc_type_lookup): Support BFD_RELOC_MIPS_EH. (bfd_elf64_bfd_reloc_name_lookup): Likewise. (mips_elf64_rtype_to_howto): Support R_MIPS_EH. * libbfd.h: Regenerate. * reloc.c (BFD_RELOC_MIPS_EH): New. gas/ * config/tc-mips.c (md_apply_fix): Support BFD_RELOC_MIPS_EH. include/elf * mips.h (R_MIPS_EH): New.
2013-05-28Correct the relocation names for R_AARCH64_TLSDESC_LD_PREL19 and ↵Yufeng Zhang2-2/+9
R_AARCH64_TLSDESC_ADR_PAGE21.
2013-05-22include/opcode/Richard Sandiford2-0/+6
2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> * mips.h (M_LQC2_AB, M_SQC2_AB): New macros. opcodes/ 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions. gas/ 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> * config/tc-mips.c (macro): Handle M_LQC2_AB and M_SQC2_AB. gas/testsuite/ 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> * gas/mips/r5900-full.s, gas/mips/r5900-full.d: Add tests for LQ and SQ macros. * gas/mips/r5900-vu0.s, gas/mips/r5900-vu0.d: New test. * gas/mips/mips.exp: Run it.
2013-05-22Add EM_INTEL205 to EM_INTEL209H.J. Lu2-0/+13
* common.h (EM_INTEL205): New. (EM_INTEL206): Likewise. (EM_INTEL207): Likewise. (EM_INTEL208): Likewise. (EM_INTEL209): Likewise.
2013-05-10binutils/ChangeLog:Andrew Pinski2-4/+22
* doc/binutils.texi: Document -Mvirt disassembler option. gas/ChangeLog: * config/tc-mips.c (struct mips_set_options): New ase_virt field. (mips_opts): Update for the new field. (file_ase_virt): New variable. (ISA_SUPPORTS_VIRT_ASE): New macro. (ISA_SUPPORTS_VIRT64_ASE): New macro. (MIPS_CPU_ASE_VIRT): New define. (is_opcode_valid): Handle ase_virt. (macro_build): Handle "+J". (validate_mips_insn): Likewise. (mips_ip): Likewise. (enum options): Add OPTION_VIRT and OPTION_NO_VIRT. (md_longopts): Add mvirt and mnovirt (md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT. (mips_after_parse_args): Handle ase_virt field. (s_mipsset): Handle "virt" and "novirt". (mips_elf_final_processing): Add a comment about virt ASE might need a new flag. (md_show_usage): Print out the usage of -mvirt and mno-virt options. * doc/c-mips.texi: Document -mvirt and -mno-virt. Document ".set virt" and ".set novirt". gas/testsuite/ChangeLog: * gas/mips/mips.exp: Run virt and virt64 testcases. * gas/mips/virt.d: New file. * gas/mips/virt.s: New file. * gas/mips/virt64.d: New file. * gas/mips/virt64.s: New file. include/opcode/ChangeLog: * mips.h (OP_MASK_CODE10): Correct definition. (OP_SH_CODE10): Likewise. Add a comment that "+J" is used now for OP_*CODE10. (INSN_ASE_MASK): Update. (INSN_VIRT): New macro. (INSN_VIRT64): New macro opcodes/ChangeLog: * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2 . Add INSN_VIRT and INSN_VIRT64 to mips64r2. (parse_mips_dis_option): Handle the virt option. (print_insn_args): Handle "+J". (print_mips_disassembler_options): Print out message about virt64. * mips-opc.c (IVIRT): New define. (IVIRT64): New define. (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions. Move rfe to the bottom as it conflicts with tlbgp.
2013-05-062013-05-06 Paul Brook <paul@codesourcery.com>Catherine Moore2-3/+7
include/elf/ * mips.h (R_MIPS_PC32): Update comment. * elf64-mips.c (elf_mips_gnu_pcrel32): New. (bfd_elf64_bfd_reloc_type_lookup, bfd_elf64_bfd_reloc_name_lookup, mips_elf64_rtype_to_howto): Handle R_MIPS_PC32. * elfn32-mips.c (elf_mips_gnu_pcrel32): New. (bfd_elfn32_bfd_reloc_type_lookup, bfd_elfn32_bfd_reloc_name_lookup, mips_elfn32_rtype_to_howto): Handle R_MIPS_PC32. 2013-05-06 Paul Brook <paul@codesourcery.com> Catherine Moore <clm@codesourcery.com> gas/ * config/tc-mips.c (md_pcrel_from): Handle BFD_RELOC_32_PCREL. (limited_pcrel_reloc_p): Likewise. (md_apply_fix): Likewise. (tc_gen_reloc): Likewise.
2013-05-02 * archures.c: Add some more MSP430 machine numbers.Nick Clifton4-3/+124
* config.bfd (msp430): Define targ_selvecs. * configure.in: Add bfd_elf32_msp430_ti_vec. * cpu-msp430.c: Add some more MSP430 machine numbers. * elf32-msp430.c Add support for MSP430X relocations. Add support for TI compiler generated relocations. Add support for sym_diff relocations. Add support for relaxing out of range short branches into long branches. Add support for MSP430 attribute section. * reloc.c: Add MSP430X relocations. * targets.c: Add bfd_elf32_msp430_ti_vec. * bfd-in2.h: Regenerate. * configure: Regenerate. * libbfd.h: Regenerate. * readelf.c: Add support for MSP430X architecture. * readelf.exp: Expect -wi test to fail for the MSP430. * config/tc-msp430.c: Add support for the MSP430X architecture. Add code to insert a NOP instruction after any instruction that might change the interrupt state. Add support for the LARGE memory model. Add code to initialise the .MSP430.attributes section. * config/tc-msp430.h: Add support for the MSP430X architecture. * doc/c-msp430.texi: Document the new -mL and -mN command line options. * NEWS: Mention support for the MSP430X architecture. * gas/all/gas.exp: Skip the DIFF1 test for the MSP430. Expect the FORWARD test to pass for the MSP430. Skip the REDEF tests for the MSP430. Expect the 930509A test to fail for the MSP430. * gas/all/sleb128-4.d: Skip for the MSP430. * gas/elf/elf.exp: Set target_machine to msp430 for the MSP430. Skip the EHOPT0 test for the MSP430. Skip the REDEF and EQU-RELOC tests for the MSP430. * gas/elf/section2.e-msp430: New file. * gas/lns/lns-big-delta.d: Remove expectation of 20-bit addresses. * gas/lns/lns.exp: Use alternate LNS COMMON test for the MSP430. * gas/msp430/msp430x.s: New test. * gas/msp430/msp430x.d: Expected disassembly. * gas/msp430/msp430.exp: Run new test. * gas/msp430/opcode.d: Update expected disassembly. * msp430.h: Add MSP430X relocs. Add some more MSP430 machine numbers. Add values used by .MSP430.attributes section. * msp430.h: Add patterns for MSP430X instructions. * Makefile.am: Add emsp430X.c * Makefine.in: Regenerate. * configure.tgt (msp430): Add msp430X emulation. * ldmain.c (multiple_definition): Only disable relaxation if it was enabled by the user. * ldmain.h (RELAXATION_ENABLED_BY_USER): New macro. * emulparams/msp430all.sh: Add support for MSP430X. * emultempl/generic.em: (before_parse): Enable relaxation for the MSP430. * scripttempl/msp430.sc: Reorganize sections. Add .rodata section. * scripttempl/msp430_3.sc: Likewise. * NEWS: Mention support for MSP430X. * ld-elf/flags1.d: Expect this test to pass on the MSP430. * ld-elf/init-fini-arrays.d: Expect this test to fail on the MSP430. * ld-elf/merge.d: Expect this test to pass on the MSP430. * ld-elf/sec64k.exp: Skip these tests for the MSP430. * ld-gc/pr13683.d: Expect this test to fail on the MSP430. * ld-srec/srec.exp: Expect these tests to fail on the MSP430. * ld-undefined/undefined.exp: Expect the UNDEFINED LINE test to fail on the MSP430. * msp430-dis.c: Add support for MSP430X instructions.
2013-04-06Increase the accuracy of sparc instruction aliases.David S. Miller2-0/+8
Make current with UA2011 specification. Add an F_PREFERRED opcode flag that indicates a preferred alias when multiple aliases for the same opcode exists. For 'lzd': Add 'lzcnt' as primary instruction, and make 'lzd' an alias. Add 'ldtw', 'ldtwa', 'sttw', 'sttwa': The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on integer registers. Mark the latter now as aliases. For 'flush': Support "[address]" syntax as well as plain "address". Rework 'mov' aliases for 'wr': Eliminate bogus three operand moves, and encode the instructions properly for the "mov REG, %ASR" cases, specifically we should encode the register in rs2 not rs1 as per The SPARC V8 Architecture Manual. Add missing cbcond aliases: c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu Add 'd' suffix VIS logical ops: The primary opcode for 'fzero' is now 'fzerod' (compare with 'fzeros'), for example. And thus 'fzero' is now an alias. Add modern opcodes for condition code setting edge instructions: They are now edgeN{,l}cc instead of plain edgeN{,l}. Add modern opcodes for VIS comparisons: All VIS comparisons now start with prefix "fp", retain the older variants as aliases. The signed variants for equal and not-equal have "u" aliases to show that these comparisons are equally suited for unsigned compares. Update existing test cases as needed, and add several new ones. include/opcode/ * sparc.h (F_PREFERRED): Define. (F_PREF_ALIAS): Define. opcodes/ * sparc-dis.c (compare_opcodes): When encountering multiple aliases of an opcode, prefer the one with F_PREFERRED set. * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa, lzcnt, flush with '[address]' syntax, and missing cbcond pseudo ops. Make 64-bit VIS logical ops have "d" suffix in their names, mark existing mnenomics as aliases. Add "cc" suffix to edge instructions generating condition codes, mark existing mnenomics as aliases. Add "fp" prefix to VIS compare instructions, mark existing mnenomics as aliases. gas/testsuite/ * gas/sparc/cbcond.s: Add tests for new opcode aliases. * gas/sparc/cbcond.d: Updated. * gas/sparc/hpcvis3.s: Add tests for new opcode aliases. * gas/sparc/hpcvis3.d: Updated. * gas/sparc/v8-movwr-imm.d: Fix expected disassembly. * gas/sparc/edge.s: New test. * gas/sparc/edge.d: Expected disassembly. * gas/sparc/flush.s: New test. * gas/sparc/flush.d: Expected disassembly. * gas/sparc/ldd_std.s: New test. * gas/sparc/ldd_std.d: Expected disassembly. * gas/sparc/ldtw_sttw.s: New test. * gas/sparc/ldtw_sttw.d: Expected disassembly. * gas/sparc/sparc.exp: Run new tests.
2013-04-03merge from gccDJ Delorie2-0/+13
2013-04-03 * elf32-v850.c (v850_elf_is_target_special_symbol): New function.Nick Clifton2-0/+7
(bfd_elf32_bfd_is_target_special_symbol): Define. * v850.h (V850_INVERSE_PCREL): Define. * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the destination address by subtracting the operand from the current address. * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store a positive value in the insn. (extract_u16_loop): Do not negate the returned value. (D16_LOOP): Add V850_INVERSE_PCREL flag. (ceilf.sw): Remove duplicate entry. (cvtf.hs): New entry. (cvtf.sh): Likewise. (fmaf.s): Likewise. (fmsf.s): Likewise. (fnmaf.s): Likewise. (fnmsf.s): Likewise. (maddf.s): Restrict to E3V5 architectures. (msubf.s): Likewise. (nmaddf.s): Likewise. (nmsubf.s): Likewise.
2013-03-28 PR binutils/15068Nick Clifton2-9/+14
* tic6x-opcode-table.h: Fix patterns for add, ldnw and xor. * gas/tic6x/insns16-lsd-unit.s: Correct bit patterns for mvk, add and xor. * gas/tic6x/insns16-lsd-unit.d: Update expected output.
2013-03-27 PR binutils/15068Nick Clifton4-10/+1659
* tic6x-dis.c: Add support for displaying 16-bit insns. * tic6xc-insn-formats.h (FLD): Add use of bitfield array. Add 16-bit opcodes. * tic6xc-opcode-table.h: Add 16-bit insns. * tic6x.h: Add support for 16-bit insns. * config/tc-tic6x.c (tic6x_try_encode): Add use of bitfields array. * gas/tic6x/insns16-d-unit.s: New test. * gas/tic6x/insns16-d-unit.d: Expected disassembly. * gas/tic6x/insns16-ddec.s: New test. * gas/tic6x/insns16-ddec.d: Expected disassembly. * gas/tic6x/insns16-dinc.s: New test. * gas/tic6x/insns16-dinc.d: Expected disassembly. * gas/tic6x/insns16-dind.s: New test. * gas/tic6x/insns16-dind.d: Expected disassembly. * gas/tic6x/insns16-doff4.s: New test. * gas/tic6x/insns16-doff4.d: Expected disassembly. * gas/tic6x/insns16-l-unit.s: New test. * gas/tic6x/insns16-l-unit.d: Expected disassembly. * gas/tic6x/insns16-lsd-unit.s: New test. * gas/tic6x/insns16-lsd-unit.d: Expected disassembly. * gas/tic6x/insns16-m-unit.s: New test. * gas/tic6x/insns16-m-unit.d: Expected disassembly. * gas/tic6x/insns16-s-unit-pcrel.s: New test. * gas/tic6x/insns16-s-unit-pcrel.d: Expected disassembly. * gas/tic6x/insns16-s-unit: New test. * gas/tic6x/insns16-s-unit.d: Expected disassembly.
2013-03-21 * elf32-h8300 (h8_relax_section): Add new relaxation of movNick Clifton4-10/+19
@(disp:32,ERx) to mov @(disp:16,ERx). (R_H8_DISP32A16): New reloc. Comments added and corrected. * reloc.c (BFD_RELOC_H8_DISP32A16): New reloc. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * ld.texinfo (H8/300): Add description of relaxation of mov @(disp:32,ERx) to mov @(disp:16,ERx). * ld-h8300/h8300.exp: Add new relax-7 test on ELF. * ld-h8300/relax-2.s: Add other direction and .w/.l variants of mov insns. * ld-h8300/relax-2.d: Update expected disassembly. * ld-h8300/relax-7a.s: New: tests for mov @(disp:32,ERx) -> mov @(disp:16,ERx). * ld-h8300/relax-7b.s: New: Likewise. * ld-h8300/relax-7.d: New: expected disassembly. * config/tc-h8300.c (do_a_fix_imm): Add relaxation of mov @(disp:32,ERx) to mov @(disp:16,ERx) insns by new reloc R_H8_DISP32A16. * config/tc-h8300.h: Remove duplicated defines.
2013-03-20 PR gas/15082Nick Clifton2-7/+17
* tic6x-opcode-table.h: Rename mpydp's specific operand type macro from ORREGD1324 to ORXREGD1324 and make it cross-path-able through tic6x_operand_xregpair operand coding type. Make mpydp instruction cross-path-able, ie: remove the FIXed 'x' opcode field, usu ORXREGD1324 for the src2 operand and remove the TIC6X_FLAG_NO_CROSS. * gas/tic6x/insns-bad-1.s: Remove test-case for mpydp with cross-path. * gas/tic6x/insns-bad-1.l: Update expected output. * gas/tic6x/insns-c674x.s: Add a test-case for mpydp with cross-path. * gas/tic6x/insns-c674x.d: Update expected output.
2013-03-20* include/opcode/tic6x.h: add tic6x_coding_dreg_(msb|lsb) field coding type inNick Clifton3-16/+36
order to encode separately the msb and lsb of a register pair ; this will be needed to encode the opcodes the same way as Ti assembler does. * gas/config/tc-tic6x.c: handle tic6x_coding_dreg_(msb|lsb) field coding types and use it to encode register pair numbers when required. * opcodes/tic6x-dis.c: decodes opcodes that have individual msb and lsb halves in src1 & src2 fields ; discard the src1 (lsb) value and only use src2 (msb), discarding bit 0, to follow what Ti SDK does in that case as any value in the src1 field yields the same output with SDK disassembler. * include/opcode/tic6x-opcode-table.h: modify absdp, dpint, dpsp, dptrunc, rcpdp and rsqrdp opcodes to use the new field coding types. * gas/testsuite/gas/tic6x/insns-c674x.d, gas/testsuite/gas/tic6x/insns-c674x.s : add test case for the newly generated opcode but keep the old ones as they seem legit as per Ti disassembler output.
2013-03-15gdb:Steve Ellcey2-1/+5
2013-03-15 Steve Ellcey <sellcey@mips.com> * remote-sim.c (sim_command_completer): Make char arguments const. include: 2013-03-15 Steve Ellcey <sellcey@mips.com> * gdb/remote-sim.h (sim_command_completer): Make char arguments const. sim: 2013-03-15 Steve Ellcey <sellcey@mips.com> * arm/wrapper.c (sim_complete_command): Make char arguments const. * avr/interp.c (sim_complete_command): Ditto. * common/sim-options.c (sim_complete_command): Ditto. * cr16/interp.c (sim_complete_command): Ditto. * erc32/interf.c (sim_complete_command): Ditto. * m32c/gdb-if.c (sim_complete_command): Ditto. * microblaze/interp.c (sim_complete_command): Ditto. * ppc/sim_calls.c (sim_complete_command): Ditto. * rl78/gdb-if.c (sim_complete_command): Ditto. * rx/gdb-if.c (sim_complete_command): Ditto. * sh/interp.c (sim_complete_command): Ditto.
2013-03-122013-03-12 Sebastian Huber <sebastian.huber@embedded-brains.de>gdb_7_6-branchpointSandra Loosemore2-3/+8
include/ * opcode/nios2.h: Edit comment. gas/ * config/tc-nios2.c (nios2_consume_arg): Delete 'k' case. Add 'o' case. Add default BAD_CASE to switch. gas/testsuite/ * gas/nios2/break.d: Check instruction values.
2013-03-122013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>Sandra Loosemore2-0/+7
include/ * opcode/nios2.h (OPX_WRPRS): New define. (OP_MATCH_WRPRS): Likewise. opcodes/ * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs. gas/ * config/tc-nios2.c (nios2_assemble_args_ds): New function. (nios2_arg_info_structs): Add "d,s" and "d,s,E" entries. gas/testsuite/ * gas/nios2/nios2.exp: Run wrprs. * gas/nios2/wrprs.d: New file. * gas/nios2/wrprs.s: Likewise.
2013-03-122013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>Sandra Loosemore2-0/+7
include/ * opcode/nios2.h (OP_RDPRS): New define. (OP_MATCH_RDPRS): Likewise. opcodes/ * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs. gas/testsuite/ * gas/nios2/nios2.exp: Run rdprs. * gas/nios2/rdprs.d: New file. * gas/nios2/rdprs.s: Likewise.
2013-03-11Add support for AArch32 CRC instruction in ARMv8.Kyrylo Tkachov2-0/+7
gas/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-arm.c (crc_ext_armv8): New feature set. (UNPRED_REG): New macro. (do_crc32_1): New function. (do_crc32b, do_crc32h, do_crc32w, do_crc32cb, do_crc32ch, do_crc32cw): Likewise. (TUEc): New macro. (insns): Add entries for crc32 mnemonics. (arm_extensions): Add entry for crc. include/opcode/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * arm.h (CRC_EXT_ARMV8): New constant. (ARCH_CRC_ARMV8): New macro. opcodes/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * arm-dis.c (arm_opcodes): Add entries for CRC instructions. (thumb32_opcodes): Likewise. (print_insn_thumb32): Handle 'S' control char. gas/testsuite/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * gas/arm/crc32-bad.d: New file. * gas/arm/crc32-bad.l: Likewise. * gas/arm/crc32-bad.s: Likewise. * gas/arm/crc32.d: Likewise. * gas/arm/crc32.s: Likewise.
2013-03-08 * elf-bfd.h (elfcore_write_s390_tdb): Add prototype.Nick Clifton2-4/+7
* elf.c (elfcore_write_s390_tdb): New function. (elfcore_write_register_note): Call it. (elfcore_grok_s390_tdb): New function. (elfcore_grok_note): Call it. * readelf.c (get_note_type): Add NT_S390_TDB.
2013-03-01Restore patch lost in last merge from GCC.Cary Coutant1-0/+14
include/ * dwarf2.h (enum dwarf_sect): New enum type.
2013-03-01merge from gccDJ Delorie1-14/+0
2013-03-01include/Cary Coutant2-0/+18
* dwarf2.h (enum dwarf_sect): New enum type.
2013-02-28include/opcode/Yufeng Zhang2-0/+5
* aarch64.h (AARCH64_FEATURE_CRC): New macro. opcodes/ * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros. (aarch64_feature_crc): New static. (CRC): New macro. (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w, crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions. * aarch64-asm-2.c: Re-generate. * aarch64-dis-2.c: Ditto. * aarch64-opc-2.c: Ditto. gas/ * config/tc-aarch64.c (aarch64_features): Add the 'crc' option. gas/testsuite/ * gas/aarch64/crc32.s: New test. * gas/aarch64/crc32.d: Ditto.
2013-02-18include/Alan Modra2-8/+8
* bfdlink.h (struct bfd_link_info): Delete emit_note_gnu_build_id. bfd/ * configure.in: Bump version to 2.23.52. * elf-bfd.h (struct elf_build_id_info): New. (struct elf_obj_tdata): Delete after_write_object_contents, after_write_object_contents_info and build_id_size. Make build_id a pointer to struct elf_build_id_info. * elf.c (_bfd_elf_write_object_contents): Style. Update after_write_ibject_contents invocation. (elfobj_grok_gnu_build_id): Update for new build_id struct. Don't allow zero size notes. * configure: Regenerate. gdb/ * elfread.c (struct build_id): Delete. Use struct elf_build_id throughout file instead. (build_id_bfd_get): Update to use new elf_tdata build_id field. Don't xmalloc return value. (build_id_verify): Similarly. Don't xfree. (build_id_to_debug_filename): Update. (find_separate_debug_file_by_buildid): Update, don't xfree. ld/ * emultempl/elf32.em (emit_note_gnu_build_id): New static var. Replace all info->emit_note_gnu_build_id refs. (id_note_section_size): Rename from gld${EMULATION_NAME}_id_note_section_size. (struct build_id_info): Delete. (write_build_id): Rename from gld${EMULATION_NAME}_write_build_id_section. Update elf_tdata usage. Style, formatting. (setup_build_id): New function. (gld${EMULATION_NAME}_after_open): Use setup_build_id.
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