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2017-04-11Reorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500Alan Modra2-43/+48
2017-04-11Bye bye PPC_OPCODE_HTM and -mhtmAlan Modra2-5/+1
2017-04-11Bye Bye PPC_OPCODE_VSX3Alan Modra2-3/+1
2017-04-11Bye bye PPC_OPCODE_ALTIVEC2Alan Modra2-3/+4
2017-04-06Add support for disassembling WebAssembly opcodes.Pip Cet2-0/+7
2017-04-05-Wwrite-strings: Constify struct disassemble_info's disassembler_options fieldPedro Alves2-4/+10
2017-04-04Support ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXXH.J. Lu2-0/+14
2017-04-04RISC-V: Resurrect GP-relative disassembly hintsPalmer Dabbelt2-0/+7
2017-03-31RISC-V: Add physical memory protection CSRsAndrew Waterman2-0/+83
2017-03-30Add support for the WebAssembly file format and the wasm32 ELF conversion to ...Pip Cet3-0/+233
2017-03-29PowerPC -Mraw disassemblyAlan Modra2-37/+48
2017-03-27Add minimal support for WebAssembly backend to the BFD library.Pip Cet2-0/+32
2017-03-27Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.Rinat Zelig2-6/+12
2017-03-21S/390: Remove vx2 facility flagAndreas Krebbel2-2/+6
2017-03-21arc/nps400: Add cp16/cp32 instructions to opcodes libraryRinat Zelig2-0/+5
2017-03-16Add support for a GNU BUILD note type to record the enum size.Nick Clifton2-0/+6
2017-03-14Add DW_OP_GNU_variable_valueH.J. Lu2-0/+8
2017-03-13Sync libiberty sources with GCC.Nick Clifton2-2/+16
2017-03-13Rename R_AARCH64_TLSDESC_LD64_LO12_NC to R_AARCH64_TLSDESC_LD64_LO12 and R_AA...Nick Clifton2-2/+10
2017-03-10Add basic recognition of new EM_ ELF machine numbers.Nick Clifton2-18/+20
2017-03-08Properly dump NT_GNU_PROPERTY_TYPE_0H.J. Lu2-0/+18
2017-03-01Add support for displaying and merging GNU_BUILD_NOTEs.Nick Clifton2-0/+88
2017-02-28GDB: Add support for the new set/show disassembler-options commands.Peter Bergner2-4/+53
2017-02-28PowerPC addpcis fixAlan Modra3-2/+15
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford2-0/+13
2017-02-24[AArch64] Add a "compnum" featureRichard Sandiford2-1/+8
2017-02-24Add new counter-enable CSRsAndrew Waterman2-0/+11
2017-02-23S/390: Add support for new cpu architecture - arch12.Andreas Krebbel1-1/+4
2017-02-23opcodes,gas: associate SPARC ASIs with an architecture level.Sheldon Lobo1-1/+9
2017-02-15Add SFENCE.VMA instructionAndrew Waterman2-0/+9
2017-02-14PowerPC register expression checksAlan Modra2-70/+84
2017-02-06[ARC] Provide an interface to decode ARC instructions.Claudiu Zissulescu1-1/+23
2017-01-25Clarify that include/opcode/ files are part of GNU opcodesDimitar Dimitrov7-6/+15
2017-01-25Fix include/ChangeLog entry formatPedro Alves1-1/+1
2017-01-24[PATCH] Add NT_ARM_SVEAlan Hayward2-0/+6
2017-01-04[DWARF] Sync GCC dwarf.def change on AArch64Jiong Wang2-1/+18
2017-01-04[AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy2-1/+8
2017-01-03Add support for the Q extension to the RISCV ISA.Kito Cheng3-0/+108
2017-01-03Sync dwarf headers with master versions in gcc repository.Nick Clifton3-18/+213
2017-01-02Update year range in copyright notice of all files.Alan Modra300-299/+303
2017-01-02ChangeLog rotationAlan Modra2-829/+843
2017-01-01update copyright year range in GDB filesJoel Brobecker22-22/+22
2016-12-31PRU BFD supportDimitar Dimitrov5-1/+475
2016-12-23MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki2-2/+13
2016-12-23MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki2-5/+10
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki2-0/+8
2016-12-21Remove high bit set charactersAlan Modra3-9/+14
2016-12-20MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki2-0/+12
2016-12-20Re-work RISC-V gas flags: now we just support -mabi and -marchAndrew Waterman2-2/+21
2016-12-20Rework RISC-V relocationsAndrew Waterman2-0/+13
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