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2021-10-28RISC-V/SiFive: Added SiFive custom cache control instructions.users/riscv/binutils-integration-branchNelson Chu2-0/+16
According to the chapter 10 of the following U74-MC manual, https://sifive.cdn.prismic.io/sifive/6d9a2510-2632-44f3-adb9-d0430f139372_sifive_coreip_U74MC_AXI4_rtl_v19_08p2p0_release_manual.pdf and the implementations of freedom-metal, https://github.com/sifive/freedom-metal/blob/v201908-branch/src/cache.c * Encodings, 31-25 24-20 19-15 14-12 11-7 6-0 FUNCT7 RS2 RS1 FUNCT3 RD OPCODE 1111110 00000 xxxxx 000 00000 1110011 CFLUSH.D.L1 1111110 00010 xxxxx 000 00000 1110011 CDISCARD.D.L1 1111110 00001 00000 000 00000 1110011 CFLUSH.I.L1 * Extension names, xsfcflushdlone: CFLUSH.D.L1. xsfcdiscarddlone: CDISCARD.D.L1. xsfcflushilone: CFLUSH.I.L1. * Vendor target triples, For assembler, the target vendor is defined as TARGET_VENDOR in the gas/config.h, but I don't see any related settings in bfd/config.h and opcode/config. Since we may have vendor relocations in the future, and these relocation numbers may repeat, I add a new RISCV_TARGET_VENDOR in the bfd/config.h for riscv. The vendor name will be stored in the bfd/cpu-riscv.c, so that all tools (gas, bfd, opcode, ...) can get the vendor name from the configure setting. If the --with-arch configure option, -march gas option and elf architecture attributes are not set, then we will generate the default ISA string according to the chosen target vendor. For example, if you build the binutils with the configure option, --target=riscv64-sifive-elf, then the assembler will find the whole supported extension tables in the bfd/elfxx-riscv.c, and generate the suitable ISA string. bfd/ * configure.ac (RISCV_TARGET_VENDOR): Defined to store target_vendor, only when the target is riscv*. * config.in: Regenerated. * configure: Regenerated. * cpu-riscv.c (riscv_vendor_name): Defined to RISCV_TARGET_VENDOR. * cpu-riscv.h (enum riscv_spec_class): Added VENDOR_SPEC_CLASS_SIFIVE. * elfxx-riscv. (EXT_SIFIVE): Defined to choose the default extensions for sifive. (riscv_supported_vendor_sifive_ext): Added extensions for sifive cache control instructions. (riscv_supported_std_ext, riscv_all_supported_ext): Updated. (riscv_get_default_ext_version): Updated. (riscv_set_default_arch): Updated. gas/ * config/tc-riscv.c (VENDOR_SIFIVE_EXT): Added. (riscv_extended_subset_supports): Handle INSN_CLASS_XSF*. (op_vendor_sifive_hash): Added to store sifive opcodes. (md_begin): Init the op_vendor_sifive_hash. (riscv_find_extended_opcode_hash): Find the opcodes from op_vendor_sifive_hash. * testsuite/gas/riscv/extended/sifive-insns.d: New testcase. * testsuite/gas/riscv/extended/sifive-insns.s: Likewise. include/ * opcode/riscv-opc-extended.h: Added opcodes for sifive cache instructions. * opcode/riscv.h (enum riscv_extended_insn_class): Added INSN_CLASS_XSF*. opcodes/ * riscv-opc.c (riscv_vendor_sifive_opcodes): Added. (riscv_extended_opcodes): Updated.
2021-10-28RISC-V/rvv: Added zve* and zvl* extensions, and clarify the imply rules.Nelson Chu1-0/+2
* Recognized zve* and zvl* extensions. - zve*: zve64d, zve64f, zve64x, zve32f and zve32x. - zvl*: zvl32b, zvl64b, zvl128b, zvl256b, zvl512b, zvl1024b, zvl2048b, zvl4096b, zvl8192b, zvl16384b, zvl32768b and zvl65536b. * Spec said that v requires f and d, zve64d requires d, zve64f and zve32f require f. However, according to the issue 723, [https://github.com/riscv/riscv-v-spec/issues/723] The general rule is that extension names imply the things they require. Therefore, the current imply rules should be as follows, - v imply f and d. - zve64d imply d. - zve64f and zve32f imply f. - zvamo imply a. Besides, consider the implicit zve and zvl extensions, - v imply zve64d and zvl128b. - zve64* imply the corresponding zve32*. For example, zve64f imply zve32f, and zve64x imply zve32x. - zve*d imply zve*f and zve*x. For example, zve64d imply zve64f and zve64x. - zve*f imply zve*x. For example, zve64f imply zve64x. - zve64* imply zvl64b, and zve32* imply zvl32b. - The larger zvl* imply all smaller zvl*. For example, zvl128b imply zvl64b, and zvl32b. Therefore, "-march=rv64iv -misa-spec=20191213" will be "rv64i2p0_f2p0_d2p0_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0". Note: zicsr is the imply extension of f. * For zve32x, the (segmant) load/store instructions are illegal when EEW is 64. Besides, vsew cannot be set to 64 by vsetvli when zve32* is enabled. * For zvl*b extensions, we also need to enable either v or zve* extensions. Otherwise we should issue errors. bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Added imply rules for v, zve* and zvl*b extensions. (riscv_supported_std_z_ext): Added zve* and zvl*b extensions. (riscv_parse_check_conflicts): The zvl*b extensions cannot be set without v and zve* extensions. gas/ * config/tc-riscv.c (riscv_extended_subset_supports): Handle zve*. (my_getVsetvliExpression): vsew cannot be set to 64 by vsetvli when zve32* is enabled. (riscv_ip): The (segmant) loads and stores with EEW 64 cannot be used when zve32x is enabled. * testsuite/gas/riscv/extended/march-imply-v.d: New testcase. * testsuite/gas/riscv/extended/march-imply-zve*.d: Likewise. * testsuite/gas/riscv/extended/march-imply-zvl*b.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-zve32x.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-zve32x.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-zve32x.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-zvl.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-zvl.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d: Removed a-ext from -march since it will be added as implicit ext for zvamo. * testsuite/gas/riscv/extended/vector-insns.d: Likewise. include/ * opcode/riscv.h: Defined INSN_V_EEW64. opcodes/ * riscv-opc.c (riscv_draft_opcodes): Added INSN_V_EEW64 for vector loads and stores when the eew encodings are 64.
2021-10-28RISC-V/rvv: Separate zvamo from v, and removed the zvlsseg extension name.Nelson Chu1-2/+1
* Separate zvamo from v extension with v1.0, but keep the implementations. * Removed zvlsseg extension name as the vector segmant loads and stores are required (included) in v extension. * Updated the versions of v and zvamo from draft v0.10 to frozen v1.0. bfd/ * elfxx-riscv.c (riscv_supported_std_z_ext): Removed entry of zvlsseg. gas/ * config/tc-riscv.c (riscv_extended_subset_supports): Changed INSN_CLASS_V_OR_ZVAMO to INSN_CLASS_ZVAMO, and removed INSN_CLASS_V_OR_ZVLSSEG. (riscv_extended_csr_class_check): Updated since the name zvlsseg is removed. * testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d: Changed -march from rv32iav to rv32ia_zvamo. * testsuite/gas/riscv/extended/vector-insns.d: Changed -march from rv32iafv to rv32iafv_zvamo. include/ * opcode/riscv.h (riscv_extended_insn_class): Changed INSN_CLASS_V_OR_ZVAMO to INSN_CLASS_ZVAMO, and removed INSN_CLASS_V_OR_ZVLSSEG. opcodes/ * riscv-opc.c (riscv_draft_opcodes): Changed INSN_CLASS_V_OR_ZVAMO to INSN_CLASS_ZVAMO since they are separated from v. Also changed INSN_CLASS_V_OR_ZVLSSEG to INSN_CLASS_V as they are included in v.
2021-10-28RISC-V/rvv: Added assembly pseudo and changed assembler mnemonics.Nelson Chu1-14/+14
* Added pseudo instruction, - vfabs.v vd,vs = vfsgnjx.vv vd,vs,vs * Changed assembler mnemonics, and the older names kept as aliases, - Changed from vle1.v to vlm.v, and vse1.v to vsm.v. - Changed from vfredsum and vfwredsum to vfredusum and vfwredusum respectively. - Changed from vpopc.m to vcpop.m, to be consistent with scalar instruction. - Changed from vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm. gas/ * testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.l: Updated. * testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-vmsgtvx.d: Likewise. * testsuite/gas/riscv/extended/vector-insns.d: Likewise. * testsuite/gas/riscv/extended/vector-insns.s: Likewise. include/ * opcode/riscv-opc-extended.h: Updated. opcodes/ * riscv-opc.c: Added pseudo vfabs.v, and changed assembler mnemonics.
2021-10-28RISC-V/t-head: Add CSRs and opcodes of the T-HEAD XUANTIE CPUsLifang Xia2-0/+581
Add CSRs and opcodes of the XUANTIE CPUs, extensions named "theadc", "xtheade" and "xtheadse". New ARG format for operands: "Xgm@n": encode GPR with m bit at opcode[m+n-1:n]. "Xg5@0": encode GPR with 5 bit at opcode[4:0]. "Xg5@8": encode GPR with 5 bit at opcode[12:8]. "XIm@n": m bits unsigned immediate at opcode[m+n-1:n]. "XI5@0": 5 bits unsigned immediate at opcode[4:0]. "XI4@8": 4 bits unsigned immediate at opcode[11:8]. "XSm@n": m bits signed immediate at opcode[m+n-1:n]. "XS5@0": 5 bits signed immediate at opcode[4:0]. "XS4@8": 4 bits signed immediate at opcode[11:8]. "XFm@n": m bits FR at opcode[m+n-1:n]. "XF5@0": 5 bits FR at opcode[4:0]. "XF5@0": 5 bits FR at opcode[4:0]. bfd/ * cpu-riscv.h (enum riscv_spec_class) <VENDOR_SPEC_CLASS_THEAD>: New. * elfxx-riscv.c (riscv_supported_vendor_thead_ext): New. (riscv_all_supported_ext): Updated. (riscv_get_default_ext_version): Updated. gas/ * config/tc-riscv.c (VENDOR_THEAD_EXT): New. (enum riscv_extended_csr_class) <CSR_CLASS_VENDOR_THEAD>: New. (riscv_extended_subset_supports): Check subset: INSN_CLASS_THEAD* (op_vendor_thead_hash): New, the hash of T-HEAD Xuantie's opcodes. (riscv_csr_address): Skip check version for T-HEAD Xuantie CPUs. (validate_riscv_extended_insn): Parsing T-HEAD opargs. (md_begin): Init op_vendor_thead_hash. (riscv_find_extended_opcode_hash): Search op_vendor_thead_hash. (riscv_parse_extended_operands): Parsing T-HEAD opargs. * testsuite/gas/riscv/extended/thead*: New testcases. include/ * opcode/riscv-opc-extended.h: Add CSRs and opcode of the T-HEAD XUANTIE CPUs. * opcode/riscv.h (riscv_extended_insn_class) <INSN_CLASS_THEADC>: New. <INSN_CLASS_THEADC_OR_THEADE>: New. <INSN_CLASS_THEADC_OR_THEADE_OR_THEADSE>: New. <INSN_CLASS_THEADE>: New. <INSN_CLASS_THEADSE>: New. (*VENDOR_THEAD_*): T-HEAD IMM encoding. opcodes/ * riscv-dis.c (print_extended_insn_args): Parsing T-HEAD opargs. * riscv-opc.c (match_thead_rd1_rd2_neq_rs1): New. (riscv_vendor_thead_opcodes): New. (riscv_extended_opcodes): Add riscv_vendor_thead_opcodes.
2021-10-28RISC-V: Support svinval extensions.Nelson Chu2-0/+17
https://github.com/riscv/riscv-isa-manual/pull/668/files There are five new instructions for svinval extension. According to the above draft spec, two of them (HINVAL.VVMA and HINVAL.GVMA) need to enable the hypervisor extension. But there is no implementation of hypervisor extension in mainline, so let's consider the related issues later. 31..25 24..20 19..15 14..12 11...7 6..2 1..0 sinval.vma 0001011 rs2 rs1 000 00000 11100 11 sfence.w.inval 0001100 00000 00000 000 00000 11100 11 sfence.inval.ir 0001100 00001 00000 000 00000 11100 11 hinval.vvma 0011011 rs2 rs1 000 00000 11100 11 hinval.gvma 0111011 rs2 rs1 000 00000 11100 11 bfd/ * elfxx-riscv.c (riscv_supported_std_s_ext): Added svinval. gas/ * config/tc-riscv.c (riscv_extended_subset_supports): Handle INSN_CLASS_SVINVAL. * testsuite/gas/riscv/extended/extended.exp: Updated. * testsuite/gas/riscv/extended/svinval.d: Mew testcases. * testsuite/gas/riscv/extended/svinval.s: Likewise. include/ * opcode/riscv-opc-extended.h: Added encodings for svinval. * opcode/riscv.h (riscv_extended_insn_class): Added INSN_CLASS_SVINVAL. opcodes/ * riscv-opc.c (riscv_draft_opcodes): Added svinval instructions.
2021-10-28RISC-V/zfh: Add half-precision floating-point v0.1 instructions.Nelson Chu2-0/+116
This patch is porting from the following riscv github, https://github.com/riscv/riscv-binutils-gdb/commits/rvv-1.0.x-zfh And here is the draft zfh spec, https://github.com/riscv/riscv-isa-manual/tree/zfh bfd/ * elfxx-riscv.c (riscv_supported_std_z_ext): Added zfh. (riscv_implicit_subset): Add implicit f and zicsr for zfh. gas/ * config/tc-riscv.c (riscv_extended_subset_supports): Handle INSN_CLASS*_ZFH. (extended_macro): Handle M_FLH and M_FSH. * testsuite/gas/riscv/extended/extended.exp: Updated. * testsuite/gas/riscv/extended/fp-zfh-insns.d: New testcase. * testsuite/gas/riscv/extended/fp-zfh-insns.s: Likewise. include/ * opcode/riscv-opc-extended.h: Added zfh encoding macros and DECLARE_INSN. * opcode/riscv.h (enum riscv_extended_insn_class): Added INSN_CLASS*_ZFH. (enum M_FLH, M_FSH): Added. opcodes/ * riscv-opc.c (riscv_draft_opcodes): Added zfh instructions.
2021-10-28RISC-V/rvv: Add rvv v0.10 instructions.Nelson Chu2-1/+1448
2021-03-30 Jim Wilson <jimw@sifive.com> Kito Cheng <kito.cheng@sifive.com> Nelson Chu <nelson.chu@sifive.com> This patch is porting from the following riscv github, https://github.com/riscv/riscv-binutils-gdb/tree/rvv-1.0.x And here is the vector draft spec, https://github.com/riscv/riscv-v-spec The match_func in opcodes/riscv-opc.c have many purposes. One of them is checking the instruction constraints. But we got the request before that the assembler constraint checkings break some hardware exception testcases, which are written by assmebly code. Therefore, we add new assembler options and .option directives to let users can disable/enable the rvv constraints. For now the constraints are disabled by default, but should we default enable them for safety? Besides, the match_func will return different error constriant messages, so that we can report the details to users. This should be more user-friendly. bfd/ * elfxx-riscv.c (riscv_supported_std_ext): Updated the draft version of v. (riscv_supported_std_z_ext): Added draft zvamo and zvlsseg. gas/ * config/tc-riscv.c (enum DRAFT_EXT): Added. (enum riscv_extended_csr_class): Added CSR_CLASS_V for rvv CSRs. (enum reg_extended_class): Added vector registers. (op_draft_hash): Added draft hash table for rvv. (md_begin): Init op_draft_hash and register hash for rvv. (riscv_extended_subset_supports): Handle INSN_CLASS_V*. (riscv_extended_csr_class_check): Handle CSR_CLASS_V. (validate_riscv_extended_insn): Check if the rvv instructions are valid. (riscv_find_extended_opcode_hash): Search instruction opcode from op_draft_hash. (vector_macro): Call macro_build to expand rvv macros into instructions. (extended_macro_build): Handle rvv operands for macro_build. (extended_macro): Handle M_VMSGE and M_VMSGEU. (my_getVsetvliExpression): Similar to my_getVsetvliExpression, but used for parsing vsetvli operands. (riscv_parse_extended_operands): Handle rvv operands. Pass &regno from riscv_ip, otherwise we will get fail when parsing Vf operand for AMO VS3. (riscv_ip): Add two new arguments to match_func, check_constraints and &error. We can disbale the match_func check by setting check_constraints to zero; The part of match_func will set different error messages to the &error, and them we can report more details to users. (riscv_set_options, riscv_opts, s_riscv_option): Add .option checkconstraints and nocheckconstraints, to enable/disable the match_func constraints checking. Disable it by default. (enum options, md_longopts, md_parse_option): Add assembler options m[no-]check-constraints. * testsuite/gas/riscv/extended/extended.exp: Updated. * testsuite/gas/riscv/extended/extended-csr.d: New testcase for rvv CSRs. * testsuite/gas/riscv/extended/extended-csr.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-fixp.d: New testcase for rvv constriants. * testsuite/gas/riscv/extended/vector-insns-fail-arith-fixp.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-fixp.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-int.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-int.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-int.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-load-store.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-load-store.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-load-store.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-mask.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-mask.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-mask.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-permutation.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-permutation.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-permutation.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-zvamo.l: Likewise. * testsuite/gas/riscv/extended/vector-insns-fail-zvamo.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-vmsgtvx.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-vmsgtvx.s: Likewise. * testsuite/gas/riscv/extended/vector-insns-zero-imm.d: Likewise. * testsuite/gas/riscv/extended/vector-insns-zero-imm.s: Likewise. * testsuite/gas/riscv/extended/vector-insns.d: Likewise. * testsuite/gas/riscv/extended/vector-insns.s: Likewise. include/ * opcode/riscv-opc-extended.h: Added rvv encoding macros and CSRs. * opcode/riscv.h: Added rvv immediate encodings and fields. (struct riscv_opcode): Updated match_func. (enum riscv_extended_insn_class): Added INSN_CLASS_V*. (enum M_VMSGE, M_VMSGEU): Added. opcodes/ * riscv-dis.c (print_extended_insn_args): Handle rvv operands. (riscv_disassemble_opcode): Updated match_func. * riscv-opc.c (match_*): Updated since two new parameters. (riscv_vecr_names_numeric): Added rvv register names. (riscv_vecm_names_numeric): Added rvv mask register name. (riscv_vsew, riscv_vlmul, riscv_vta, riscv_vma): Added for vsetvli. (MASK_VD, MASK_VS1, MASK_VS2, MASK_VMASK): Added for rvv match_func. (match_vs1_eq_vs2, match_vs1_eq_vs2_neq_vm, match_vd_eq_vs1_eq_vs2): Added to check special register usage, cannot be disabled. (match_widen_vd_neq_vs1_neq_vs2_neq_vm): The rvv constraint check, can be disabled/enabled by m[no-]check-constraints or .option [no]checkconstraints. (match_widen_vd_neq_vs1_neq_vm): Likewise. (match_widen_vd_neq_vs2_neq_vm): Likewise. (match_widen_vd_neq_vm): Likewise. (match_narrow_vd_neq_vs2_neq_vm): Likewise. (match_vd_neq_vs1_neq_vs2): Likewise. (match_vd_neq_vs1_neq_vs2_neq_vm): Likewise. (match_vd_neq_vs2_neq_vm): Likewise. (match_vd_neq_vm): Likewise. (match_vls_nf_rv): Likewise. (match_vmv_nf_rv): Likewise. (riscv_draft_opcodes): Added rvv v0.10 instructions. (riscv_extended_opcodes): Updated.
2021-10-28RISC-V/extended: Add assembler and dis-assembler hooks for extended extensions.Nelson Chu2-3/+30
To keep the original functions clean, we try to provide assembler and dis-assembler hooks as enough as possible for extended extensions. We probably need to add more once they are not enough in the future. However, there are several changes that might need to be discussed as follows, * Change the type of enums to int directly, to extend them for extended extensions. Not sure if the change is good enough, but it should be the easiler way to extend enums. * The extended operands should be parsed in the extended hooks, validate_riscv_extended_insn and riscv_parse_extended_operands. Obviously, we may need to reparse the opernad string in the extended hooks, when the original functions cannot recognize them. But the original functions have already pointed the parsed poniter to the next characters. Therefore, we should use a new pointer, opargStart, to record the position before parsing, and then pass it to the hooks when we need to reparse the extended operands. * Part of the "internal: unknown" errors are reported in the extended hooks rather than the original functions. For example, we used to report the "internal: unreachable" in the riscv_multi_subset_supports, to tell developers that they forgot to handle the new defined INSN_CLASS_. And the function returns TRUE/FALSE if the instruction is allowed or not according to the architecture string. The riscv_extended_subset_supports is the extended hook of riscv_multi_subset_supports, so it also returns a bfd_boolean to check the same thing. But it is hard to know if the INSN_CLASS_* is unknown from the same returned bfd_boolean, unless we add another new flag, or we just move the error report to the hook directly. I choose the latter for now, but it may cause the code of mainline and integration branches are inconsistent, which may affect the difficulty of the regular merge between these two branches. The same inconsistent problem also happens in riscv_parse_extended_operands. The hook only parse an operand rather than all, so it just has a switch without a for loop. We used to set "continue" to skip the loop in the switch, but the extended hook doesn't need the "continue". Perhaps we should use a single while/for in the hooks to keep the code consistent, then the regular merge may be more easiler. * Rename the variables to the more meaningful names in the riscv_ip, validate_riscv_insn and print_insn_args. - oparg: Renamed from args, means the arguments in the opcode table. - opargStart: Added to record the start of the argument. - asarg: Renamed from s, means the arguments of assembly string. - asargStart: Renamed from argsStart. * Extract the part that parsing the instruction opcode from the riscv_disassemble_insn, since we will need to call it for many times to search multiple opcode tables. gas/ * config/tc-riscv.c (enum EXTENDED_EXT_NUM): Added to choose the right extended opcode hashes in the riscv_find_extended_opcode_hash. (enum riscv_csr_class): Added CSR_CLASS_EXTENDED. (enum reg_class): Added RCLASS_EXTENDED_NUM. (enum reg_extended_class): Added to define extended registers. (struct riscv_csr_extra): Changed enum riscv_csr_class to int, to increase the expandability of enum. (riscv_init_csr_hash): Likewise. (riscv_find_opcode_hash): Handle more than one opcode hashes. (md_begin): Included riscv-opc-extended.h to define extended CSR. (init_ext_version_hash): Updated. (riscv_get_default_ext_version): Likewise. (md_assemble): Likewise. (s_riscv_insn): Likewsie. (riscv_after_parse_args): Likewise. (riscv_find_extended_opcode_hash): Extended hook for riscv_find_opcode_hash. (riscv_extended_subset_supports): Extended hook for riscv_multi_subset_supports. (riscv_extended_csr_class_check): Extended hook for riscv_csr_address, to check the CSR ISA dependency. (extended_macro): Extended hook for macro. (validate_riscv_extended_insn): Extended hook for validate_riscv_insn. (extended_macro_build): Extended hook for macro_build. (riscv_parse_extended_operands): Extended hook for riscv_ip. (riscv_multi_subset_supports): Updated to call extended hook. (riscv_csr_address): Likewise (macro): Likewise. (validate_riscv_insn): Likewise. Also define new variables, xxx and xxxStart, in case single letters are not enough to represent all extended operands. (macro_build): Likewise. (riscv_ip): Likewise. The asarg means assembly operand string, and oparg means operand string defined in the opcode table. * testsuite/gas/riscv/extended/extended.exp: New file to run extended testcases. include/ * opcode/riscv-opc-extended.h: New file to define encoding macros and CSR for extended extensions. * opcode/riscv.h: Included riscv-opc-extended.h. (enum riscv_insn_class): Added INSN_CLASS_EXTENDED. (struct riscv_opcode): Same as struct riscv_csr_extra. (enum M_EXTENDED): Added to support extended pseudo macros. opcode/ * riscv-dis.c (print_extended_insn_args): Extended hook for print_insn_args. (print_insn_args): Updated to call extended hook, and same as what validate_riscv_insn does. Also include riscv-opc-extended.h to show extended CSR correctly. * riscv-opc.c (riscv_extended_opcodes): Added to store all supported extended instruction opcodes.
2021-10-24LoongArch opcodes supportliuzhensong2-0/+240
2021-10-22 Chenghua Xu <xuchenghua@loongson.cn> Zhensong Liu <liuzhensong@loongson.cn> Weinan Liu <liuweinan@loongson.cn> include/ * opcode/loongarch.h: New. * dis-asm.h: Declare print_loongarch_disassembler_options. opcodes/ * Makefile.am: Add LoongArch. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Declare print_insn_loongarch. * loongarch-coder.c: New. * loongarch-dis.c: New. * loongarch-opc.c: New. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
2021-10-24LoongArch bfd supportliuzhensong2-1/+130
2021-10-22 Chenghua Xu <xuchenghua@loongson.cn> Zhensong Liu <liuzhensong@loongson.cn> Weinan Liu <liuweinan@loongson.cn> bfd/ * Makefile.am: Add LoongArch. * archures.c: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * cpu-loongarch.c: New. * elf-bfd.h: Add LoongArch. * elf.c: Add LoongArch elfcore_grok_xxx. * elfnn-loongarch.c: New. * elfxx-loongarch.c: New. * elfxx-loongarch.h: New. * reloc.c: Add LoongArch BFD RELOC ENUM. * targets.c: Add LoongArch target. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * libbfd.h: Regenerate. * po/BLD-POTFILES.in: Regenerate. * po/SRC-POTFILES.in: Regenerate. include/ * elf/common.h: Add NT_LARCH_{CPUCFG,CSR,LSX,LASX}. * elf/loongarch.h: New.
2021-10-07RISC-V: Add support for Zbs instructionsPhilipp Tomsich2-0/+25
This change adds the Zbs instructions from the Zbs 1.0.0 specification. See https://github.com/riscv/riscv-bitmanip/releases/tag/1.0.0 for the frozen specification. 2021-01-09 Philipp Tomsich <philipp.tomsich@vrull.eu> bfd/ * elfxx-riscv.c (riscv_supported_std_z_ext): Added zbs. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZBS. * testsuite/gas/riscv/b-ext.d: Test Zbs instructions. * testsuite/gas/riscv/b-ext.s: Likewise. * testsuite/gas/riscv/b-ext-64.d: Likewise. * testsuite/gas/riscv/b-ext-64.s: Likewise. include/ * opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for Zbs. * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZBS. opcodes/ * riscv-opc.c (riscv_supported_std_z_ext): Add zbs. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
2021-09-30aarch64: add armv9-a architecture to -marchPrzemyslaw Wirkus1-0/+5
Patch is adding new 'armv9-a` command line flag to -march for AArch64. gas/ * config/tc-aarch64.c: Add 'armv9-a' command line flag. * docs/c-aarch64.text: Update docs. * NEWS: Update docs. include/ * opcode/aarch64.h (AARCH64_FEATURE_V9): New define. (AARCH64_ARCH_V9): New define.
2021-09-30Add Solaris specific ELF note processingLibor Bukata1-0/+23
Add elfcore_grok_solaris_note function that enables to obtain process status, register values, and program info from Solaris's core files. bfd/ * elf.c (elfcore_grok_solaris_note): Solaris specific ELF note parser. Better GDB's coredump analysis on Solaris... (elfcore_grok_solaris_note_impl): New function. (elfcore_grok_solaris_prstatus): New function. (elfcore_grok_solaris_info): New function. (elfcore_grok_solaris_lwpstatus): New function. (elf_parse_notes): Added "CORE" groker element. include/ * elf/common.h: Add note segment constants for core files on Solaris systems.
2021-09-07Revert: [AArch64] MTE corefile supportLuis Machado2-6/+9
bfd * elf.c (elfcore_make_memtag_note_section): New function. (elfcore_grok_note): Handle NT_MEMTAG note types. binutils* readelf.c (get_note_type): Handle NT_MEMTAG note types. include * elf/common.h (NT_MEMTAG): New constant. (NT_MEMTAG_TYPE_AARCH_MTE): New constant.
2021-09-02obstack.h __PTR_ALIGN vs. ubsanAlan Modra1-3/+3
Current ubsan complains on every use of __PTR_ALIGN (when ptrdiff_t is as large as a pointer), due to making calculations relative to a NULL pointer. This patch avoids the problem by extracting out and simplifying __BPTR_ALIGN for the usual case. I've continued to use ptrdiff_t here, where it might be better to throw away __BPTR_ALIGN entirely and just assume uintptr_t exists. * obstack.h (__PTR_ALIGN): Expand and simplify __BPTR_ALIGN rather than calculating relative to a NULL pointer.
2021-08-30RISC-V: PR27916, Support mapping symbols.Nelson Chu1-0/+7
Similar to ARM/AARCH64, we add mapping symbols in the symbol table, to mark the start addresses of data and instructions. The $d means data, and the $x means instruction. Then the disassembler uses these symbols to decide whether we should dump data or instruction. Consider the mapping-04 test case, $ cat tmp.s .text .option norelax .option norvc .fill 2, 4, 0x1001 .byte 1 .word 0 .balign 8 add a0, a0, a0 .fill 5, 2, 0x2002 add a1, a1, a1 .data .word 0x1 # No need to add mapping symbols. .word 0x2 $ riscv64-unknown-elf-as tmp.s -o tmp.o $ riscv64-unknown-elf-objdump -d tmp.o Disassembly of section .text: 0000000000000000 <.text>: 0: 00001001 .word 0x00001001 # Marked $d, .fill directive. 4: 00001001 .word 0x00001001 8: 00000001 .word 0x00000001 # .byte + part of .word. c: 00 .byte 0x00 # remaining .word. d: 00 .byte 0x00 # Marked $d, odd byte of alignment. e: 0001 nop # Marked $x, nops for alignment. 10: 00a50533 add a0,a0,a0 14: 20022002 .word 0x20022002 # Marked $d, .fill directive. 18: 20022002 .word 0x20022002 1c: 2002 .short 0x2002 1e: 00b585b3 add a1,a1,a1 # Marked $x. 22: 0001 nop # Section tail alignment. 24: 00000013 nop * Use $d and $x to mark the distribution of data and instructions. Alignments of code are recognized as instructions, since we usually fill nops for them. * If the alignment have odd bytes, then we cannot just fill the nops into the spaces. We always fill an odd byte 0x00 at the start of the spaces. Therefore, add a $d mapping symbol for the odd byte, to tell disassembler that it isn't an instruction. The behavior is same as Arm and Aarch64. The elf/linux toolchain regressions all passed. Besides, I also disable the mapping symbols internally, but use the new objudmp, the regressions passed, too. Therefore, the new objudmp should dump the objects corretly, even if they don't have any mapping symbols. bfd/ pr 27916 * cpu-riscv.c (riscv_elf_is_mapping_symbols): Define mapping symbols. * cpu-riscv.h: extern riscv_elf_is_mapping_symbols. * elfnn-riscv.c (riscv_maybe_function_sym): Do not choose mapping symbols as a function name. (riscv_elf_is_target_special_symbol): Add mapping symbols. binutils/ pr 27916 * testsuite/binutils-all/readelf.s: Updated. * testsuite/binutils-all/readelf.s-64: Likewise. * testsuite/binutils-all/readelf.s-64-unused: Likewise. * testsuite/binutils-all/readelf.ss: Likewise. * testsuite/binutils-all/readelf.ss-64: Likewise. * testsuite/binutils-all/readelf.ss-64-unused: Likewise. gas/ pr 27916 * config/tc-riscv.c (make_mapping_symbol): Create a new mapping symbol. (riscv_mapping_state): Decide whether to create mapping symbol for frag_now. Only add the mapping symbols to text sections. (riscv_add_odd_padding_symbol): Add the mapping symbols for the riscv_handle_align, which have odd bytes spaces. (riscv_check_mapping_symbols): Remove any excess mapping symbols. (md_assemble): Marked as MAP_INSN. (riscv_frag_align_code): Marked as MAP_INSN. (riscv_init_frag): Add mapping symbols for frag, it usually called by frag_var. Marked as MAP_DATA for rs_align and rs_fill, and marked as MAP_INSN for rs_align_code. (s_riscv_insn): Marked as MAP_INSN. (riscv_adjust_symtab): Call riscv_check_mapping_symbols. * config/tc-riscv.h (md_cons_align): Defined to riscv_mapping_state with MAP_DATA. (TC_SEGMENT_INFO_TYPE): Record mapping state for each segment. (TC_FRAG_TYPE): Record the first and last mapping symbols for the fragments. The first mapping symbol must be placed at the start of the fragment. (TC_FRAG_INIT): Defined to riscv_init_frag. * testsuite/gas/riscv/mapping-01.s: New testcase. * testsuite/gas/riscv/mapping-01a.d: Likewise. * testsuite/gas/riscv/mapping-01b.d: Likewise. * testsuite/gas/riscv/mapping-02.s: Likewise. * testsuite/gas/riscv/mapping-02a.d: Likewise. * testsuite/gas/riscv/mapping-02b.d: Likewise. * testsuite/gas/riscv/mapping-03.s: Likewise. * testsuite/gas/riscv/mapping-03a.d: Likewise. * testsuite/gas/riscv/mapping-03b.d: Likewise. * testsuite/gas/riscv/mapping-04.s: Likewise. * testsuite/gas/riscv/mapping-04a.d: Likewise. * testsuite/gas/riscv/mapping-04b.d: Likewise. * testsuite/gas/riscv/mapping-norelax-04a.d: Likewise. * testsuite/gas/riscv/mapping-norelax-04b.d: Likewise. * testsuite/gas/riscv/no-relax-align.d: Updated. * testsuite/gas/riscv/no-relax-align-2.d: Likewise. include/ pr 27916 * opcode/riscv.h (enum riscv_seg_mstate): Added. opcodes/ pr 27916 * riscv-dis.c (last_map_symbol, last_stop_offset, last_map_state): Added to dump sections with mapping symbols. (riscv_get_map_state): Get the mapping state from the symbol. (riscv_search_mapping_symbol): Check the sorted symbol table, and then find the suitable mapping symbol. (riscv_data_length): Decide which data size we should print. (riscv_disassemble_data): Dump the data contents. (print_insn_riscv): Handle the mapping symbols. (riscv_symbol_is_valid): Marked mapping symbols as invalid.
2021-08-17sim: rename ChangeLog files to ChangeLog-2021Mike Frysinger1-0/+0
Now that ChangeLog entries are no longer used for sim patches, this commit renames all relevant sim ChangeLog to ChangeLog-2021, similar to what we would do in the context of the "Start of New Year" procedure. The purpose of this change is to avoid people merging ChangeLog entries by mistake when applying existing commits that they are currently working on. Also throw in a .gitignore entry to keep people from adding new ChangeLog files anywhere in the sim tree.
2021-08-17PATCH [4/4] arm: Add Tag_PACRET_use build attributeAndrea Corallo1-0/+1
bfd/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf32-arm.c (elf32_arm_merge_eabi_attributes): Add 'Tag_PACRET_use' case. binutils/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * readelf.c (arm_attr_tag_PAC_extension): Declare. (arm_attr_public_tags): Add 'PAC_extension' lookup. elfcpp/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * arm.h: Define 'Tag_PACRET_use' enum. gas/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (arm_convert_symbolic_attribute): Add 'Tag_PACRET_use' to the attribute_table. include/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf/arm.h (elf_arm_reloc_type): Add 'Tag_PACRET_use'.
2021-08-17PATCH [3/4] arm: Add Tag_BTI_use build attributeAndrea Corallo1-0/+1
bfd/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf32-arm.c (elf32_arm_merge_eabi_attributes): Add 'Tag_BTI_use' case. binutils/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * readelf.c (arm_attr_tag_PAC_extension): Declare. (arm_attr_public_tags): Add 'PAC_extension' lookup. elfcpp/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * arm.h: Define 'Tag_BTI_use' enum. gas/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (arm_convert_symbolic_attribute): Add 'Tag_BTI_use' to the attribute_table. include/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf/arm.h (elf_arm_reloc_type): Add 'Tag_BTI_use'.
2021-08-17PATCH [2/4] arm: Add Tag_BTI_extension build attributeAndrea Corallo1-0/+1
bfd/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf32-arm.c (elf32_arm_merge_eabi_attributes): Add 'Tag_BTI_extension' case. binutils/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * readelf.c (arm_attr_tag_PAC_extension): Declare. (arm_attr_public_tags): Add 'PAC_extension' lookup. elfcpp/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * arm.h: Define 'Tag_BTI_extension' enum. gas/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (arm_convert_symbolic_attribute): Add 'Tag_BTI_extension' to the attribute_table. include/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf/arm.h (elf_arm_reloc_type): Add 'Tag_BTI_extension'.
2021-08-17PATCH [1/4] arm: Add Tag_PAC_extension build attributeAndrea Corallo1-0/+1
bfd/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf32-arm.c (elf32_arm_merge_eabi_attributes): Add 'Tag_PAC_extension' case. binutils/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * readelf.c (arm_attr_tag_PAC_extension): Declare. (arm_attr_public_tags): Add 'PAC_extension' lookup. elfcpp/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * arm.h: Define 'Tag_PAC_extension' enum. gas/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (arm_convert_symbolic_attribute): Add 'Tag_PAC_extension' to the attribute_table. include/ 2021-07-06 Andrea Corallo <andrea.corallo@arm.com> * elf/arm.h (elf_arm_reloc_type): Add 'Tag_PAC_extension'.
2021-08-11Add 3 new PAC-related ARM note typesLuis Machado1-0/+9
The following patch synchronizes includes/objdump/readelf with the Linux Kernel in terms of ARM regset notes. We're currently missing 3 of them: NT_ARM_PACA_KEYS NT_ARM_PACG_KEYS NT_ARM_PAC_ENABLED_KEYS We don't need GDB to bother with this at the moment, so this doesn't update bfd/elf.c. If needed, we can do it in the future. binutils/ * readelf.c (get_note_type): Handle new ARM PAC notes. include/elf/ * common.h (NT_ARM_PACA_KEYS, NT_ARM_PACG_KEYS) (NT_ARM_PAC_ENABLED_KEYS): New constants.
2021-07-26PATCH [6/10] arm: Add -march=armv8.1-m.main+pacbti flagAndrea Corallo1-0/+7
gas/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * config/tc-arm.c (pacbti_ext): Define. (BAD_PACBTI): New macro. (armv8_1m_main_ext_table): Add 'pacbti' extension. include/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * opcode/arm.h (ARM_EXT3_PACBTI, ARM_AEXT3_V8_1M_MAIN_PACBTI): New macro.
2021-07-26PATCH [5/10] arm: Extend again arm_feature_set struct to provide more bitsAndrea Corallo1-4/+16
include/ 2021-06-11 Andrea Corallo <andrea.corallo@arm.com> * opcode/arm.h (arm_feature_set): Extend 'core' field. (ARM_CPU_HAS_FEATURE, ARM_FSET_CPU_SUBSET, ARM_CPU_IS_ANY) (ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE, ARM_FEATURE_EQUAL) (ARM_FEATURE_ZERO, ARM_FEATURE_CORE_EQUAL): Account for 'core[2]'. (ARM_FEATURE_CORE_HIGH_HIGH): New macro.
2021-07-08elf: Add GNU_PROPERTY_1_NEEDED checkH.J. Lu1-4/+19
If GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS is set on any input relocatable files: 1. Don't generate copy relocations. 2. Turn off extern_protected_data since it implies GNU_PROPERTY_NO_COPY_ON_PROTECTED. 3. Treate reference to protected symbols with indirect external access as local. 4. Set GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS on output. 5. When generating executable, clear this bit when there are non-GOT or non-PLT relocations in input relocatable files without the bit set. 6. Add -z [no]indirect-extern-access to control indirect external access. bfd/ * elf-bfd (elf_obj_tdata): Add has_indirect_extern_access. (elf_has_indirect_extern_access): New. * elf-properties.c (_bfd_elf_parse_gnu_properties): Set elf_has_indirect_extern_access and elf_has_no_copy_on_protected when seeing GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS. (elf_write_gnu_propertie): Add an argument to pass link_info. Set needed_1_p for GNU_PROPERTY_1_NEEDED in memory. (_bfd_elf_link_setup_gnu_properties): Handle GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS for -z indirect-extern-access. Set nocopyreloc to true and extern_protected_data to false for indirect external access. (_bfd_elf_convert_gnu_properties): Updated. * elf32-i386.c (elf_i386_check_relocs): Set non_got_ref_without_indirect_extern_access on legacy non-GOT or non-PLT references. * elf64-x86-64.c (elf_x86_64_check_relocs): Likewise. * elflink.c (_bfd_elf_symbol_refs_local_p): Return true for STV_PROTECTED symbols with indirect external access. * elfxx-x86.c (_bfd_x86_elf_adjust_dynamic_symbol): Clear indirect_extern_access for legacy non-GOT/non-PLT references. * elfxx-x86.h (elf_x86_link_hash_entry): Add non_got_ref_without_indirect_extern_access. include/ * bfdlink.h (bfd_link_info): Add indirect_extern_access and needed_1_p. Change nocopyreloc to int. ld/ * NEWS: Mention -z [no]indirect-extern-access * ld.texi: Document -z [no]indirect-extern-access * ldmain.c (main): Initialize link_info.indirect_extern_access to -1. * emulparams/extern_protected_data.sh: Support -z [no]indirect-extern-access. * testsuite/ld-elf/indirect-extern-access-1.rd: New file * testsuite/ld-elf/indirect-extern-access-1a.c: Likewise. * testsuite/ld-elf/indirect-extern-access-1b.c: Likewise. * testsuite/ld-elf/indirect-extern-access-2.rd: Likewise. * testsuite/ld-elf/indirect-extern-access-2a.c: Likewise. * testsuite/ld-elf/indirect-extern-access-2b.c: Likewise. * testsuite/ld-elf/indirect-extern-access-3.rd: Likewise. * testsuite/ld-elf/indirect-extern-access.S: Likewise. * testsuite/ld-elf/property-1_needed-1b.d: Likewise. * testsuite/ld-elf/property-1_needed-1c.d: Likewise. * testsuite/ld-x86-64/indirect-extern-access.rd: Likewise. * testsuite/ld-x86-64/protected-data-1.h: Likewise. * testsuite/ld-x86-64/protected-data-1a.c: Likewise. * testsuite/ld-x86-64/protected-data-1b.c: Likewise. * testsuite/ld-x86-64/protected-data-2a.S: Likewise. * testsuite/ld-x86-64/protected-data-2b.S: Likewise. * testsuite/ld-x86-64/protected-func-2a.S: Likewise. * testsuite/ld-x86-64/protected-func-2b.S: Likewise. * testsuite/ld-x86-64/protected-func-2c.c: Likewise. * testsuite/ld-elf/linux-x86.exp: Run test with GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS. * testsuite/ld-x86-64/x86-64.exp: Run tests for protected function and data with indirect external access.
2021-07-08elf: Add GNU_PROPERTY_1_NEEDEDH.J. Lu1-0/+7
Add GNU_PROPERTY_1_NEEDED: #define GNU_PROPERTY_1_NEEDED GNU_PROPERTY_UINT32_OR_LO to indicate the needed properties by the object file. Add GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS: #define GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS (1U << 0) to indicate that the object file requires canonical function pointers and cannot be used with copy relocation. binutils/ * readelf.c (decode_1_needed): New. (print_gnu_property_note): Handle GNU_PROPERTY_1_NEEDED. include/ * elf/common.h (GNU_PROPERTY_1_NEEDED): New. (GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS): Likewise. ld/ * testsuite/ld-elf/property-1_needed-1a.d: New file. * testsuite/ld-elf/property-1_needed-1.s: Likewise.
2021-07-08ld: Limit cache size and add --max-cache-size=SIZEH.J. Lu1-0/+7
When link_info.keep_memory is true, linker caches the relocation information and symbol tables of input files in memory. When there are many input files with many relocations, we may run out of memory. Add --max-cache-size=SIZE to set the maximum cache size. bfd/ PR ld/18028 * bfd.c (bfd): Add alloc_size. * elf-bfd.h (_bfd_elf_link_info_read_relocs): New. * elf32-i386.c (elf_i386_check_relocs): Use _bfd_link_keep_memory. Update cache_size. * elf64-x86-64.c (elf_x86_64_check_relocs): Likewise. * elflink.c (_bfd_elf_link_read_relocs): Renamed to ... (_bfd_elf_link_info_read_relocs): This. Update cache_size. (_bfd_elf_link_read_relocs): New. (_bfd_elf_link_check_relocs): Call _bfd_elf_link_info_read_relocs instead of _bfd_elf_link_read_relocs. (elf_link_add_object_symbols): Likewise. (elf_link_input_bfd): Likewise. (init_reloc_cookie_rels): Likewise. (init_reloc_cookie): Update cache_size. Call _bfd_elf_link_info_read_relocs instead of _bfd_elf_link_read_relocs. (link_info_ok): New. (elf_gc_smash_unused_vtentry_relocs): Updated. Call _bfd_elf_link_info_read_relocs instead of _bfd_elf_link_read_relocs. (bfd_elf_gc_sections): Use link_info_ok. Pass &link_info_ok to elf_gc_smash_unused_vtentry_relocs. * libbfd-in.h (_bfd_link_keep_memory): New. * linker.c (_bfd_link_keep_memory): New. * opncls.c (bfd_alloc): Update alloc_size. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. include/ PR ld/18028 * bfdlink.h (bfd_link_info): Add cache_size and max_cache_size. ld/ PR ld/18028 * NEWS: Mention --max-cache-size=SIZE. * ld.texi: Document --max-cache-size=SIZE. * ldlex.h (option_values): Add OPTION_MAX_CACHE_SIZE. * ldmain.c: (main): Set link_info.max_cache_size to -1. * lexsup.c (ld_options): Add --max-cache-size=SIZE. (parse_args): Support OPTION_MAX_CACHE_SIZE. * testsuite/ld-bootstrap/bootstrap.exp: Add test for --max-cache-size=-1.
2021-07-06RISC-V: Add PT_RISCV_ATTRIBUTES and add it to PHDR.Kito Cheng1-0/+5
We added PT_RISCV_ATTRIBUTES to program header to make .riscv.attribute easier to find in dynamic loader or kernel. Ref: https://github.com/riscv/riscv-elf-psabi-doc/pull/71 ChangeLog: bfd/ * elfnn-riscv.c(RISCV_ATTRIBUTES_SECTION_NAME): New. (riscv_elf_additional_program_headers): Ditto. (riscv_elf_modify_segment_map): Ditto. (elf_backend_additional_program_headers): Ditto. (elf_backend_modify_segment_map): Ditto. (elf_backend_obj_attrs_section): Use RISCV_ATTRIBUTES_SECTION_NAME rather than string literal. binutils/ * readelf.c(get_riscv_segment_type): New. (get_segment_type): Handle EM_RISCV. include/ * elf/riscv.h (PT_RISCV_ATTRIBUTES): New. * testsuite/ld-elf/orphan-region.ld: Discard .riscv.attributes section for simplify testcase. * testsuite/ld-riscv-elf/attr-phdr.d: New. * testsuite/ld-riscv-elf/attr-phdr.s: Ditto. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Add attr-phdr to testcase.
2021-07-03Add markers for 2.37 branchNick Clifton1-0/+4
2021-07-03Synchronize libiberty sources (and include/demangle.h) with GCC master versionNick Clifton2-0/+12
2021-07-01opcodes: constify aarch64_opcode_tablesMike Frysinger2-1/+5
This table is huge (~350k), so stop putting it into writable .data since it's only const data.
2021-07-01arm: don't treat XScale features as part of the FPU [PR 28031]Richard Earnshaw2-1/+6
Although the XScale and its iwMMX extensions are implemented in the Arm co-processor space, they are not considered to be part of the FPU specification. In particular, they cannot be enabled or disabled via a .fpu directive. It's therefore incorrect to strip these properties when a new .fpu directive is encountered. Note that the legacy Maverick co-processor is considered to be a FPU and it is possible to control this via the .fpu directive. include: PR gas/28031 * opcode/arm.h (FPU_ANY): Exclude XScale-related features.
2021-06-29sim: callback: add printf attributesMike Frysinger2-4/+13
This helps these funcs get printf format checking coverage. The sim-io.c hack as a result is a bit unfortunate, but the compiler throws warnings when printing with empty strings. In this one case, we actually want that due to the side-effect of the callback halting execution for us.
2021-06-24sim: callback: extend syscall interface to handle 7 argsMike Frysinger2-1/+6
The Linux syscall interface, depending on architecture, handles up to 7 arguments. Extend the callback API to handle those.
2021-06-23sim: callback: add a kill interfaceMike Frysinger2-0/+5
This will make it easier to emulate the syscall. If the kill target is the sim itself, don't do anything. This forces the higher layers to make a decision as to how to handle this event: like halting the overall engine process.
2021-06-22sim: callback: add a getpid interfaceMike Frysinger2-0/+5
Rather than hit the OS interface directly, use the existing callback layer so the instantiator can decide behavior.
2021-06-18elf: Add GNU_PROPERTY_UINT32_AND_XXX/GNU_PROPERTY_UINT32_OR_XXXH.J. Lu2-0/+17
Implement GNU_PROPERTY_UINT32_AND_XXX/GNU_PROPERTY_UINT32_OR_XXX: https://sourceware.org/pipermail/gnu-gabi/2021q1/000467.html 1. GNU_PROPERTY_UINT32_AND_LO..GNU_PROPERTY_UINT32_AND_HI #define GNU_PROPERTY_UINT32_AND_LO 0xb0000000 #define GNU_PROPERTY_UINT32_AND_HI 0xb0007fff A bit in the output pr_data field is set only if it is set in all relocatable input pr_data fields. If all bits in the the output pr_data field are zero, this property should be removed from output. If the bit is 1, all input relocatables have the feature. If the bit is 0 or the property is missing, the info is unknown. 2. GNU_PROPERTY_UINT32_OR_LO..GNU_PROPERTY_UINT32_OR_HI #define GNU_PROPERTY_UINT32_OR_LO 0xb0008000 #define GNU_PROPERTY_UINT32_OR_HI 0xb000ffff A bit in the output pr_data field is set if it is set in any relocatable input pr_data fields. If all bits in the the output pr_data field are zero, this property should be removed from output. If the bit is 1, some input relocatables have the feature. If the bit is 0 or the property is missing, the info is unknown. bfd/ * elf-properties.c (_bfd_elf_parse_gnu_properties): Handle GNU_PROPERTY_UINT32_AND_LO, GNU_PROPERTY_UINT32_AND_HI, GNU_PROPERTY_UINT32_OR_LO and GNU_PROPERTY_UINT32_OR_HI. (elf_merge_gnu_properties): Likewise. binutils/ * readelf.c (print_gnu_property_note): Handle GNU_PROPERTY_UINT32_AND_LO, GNU_PROPERTY_UINT32_AND_HI, GNU_PROPERTY_UINT32_OR_LO and GNU_PROPERTY_UINT32_OR_HI. include/ * elf/common.h (GNU_PROPERTY_UINT32_AND_LO): New. (GNU_PROPERTY_UINT32_AND_HI): Likewise. (GNU_PROPERTY_UINT32_OR_LO): Likewise. (GNU_PROPERTY_UINT32_OR_HI): Likewise. ld/ * testsuite/ld-elf/property-and-1.d: New file. * testsuite/ld-elf/property-and-1.s: Likewise. * testsuite/ld-elf/property-and-2.d: Likewise. * testsuite/ld-elf/property-and-2.s: Likewise. * testsuite/ld-elf/property-and-3.d: Likewise. * testsuite/ld-elf/property-and-3.s: Likewise. * testsuite/ld-elf/property-and-4.d: Likewise. * testsuite/ld-elf/property-and-empty.s: Likewise. * testsuite/ld-elf/property-or-1.d: Likewise. * testsuite/ld-elf/property-or-1.s: Likewise. * testsuite/ld-elf/property-or-2.d: Likewise. * testsuite/ld-elf/property-or-2.s: Likewise. * testsuite/ld-elf/property-or-3.d: Likewise. * testsuite/ld-elf/property-or-3.s: Likewise. * testsuite/ld-elf/property-or-4.d: Likewise. * testsuite/ld-elf/property-or-empty.s: Likewise.
2021-06-15Allow readelf to recognise GO buildid notes.Nick Clifton2-0/+5
binutils * readelf.c (get_note_type): Add support for NT_GO_BUILDID. include * elf/common.h (NT_GO_BUILDID): Define.
2021-06-02arc: Construct disassembler options dynamicallyShahab Vahedi2-0/+5
The idea of this change is simple: Populate a data structure, namely "disasm_option_and_arg_t" from "include/dis-asm.h", to encompass the disassembly options and their possible arguments. This will make it easier to manage or extend those options by adapting entries in a data structure, "arc_options". There will be lesser need to hard-code the options in the code itself. Moreover, ARC GDB will use this population function, "disassembler_options_arc ()", to enable the "set disassembler-option" for ARC targets. The gdb change will be in a separate patch though. The changes in this patch can be divided into: 1) Introduction of "disassembler_options_arc ()" that will return a "disasm_option_and_arg_t" structure representing the disassembly options and their likely arguments. 2) New data type "arc_options_arg_t" and new data "arc_options". These are the internals for keeping track of options and arguments entries that can easily be extended. 3) To print the options, the "print_arc_disassembler_options ()" has been adjusted to use this dynamically built structure instead of having them hard-coded inside. To see this in effect, one can look into the output of: $ ./binutils/objdump --help ... The following ARC specific disassembler options are... ... include/ChangeLog: * dis-asm.h (disassembler_options_arc): New prototype. opcodes/ChangeLog: * arc-dis.c (arc_option_arg_t): New enumeration. (arc_options): New variable. (disassembler_options_arc): New function. (print_arc_disassembler_options): Reimplement in terms of "disassembler_options_arc".
2021-05-29MIPS/opcodes: Properly handle ISA exclusionMaciej W. Rozycki2-19/+24
Remove the hack used for MIPSr6 ISA exclusion from `cpu_is_member' and handle the exclusion for any ISA levels properly in `opcode_is_member'. Flatten the structure of the `if' statements there. No functional change for the existing opcode tables. include/ * opcode/mips.h (cpu_is_member): Remove code for MIPSr6 ISA exclusion. (opcode_is_member): Handle ISA level exclusion.
2021-05-29MIPS/opcodes: Factor out ISA matching against flagsMaciej W. Rozycki2-4/+27
In preparation for the next change factor out code for ISA matching against instruction flags used in MIPS opcode tables, similarly to how CPU matching is already done. No functional change, though for clarity split the single `if' statement into multiple ones and use temporaries rather than repeated expressions. include/ * opcode/mips.h (isa_is_member): New inline function, factored out from... (opcode_is_member): ... here.
2021-05-29MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki2-2/+15
The CP0 control register set has never been defined, however encodings for the CFC0 and CTC0 instructions remained available for implementers up until the MIPS32 ISA declared them invalid and causing the Reserved Instruction exception[1]. Therefore we handle them for both assembly and disassembly, however in the latter case the names of CP0 registers from the regular set are incorrectly printed if named registers are requested. This is because we do not define separate operand classes for coprocessor regular and control registers respectively, which means the disassembler has no way to tell the two cases apart. Consequently nonsensical disassembly is produced like: cfc0 v0,c0_random Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0 instructions[2] although it failed to document them in the relevant opcode table until MIPSr6 only. Correct the issue then by defining a new register class, OP_REG_CONTROL, and corresponding operand codes, `g' and `y' for the two positions in the machine instruction a control register operand can take. Adjust the test cases affected accordingly. While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries with each other so that they come in the alphabetical order. References: [1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of rs Field", p. 242 [2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of Instructions", pp. 195, 216 include/ * opcode/mips.h: Document `g' and `y' operand codes. (mips_reg_operand_type): Add OP_REG_CONTROL enumeration constant. gas/ * tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case. (macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G' operand code. opcodes/ * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register handling code over to... <OP_REG_CONTROL>: ... this new case. * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases. (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2", "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries replacing the `G' operand code with `g'. Update "cftc1" and "cftc2" entries replacing the `E' operand code with `y'. * micromips-opc.c (decode_micromips_operand) <'g'>: New case. (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2" entries replacing the `G' operand code with `g'. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0 operand disassembly. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
2021-05-29MIPS/opcodes: Free up redundant `g' operand codeMaciej W. Rozycki2-2/+6
In the operand handling rewrite made for the MIPS disassembler with commit ab90248154ba ("Add structures to describe MIPS operands"), <https://sourceware.org/ml/binutils/2013-07/msg00135.html>, the `g' operand code has become redundant for the regular MIPS instruction set by duplicating the OP_REG_COPRO semantics of the `G' operand code. Later commit 351cdf24d223 ("Implement O32 FPXX, FP64 and FP64A ABI extensions") converted the CTTC1 instruction from the `g' to the `G' operand code, but still left a few instructions behind. Convert the three remaining instructions still using the `g' code then, namely: CTTC2, MTTC2 and MTTHC2, and remove all traces of the operand code, freeing it up for other use. opcodes/ * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2", and "mtthc2" to using the `G' rather than `g' operand code for the coprocessor control register referred. include/ * opcode/mips.h: Complement change made to opcodes and remove references to the `g' regular MIPS ISA operand code.
2021-05-28x86: Restore PC16 relocation overflow checkH.J. Lu2-1/+5
The x86-64 psABI has --- A program or object file using R_X86_64_8, R_X86_64_16, R_X86_64_PC16 or R_X86_64_PC8 relocations is not conformant to this ABI, these relocations are only added for documentation purposes. --- Since x86 PC16 relocations have been used for 16-bit programs in an ELF32 or ELF64 container, PC16 relocation should wrap-around in 16-bit address space. Revert commit a7664973b24a242cd9ea17deb5eaf503065fc0bd Author: Jan Beulich <jbeulich@suse.com> Date: Mon Apr 26 10:41:35 2021 +0200 x86: correct overflow checking for 16-bit PC-relative relocs and xfail the related tests. Also revert commit 50c95a739c91ae70cf8481936611aa1f5397a384 Author: H.J. Lu <hjl.tools@gmail.com> Date: Wed May 26 12:13:13 2021 -0700 x86: Propery check PC16 reloc overflow in 16-bit mode instructions while keeping PR ld/27905 tests for PC16 relocation in 16-bit programs. bfd/ PR ld/27905 * elf32-i386.c: Don't include "libiberty.h". (elf_howto_table): Revert commits a7664973b24 and 50c95a739c9. (elf_i386_rtype_to_howto): Revert commit 50c95a739c9. (elf_i386_info_to_howto_rel): Likewise. (elf_i386_tls_transition): Likewise. (elf_i386_relocate_section): Likewise. * elf64-x86-64.c (x86_64_elf_howto_table): Revert commits a7664973b24 and 50c95a739c9. (elf_x86_64_rtype_to_howto): Revert commit 50c95a739c9. * elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Likewise. * elfxx-x86.h (elf_x86_obj_tdata): Likewise. (elf_x86_has_code16): Likewise. binutils/ PR ld/27905 * readelf.c (decode_x86_feature_2): Revert commit 50c95a739c9. gas/ PR ld/27905 * config/tc-i386.c (set_code_flag): Revert commit 50c95a739c9. (set_16bit_gcc_code_flag): Likewise. (x86_cleanup): Likewise. * testsuite/gas/i386/code16-2.d: Updated. * testsuite/gas/i386/x86-64-code16-2.d: Likewise. include/ PR ld/27905 * elf/common.h (GNU_PROPERTY_X86_FEATURE_2_CODE16): Removed. ld/ PR ld/27905 * testsuite/ld-i386/pcrel16-2.d: xfail. * testsuite/ld-x86-64/pcrel16-2.d: Likewise.
2021-05-26x86: Propery check PC16 reloc overflow in 16-bit mode instructionsH.J. Lu2-0/+6
commit a7664973b24a242cd9ea17deb5eaf503065fc0bd Author: Jan Beulich <jbeulich@suse.com> Date: Mon Apr 26 10:41:35 2021 +0200 x86: correct overflow checking for 16-bit PC-relative relocs caused linker failure when building 16-bit program in a 32-bit ELF container. Update GNU_PROPERTY_X86_FEATURE_2_USED with #define GNU_PROPERTY_X86_FEATURE_2_CODE16 (1U << 12) to indicate that 16-bit mode instructions are used in the input object: https://groups.google.com/g/x86-64-abi/c/UvvXWeHIGMA to indicate that 16-bit mode instructions are used in the object to allow linker to properly perform relocation overflow check for 16-bit PC-relative relocations in 16-bit mode instructions. 1. Update x86 assembler to always generate the GNU property note with GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF object. 2. Update i386 and x86-64 linkers to use 16-bit PC16 relocations if input object is marked with GNU_PROPERTY_X86_FEATURE_2_CODE16. bfd/ PR ld/27905 * elf32-i386.c: Include "libiberty.h". (elf_howto_table): Add 16-bit R_386_PC16 entry. (elf_i386_rtype_to_howto): Add a BFD argument. Use 16-bit R_386_PC16 if input has 16-bit mode instructions. (elf_i386_info_to_howto_rel): Update elf_i386_rtype_to_howto call. (elf_i386_tls_transition): Likewise. (elf_i386_relocate_section): Likewise. * elf64-x86-64.c (x86_64_elf_howto_table): Add 16-bit R_X86_64_PC16 entry. (elf_x86_64_rtype_to_howto): Use 16-bit R_X86_64_PC16 if input has 16-bit mode instructions. * elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Set elf_x86_has_code16 if relocatable input is marked with GNU_PROPERTY_X86_FEATURE_2_CODE16. * elfxx-x86.h (elf_x86_obj_tdata): Add has_code16. (elf_x86_has_code16): New. binutils/ PR ld/27905 * readelf.c (decode_x86_feature_2): Support GNU_PROPERTY_X86_FEATURE_2_CODE16. gas/ PR ld/27905 * config/tc-i386.c (set_code_flag): Update x86_feature_2_used with GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF object. (set_16bit_gcc_code_flag): Likewise. (x86_cleanup): Always generate the GNU property note if x86_feature_2_used isn't 0. * testsuite/gas/i386/code16-2.d: New file. * testsuite/gas/i386/code16-2.s: Likewise. * testsuite/gas/i386/x86-64-code16-2.d: Likewise. * testsuite/gas/i386/i386.exp: Run code16-2 and x86-64-code16-2. include/ PR ld/27905 * elf/common.h (GNU_PROPERTY_X86_FEATURE_2_CODE16): New. ld/ PR ld/27905 * testsuite/ld-i386/code16.d: New file. * testsuite/ld-i386/code16.t: Likewise. * testsuite/ld-x86-64/code16.d: Likewise. * testsuite/ld-x86-64/code16.t: Likewise. * testsuite/ld-i386/i386.exp: Run code16. * testsuite/ld-x86-64/x86-64.exp: Likewise.
2021-05-23elf: Use official name LoongArch for EM_LOONGARCH.Chenghua Xu2-1/+6
The official name for Loongson Architecture is LoongArch, it is better to use LoongArch instead of Loongson Loongarch for EM_LOONGARCH to avoid confusion and keep consistent with the various of software in the future. The official documentation in Chinese: http://www.loongson.cn/uploadfile/cpu/LoongArch.pdf The translated version in English: https://loongson.github.io/LoongArch-Documentation/ binutils/ * readelf.c (get_machine_name): Change Loongson Loongarch to LoongArch. include/ * elf/common.h (EM_LOONGARCH): Change Loongson Loongarch to LoongArch.
2021-05-21[AArch64] MTE corefile supportLuis Machado2-0/+11
bfd * elf.c (elfcore_make_memtag_note_section): New function. (elfcore_grok_note): Handle NT_MEMTAG note types. binutils* readelf.c (get_note_type): Handle NT_MEMTAG note types. include * elf/common.h (NT_MEMTAG): New constant. (NT_MEMTAG_TYPE_AARCH_MTE): New constant.
2021-05-14sim: callback: convert FS interfaces to 64-bitMike Frysinger2-3/+8
Rather than rely on off_t being the right size between the host & target, have the interface always be 64-bit. We can figure out if we need to truncate when actually outputting it to the right target.
2021-05-14sim: callback: convert time interface to 64-bitMike Frysinger2-1/+8
PR sim/27705 Rather than rely on time_t being the right size between the host & target, have the interface always be 64-bit. We can figure out if we need to truncate when actually outputting it to the right target.
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