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2021-10-28RISC-V/SiFive: Added SiFive custom cache control instructions.users/riscv/binutils-integration-branchNelson Chu2-0/+16
2021-10-28RISC-V/rvv: Added zve* and zvl* extensions, and clarify the imply rules.Nelson Chu1-0/+2
2021-10-28RISC-V/rvv: Separate zvamo from v, and removed the zvlsseg extension name.Nelson Chu1-2/+1
2021-10-28RISC-V/rvv: Added assembly pseudo and changed assembler mnemonics.Nelson Chu1-14/+14
2021-10-28RISC-V/t-head: Add CSRs and opcodes of the T-HEAD XUANTIE CPUsLifang Xia2-0/+581
2021-10-28RISC-V: Support svinval extensions.Nelson Chu2-0/+17
2021-10-28RISC-V/zfh: Add half-precision floating-point v0.1 instructions.Nelson Chu2-0/+116
2021-10-28RISC-V/rvv: Add rvv v0.10 instructions.Nelson Chu2-1/+1448
2021-10-28RISC-V/extended: Add assembler and dis-assembler hooks for extended extensions.Nelson Chu2-3/+30
2021-10-24LoongArch opcodes supportliuzhensong2-0/+240
2021-10-24LoongArch bfd supportliuzhensong2-1/+130
2021-10-07RISC-V: Add support for Zbs instructionsPhilipp Tomsich2-0/+25
2021-09-30aarch64: add armv9-a architecture to -marchPrzemyslaw Wirkus1-0/+5
2021-09-30Add Solaris specific ELF note processingLibor Bukata1-0/+23
2021-09-07Revert: [AArch64] MTE corefile supportLuis Machado2-6/+9
2021-09-02obstack.h __PTR_ALIGN vs. ubsanAlan Modra1-3/+3
2021-08-30RISC-V: PR27916, Support mapping symbols.Nelson Chu1-0/+7
2021-08-17sim: rename ChangeLog files to ChangeLog-2021Mike Frysinger1-0/+0
2021-08-17PATCH [4/4] arm: Add Tag_PACRET_use build attributeAndrea Corallo1-0/+1
2021-08-17PATCH [3/4] arm: Add Tag_BTI_use build attributeAndrea Corallo1-0/+1
2021-08-17PATCH [2/4] arm: Add Tag_BTI_extension build attributeAndrea Corallo1-0/+1
2021-08-17PATCH [1/4] arm: Add Tag_PAC_extension build attributeAndrea Corallo1-0/+1
2021-08-11Add 3 new PAC-related ARM note typesLuis Machado1-0/+9
2021-07-26PATCH [6/10] arm: Add -march=armv8.1-m.main+pacbti flagAndrea Corallo1-0/+7
2021-07-26PATCH [5/10] arm: Extend again arm_feature_set struct to provide more bitsAndrea Corallo1-4/+16
2021-07-08elf: Add GNU_PROPERTY_1_NEEDED checkH.J. Lu1-4/+19
2021-07-08elf: Add GNU_PROPERTY_1_NEEDEDH.J. Lu1-0/+7
2021-07-08ld: Limit cache size and add --max-cache-size=SIZEH.J. Lu1-0/+7
2021-07-06RISC-V: Add PT_RISCV_ATTRIBUTES and add it to PHDR.Kito Cheng1-0/+5
2021-07-03Add markers for 2.37 branchNick Clifton1-0/+4
2021-07-03Synchronize libiberty sources (and include/demangle.h) with GCC master versionNick Clifton2-0/+12
2021-07-01opcodes: constify aarch64_opcode_tablesMike Frysinger2-1/+5
2021-07-01arm: don't treat XScale features as part of the FPU [PR 28031]Richard Earnshaw2-1/+6
2021-06-29sim: callback: add printf attributesMike Frysinger2-4/+13
2021-06-24sim: callback: extend syscall interface to handle 7 argsMike Frysinger2-1/+6
2021-06-23sim: callback: add a kill interfaceMike Frysinger2-0/+5
2021-06-22sim: callback: add a getpid interfaceMike Frysinger2-0/+5
2021-06-18elf: Add GNU_PROPERTY_UINT32_AND_XXX/GNU_PROPERTY_UINT32_OR_XXXH.J. Lu2-0/+17
2021-06-15Allow readelf to recognise GO buildid notes.Nick Clifton2-0/+5
2021-06-02arc: Construct disassembler options dynamicallyShahab Vahedi2-0/+5
2021-05-29MIPS/opcodes: Properly handle ISA exclusionMaciej W. Rozycki2-19/+24
2021-05-29MIPS/opcodes: Factor out ISA matching against flagsMaciej W. Rozycki2-4/+27
2021-05-29MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki2-2/+15
2021-05-29MIPS/opcodes: Free up redundant `g' operand codeMaciej W. Rozycki2-2/+6
2021-05-28x86: Restore PC16 relocation overflow checkH.J. Lu2-1/+5
2021-05-26x86: Propery check PC16 reloc overflow in 16-bit mode instructionsH.J. Lu2-0/+6
2021-05-23elf: Use official name LoongArch for EM_LOONGARCH.Chenghua Xu2-1/+6
2021-05-21[AArch64] MTE corefile supportLuis Machado2-0/+11
2021-05-14sim: callback: convert FS interfaces to 64-bitMike Frysinger2-3/+8
2021-05-14sim: callback: convert time interface to 64-bitMike Frysinger2-1/+8
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