aboutsummaryrefslogtreecommitdiff
path: root/include
AgeCommit message (Expand)AuthorFilesLines
2017-09-27Handle symbol defined in IR and referenced in DSOH.J. Lu2-0/+11
2017-05-05RISC-V: Resurrect GP-relative disassembly hintsPalmer Dabbelt2-0/+7
2017-04-03Add physical memory protection CSRsAndrew Waterman2-0/+83
2017-03-21S/390: Remove vx2 facility flagAndreas Krebbel2-2/+9
2017-02-28PowerPC addpcis fixAlan Modra3-2/+15
2017-02-27Add new counter-enable CSRsAndrew Waterman2-0/+11
2017-02-27Add SFENCE.VMA instructionAndrew Waterman2-0/+9
2017-02-27 sveRichard Sandiford2-0/+13
2017-02-27 sveRichard Sandiford2-1/+8
2017-02-27[AArch64] Add separate feature flag for weaker release consistent load insnsRichard Sandiford2-1/+8
2017-02-23S/390: Add support for new cpu architecture - arch12.Andreas Krebbel1-1/+4
2017-01-02Update year range in copyright notice of all files.Alan Modra320-319/+323
2017-01-02ChangeLog rotationAlan Modra2-822/+836
2016-12-23MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki2-2/+13
2016-12-23MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki2-5/+10
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki2-0/+8
2016-12-21Remove high bit set charactersAlan Modra3-9/+14
2016-12-20MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki2-0/+12
2016-12-20Re-work RISC-V gas flags: now we just support -mabi and -marchAndrew Waterman2-2/+21
2016-12-20Rework RISC-V relocationsAndrew Waterman2-0/+13
2016-12-16Implement and document --gc-keep-exportedfincs2-0/+7
2016-12-14MIPS/opcodes: Also set disassembler's ASE flags from ELF structuresMaciej W. Rozycki2-1/+6
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li2-3/+11
2016-12-09MIPS16: Remove unused `>' operand codeMaciej W. Rozycki2-2/+5
2016-12-07MIPS/include: opcode/mips.h: Correct INSN_CHIP_MASKMaciej W. Rozycki2-1/+5
2016-12-07MIPS/include: opcode/mips.h: Add a comment for ASE_DSPR3Maciej W. Rozycki2-0/+5
2016-12-05[ARM] Add ARMv8.3 command line option and feature flagSzabolcs Nagy2-0/+9
2016-11-29[ARC] Add checking for LP_COUNT reg usage, improve error reporting.Claudiu Zissulescu2-0/+10
2016-11-22gas,opcodes: fix hardware capabilities bumping in the sparc assembler.Jose E. Marchesi2-0/+9
2016-11-22PR20744, Incorrect PowerPC VLE relocsAlan Modra2-0/+22
2016-11-18libiberty: Add Rust symbol demangling.David Tolnay2-2/+39
2016-11-18Implement P0012R1, Make exception specifications part of the type system.Jason Merrill2-1/+8
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy2-0/+11
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy2-0/+7
2016-11-11[AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy2-0/+5
2016-11-11[AArch64] Add ARMv8.3 command line option and feature flagSzabolcs Nagy2-14/+13
2016-11-04Commit missing ChangeLog entry for Cortex-M33 supportThomas Preud'homme1-0/+6
2016-11-04Add support for ARM Cortex-M33 processorThomas Preud'homme1-0/+4
2016-11-03arc: Implement NPS-400 dcmac instructionGraham Markall2-0/+5
2016-11-03arc: Change max instruction length to 64-bitsAndrew Burgess2-28/+15
2016-11-03opcodes/arc: Make some macros 64-bit safeGraham Markall2-26/+32
2016-11-03arc: Replace ARC_SHORT macro with arc_opcode_len functionGraham Markall2-4/+8
2016-11-01Add support for RISC-V architecture.Nick Clifton5-0/+1606
2016-10-17Update list of ELF machine numbers.Nick Clifton2-2/+41
2016-10-14FINAL/OVERRIDE: Define to empty on g++ < 4.7Pedro Alves2-5/+24
2016-10-14Move OVERRIDE/FINAL from gcc/coretypes.h to include/ansidecl.hPedro Alves2-6/+27
2016-10-14[ARC] Disassembler: fix LIMM detection for short instructions.Claudiu Zissulescu2-0/+5
2016-09-29Disallow 3-operand cmp[l][i] for ppc64Alan Modra2-0/+8
2016-09-26[ARC] ISA alignment.Claudiu Zissulescu2-1/+7
2016-09-26PowerPC .gnu.attributesAlan Modra2-5/+16
generated by cgit v1.1 at 2024-11-21 23:37:28 +0000