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2022-03-18RISC-V: Prefetch hint instructions and operand setTsukasa OI2-0/+8
2022-03-16binutils/readelf: handle AMDGPU relocation typesSimon Marchi2-0/+25
2022-03-16binutils/readelf: handle NT_AMDGPU_METADATA note nameSimon Marchi2-0/+8
2022-03-16binutils/readelf: decode AMDGPU-specific e_flagsSimon Marchi2-0/+59
2022-03-16binutils/readelf: handle AMDGPU OS ABIsSimon Marchi2-0/+7
2022-03-16bfd: add AMDGCN architectureSimon Marchi3-0/+42
2022-03-16Delete PowerPC macro insn supportAlan Modra1-26/+0
2022-03-16PowerPC64 extended instructions in powerpc_macrosAlan Modra1-3/+5
2022-03-11gprofng: a new GNU profilerVladimir Mezentsev4-0/+210
2022-02-23RISC-V: Updated CSRs to privileged spec v1.12 and debug spec v1.0.Nelson Chu1-34/+49
2022-02-23RISC-V: Add Privileged Architecture 1.12 CSRsTsukasa OI1-0/+138
2022-02-13PR28882, build failure with gcc-4.2 due to use of 0b literalsAlan Modra1-8/+8
2022-02-11gdb/fortran: support ptype and print commands for namelist variablesBhuvanendra Kumar N1-1/+1
2022-02-03Rename EM_56800V4 to EM_56800EF.Cary Coutant1-1/+1
2022-02-03Add new e_machine values.Cary Coutant1-0/+3
2022-01-25Fix a probem building the binutils on SPARC/amd64Klaus Ziegler2-0/+7
2022-01-22Add markers for 2.38 branchNick Clifton1-0/+4
2022-01-14PR28751 mbind2a / mbind2b regressions on powerpc*-linuxAlan Modra1-0/+3
2022-01-13Synchronize binutils libiberty sources with gcc version.Nick Clifton2-5/+8
2022-01-12ld: Initial DT_RELR supportH.J. Lu1-0/+4
2022-01-12gas: add visibility support for XCOFFClément Chigot2-0/+10
2022-01-05elf: Set p_align to the minimum page size if possibleH.J. Lu1-0/+3
2022-01-02Update year range in copyright notice of binutils filesAlan Modra289-289/+289
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker21-21/+21
2021-12-24RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta1-0/+100
2021-12-24RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/testsVineet Gupta1-20/+0
2021-12-16arm: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford1-0/+7
2021-12-16arm: Add support for Armv8.7-A and Armv8.8-ARichard Sandiford1-0/+2
2021-12-16aarch64: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford1-40/+62
2021-12-16RISC-V: Support svinval extension with frozen version 1.0.Nelson Chu2-0/+17
2021-12-07Support AT_FXRNG and AT_KPRELOAD on FreeBSD.John Baldwin2-0/+6
2021-12-04sim: reorder header includesMike Frysinger1-2/+3
2021-12-02aarch64: Add BC instructionRichard Sandiford1-1/+3
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford1-7/+25
2021-12-02aarch64: Add support for +mopsRichard Sandiford1-1/+6
2021-12-02aarch64: Add support for Armv8.8-ARichard Sandiford1-0/+3
2021-12-02aarch64: Tweak insn sequence codeRichard Sandiford1-7/+5
2021-12-02gdb, include: replace pragmas with DIAGNOSTIC macros, fix build with g++ 4.8Simon Marchi1-0/+16
2021-12-01readelf: recognize FDO Packaging Metadata ELF noteLuca Boccassi1-0/+3
2021-12-01Fix the fields in the x_n union inside the the x_file structure so that point...Nick Clifton2-5/+15
2021-11-30RISC-V: The vtype immediate with more than the defined 8 bits are preserved.Nelson Chu1-2/+0
2021-11-26opcodes/riscv: add disassembler options support to libopcodesAndrew Burgess2-0/+6
2021-11-23AArch64: Add support for AArch64 EFI (efi-*-aarch64).Tamar Christina2-0/+64
2021-11-19RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC.Nelson Chu1-0/+6
2021-11-18RISC-V: Add instructions and operand set for z[fdq]inxjiawei1-0/+3
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus1-0/+1
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus1-0/+3
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus1-1/+11
2021-11-17aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus1-0/+1
2021-11-17aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus1-0/+14
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