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AgeCommit message (Expand)AuthorFilesLines
2022-12-31Add markers for 2.40 branchNick Clifton1-0/+4
2022-12-31sync libiberty sources with gcc mainlineNick Clifton1-0/+20
2022-12-27RISC-V: Fix T-Head Fmv vendor extension encodingChristoph Müllner1-2/+2
2022-12-22sim: drop unused SIM_ADDR type [PR sim/7504]Mike Frysinger1-6/+0
2022-12-22sim: switch sim_{read,write} APIs to 64-bit all the time [PR sim/7504]Mike Frysinger1-2/+4
2022-12-22sframe.h: add support for .cfi_b_key_frameIndu Bhagat1-6/+19
2022-12-20sim: move register headers into sim/ namespace [PR sim/29869]Mike Frysinger15-0/+0
2022-12-16libsframe: provide new access API for mangled RA bitIndu Bhagat1-0/+7
2022-12-16sframe.h: add support for .cfi_negate_ra_stateIndu Bhagat1-8/+15
2022-12-15libsframe asan: avoid generating misaligned loadsIndu Bhagat1-2/+6
2022-12-09libsframe: rename API sframe_fde_func_info to sframe_fde_create_func_infoIndu Bhagat1-2/+2
2022-12-09sframe: gas: libsframe: define constants and remove magic numbersIndu Bhagat1-0/+15
2022-12-09sframe.h: make some macros more preciseIndu Bhagat1-3/+4
2022-12-07Compression tidy and fixesAlan Modra1-3/+0
2022-11-28xtensa: allow dynamic configurationMax Filippov1-0/+442
2022-11-25riscv: Add AIA extension support (Smaia, Ssaia)Christoph Müllner1-0/+68
2022-11-19RISC-V: Add 'Ssstateen' extension and its CSRsTsukasa OI1-13/+13
2022-11-17RISC-V: Add T-Head Int vendor extensionChristoph Müllner2-0/+9
2022-11-17RISC-V: Add T-Head Fmv vendor extensionChristoph Müllner2-0/+9
2022-11-15readelf/objdump: support for SFrame sectionIndu Bhagat1-0/+3
2022-11-15bfd: linker: merge .sframe sectionsIndu Bhagat3-1/+3
2022-11-15libsframe: add the SFrame libraryWeimin Pan1-0/+231
2022-11-15sframe.h: Add SFrame format definitionIndu Bhagat1-0/+303
2022-11-14aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira1-1/+5
2022-11-08sim: drop unused CORE_ADDR_TYPEMike Frysinger1-7/+0
2022-11-02sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger1-3/+2
2022-10-31sim: reg: constify store helperMike Frysinger1-1/+2
2022-10-31sim: common: change sim_read & sim_write to use void* buffersMike Frysinger1-2/+2
2022-10-28include: Define macro to ignore -Wdeprecated-declarations on GCCTsukasa OI1-0/+3
2022-10-27PowerPC: Add support for RFC02653 - Dense Math FacilityPeter Bergner1-15/+18
2022-10-19aarch64-pe support for LD, GAS and BFDJedidiah Thompson1-0/+22
2022-10-14e200 LSP supportAlan Modra1-0/+5
2022-10-14RISC-V: Move certain arrays to riscv-opc.cTsukasa OI1-11/+2
2022-10-04RISC-V: Fix buffer overflow on print_insn_riscvTsukasa OI1-0/+2
2022-10-04RISC-V: Renamed INSN_CLASS for floating point in integer extensions.Nelson Chu1-7/+7
2022-10-04RISC-V/gas: allow generating up to 176-bit instructions with .insnJan Beulich1-0/+3
2022-10-03Fix self-move warning check for GCC 13+Jan-Benedict Glaw2-0/+8
2022-09-30LoongArch: Update ELF e_flags handling according to specification.liuzhensong1-23/+21
2022-09-23Support AT_USRSTACKBASE and AT_USRSTACKLIM.John Baldwin1-0/+2
2022-09-23RISC-V: Add Zawrs ISA extension supportChristoph Müllner2-0/+9
2022-09-22RISC-V: Add T-Head MemPair vendor extensionChristoph Müllner2-0/+18
2022-09-22RISC-V: Add T-Head MemIdx vendor extensionChristoph Müllner2-0/+135
2022-09-22RISC-V: Add T-Head FMemIdx vendor extensionChristoph Müllner2-0/+27
2022-09-22RISC-V: Add T-Head MAC vendor extensionChristoph Müllner2-0/+21
2022-09-22RISC-V: Add T-Head CondMov vendor extensionChristoph Müllner2-0/+9
2022-09-22RISC-V: Add T-Head Bitmanip vendor extensionChristoph Müllner2-0/+42
2022-09-22RISC-V: Add support for arbitrary immediate encoding formatsChristoph Müllner1-0/+17
2022-09-22RISC-V: Add T-Head SYNC vendor extensionChristoph Müllner2-0/+18
2022-09-22RISC-V: Add T-Head CMO vendor extensionChristoph Müllner2-0/+66
2022-09-22include: Add macro to ignore -Wunused-but-set-variableTsukasa OI1-0/+14
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