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2016-05-26metag: add extern C to headerTrevor Saunders2-0/+12
include/ChangeLog: 2016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * opcode/metag.h: wrap declarations in extern "C".
2016-05-23[ARC] Update instruction type and delay slot info.Claudiu Zissulescu2-1/+10
This patch corrects the instructioninformation passed into the disassebler_info structure. include/ 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (insn_subclass_t): Add COND. (flag_class_t): Add F_CLASS_EXTEND. opcodes/ 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type information. (print_insn_arc): Set insn_type information. * arc-opc.c (C_CC): Add F_CLASS_COND. * arc-tbl.h (bbit0, bbit1): Update subclass to COND. (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise. (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise. (breq, breq_s, brge, brhs, brlo, brlt): Likewise. (brne, brne_s, jeq_s, jne_s): Likewise.
2016-05-23[ARC] Rename "class" named attributes.Claudiu Zissulescu2-2/+8
gas/ 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com> * config/tc-arc.c (attributes_t): Renamed attribute class to attr_class. (find_opcode_match, assemble_insn, tokenize_extinsn): Changed. opcode/ 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com> * arc-dis.c (find_format, find_format, get_auxreg) (print_insn_arc): Changed. * arc-ext.h (INSERT_XOP): Likewise. include/ 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com> * opcode/arc.h (struct arc_opcode): Renamed attribute class to insn_class. (struct arc_flag_class): Renamed attribute class to flag_class.
2016-05-23tic54x: rename typedef of struct symbol_Trevor Saunders2-4/+9
generic gas code has a struct symbol, and tic54x typedefs a struct to symbol. This seems at least rather confusing, and it seems like target specific headers shouldn't put such generic names in the global namespace preventing other generic code from using them. opcodes/ChangeLog: 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * tic54x-dis.c (sprint_mmr): Adjust. * tic54x-opc.c: Likewise. gas/ChangeLog: 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-tic54x.c (tic54x_mmregs): Adjust. (md_begin): Likewise. (encode_condition): Likewise. (encode_cc3): Likewise. (encode_cc2): Likewise. (encode_operand): Likewise. (tic54x_undefined_symbol): Likewise. include/ChangeLog: 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * opcode/tic54x.h (struct symbol_): typedef to tic54x_symbol instead of plain symbol.
2016-05-17Add DW_LANG_RustTom Tromey2-1/+10
include/ * dwarf2.h (enum dwarf_source_language) <DW_LANG_Rust, DW_LANG_Rust_old>: New constants. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@235643 138bc75d-0d04-0410-961f-82ee72b054a4
2016-05-11Add MIPS32 DSPr3 support.Matthew Fortune3-1/+9
bfd/ * elfxx-mips.c (print_mips_ases): Add DSPR3. binutils/ * readelf.c (print_mips_ases): Add DSPR3. gas/ * config/tc-mips.c (options): Add OPTION_DSPR3 and OPTION_NO_DSPR3. (md_longopts): Likewise. (md_show_usage): Add help for -mdspr3 and -mno-dspr3. (mips_ases): Define availability for DSPr3. (mips_ase_groups): Add ASE_DSPR3 to the DSP group. (mips_convert_ase_flags): Map ASE_DSPR3 to AFL_ASE_DSPR3. * doc/as.texinfo: Document -mdspr3, -mno-dspr3. Fix -mdspr2 formatting. * doc/c-mips.texi: Document -mdspr3, -mno-dspr3, .set dspr3 and .set nodspr3. Fix -mdspr2 formatting. * testsuite/gas/mips/mips32-dspr3.d: New file. * testsuite/gas/mips/mips32-dspr3.s: Likewise. * testsuite/gas/mips/mips.exp: Run mips32-dspr3 test. include/ * elf/mips.h (AFL_ASE_DSPR3): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_DSPR3. * opcode/mips.h (ASE_DSPR3): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and mips64r6. * mips-opc.c (D34): New macro. (mips_builtin_opcodes): Define bposge32c for DSPr3.
2016-05-10Use getters/setters to access ARM branch typeThomas Preud'homme2-3/+34
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ * elf32-arm.c (elf32_arm_size_stubs): Use new macros ARM_GET_SYM_BRANCH_TYPE and ARM_SET_SYM_BRANCH_TYPE to respectively get and set branch type of a symbol. (bfd_elf32_arm_process_before_allocation): Likewise. (elf32_arm_relocate_section): Likewise and fix identation along the way. (allocate_dynrelocs_for_symbol): Likewise. (elf32_arm_finish_dynamic_symbol): Likewise. (elf32_arm_swap_symbol_in): Likewise. (elf32_arm_swap_symbol_out): Likewise. gas/ * config/tc-arm.c (arm_adjust_symtab): Use ARM_SET_SYM_BRANCH_TYPE to set branch type of a symbol. gdb/ * arm-tdep.c (arm_elf_make_msymbol_special): Use ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol. include/ * arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE enumerator. (NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro. (ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise. (ARM_SYM_BRANCH_TYPE): Replace by ... (ARM_GET_SYM_BRANCH_TYPE): This and ... (ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether BFD_ASSERT is defined or not. ld/ * emultempl/armelf.em (gld${EMULATION_NAME}_finish): Use ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol. opcodes/ * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol. (print_insn): Likewise.
2016-05-10Add support for ARMv8-M Mainline with DSP extensionThomas Preud'homme2-0/+5
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ (elf32_arm_merge_eabi_attributes): Add merging logic for Tag_DSP_extension. binutils/ * readelf.c (display_arm_attribute): Add output for Tag_DSP_extension. (arm_attr_public_tags): Define DSP_extension attribute. gas/ * NEWS: Document ARMv8-M and ARMv8-M Security and DSP Extensions. * config/tc-arm.c (arm_ext_dsp): New feature for Thumb DSP instructions. (arm_extensions): Add dsp extension for ARMv8-M Mainline. (aeabi_set_public_attributes): Memorize the feature bits of the architecture selected for Tag_CPU_arch. Use it to set Tag_DSP_extension to 1 for ARMv8-M Mainline with DSP extension. (arm_convert_symbolic_attribute): Define Tag_DSP_extension. * testsuite/gas/arm/arch7em-bad.d: Rename to ... * testsuite/gas/arm/arch7em-bad-1.d: This. * testsuite/gas/arm/arch7em-bad-2.d: New file. * testsuite/gas/arm/arch7em-bad-3.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-2.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-3.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-5.d: Likewise. * testsuite/gas/arm/attr-march-armv8m.main.dsp.d: Likewise. include/ * elf/arm.h (Tag_DSP_extension): Define. ld/ * testsuite/ld-arm/arm-elf.exp (EABI attribute merging 10 (DSP)): New test. * testsuite/ld-arm/attr-merge-10b-dsp.s: New file. * testsuite/ld-arm/attr-merge-10-dsp.attr: Likewise.
2016-05-10Allow extension availability to depend on several architecture bitsThomas Preud'homme2-0/+10
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (struct arm_option_extension_value_table): Make allowed_archs an array with 2 entries. (ARM_EXT_OPT): Adapt to only fill the first entry of allowed_archs. (ARM_EXT_OPT2): New macro filling the two entries of allowed_archs. (arm_extensions): Use separate entries in allowed_archs when several archs are allowed to use an extension and change ARCH_ANY in ARM_ARCH_NONE in allowed_archs. (arm_parse_extension): Check that, for each allowed_archs entry, all bits are set in the current architecture, ignoring ARM_ANY entries. (s_arm_arch_extension): Likewise. include/ * arm.h (ARM_FSET_CPU_SUBSET): Define macro.
2016-05-10Add support for ARMv8-M security extensions instructionsThomas Preud'homme2-1/+11
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (arm_ext_m): Add feature bit ARM_EXT2_V8M_MAIN. (arm_ext_v8m_main): New feature set for bit ARM_EXT2_V8M_MAIN. (arm_ext_v8m_m_only): New feature set for instructions in ARMv8-M not shared with a non M profile architecture. (do_rn): New function. (known_t32_only_insn): Check opcode against arm_ext_v8m_m_only rather than arm_ext_v8m. (v7m_psrs): Add ARMv8-M security extensions new special registers. (insns): Add ARMv8-M Security Extensions instructions. (aeabi_set_public_attributes): Use arm_ext_v8m_m_only instead of arm_ext_v8m_m to decide the profile and the Thumb ISA. * testsuite/gas/arm/archv8m-cmse.s: New file. * testsuite/gas/arm/archv8m-cmse-main.s: Likewise.. * testsuite/gas/arm/archv8m-cmse-msr.s: Likewise. * testsuite/gas/arm/any-cmse.d: Likewise. * testsuite/gas/arm/any-cmse-main.d: Likewise. * testsuite/gas/arm/archv8m-cmse-base.d: Likewise. * testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise. * testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise. * testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise. * testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise. include/ * opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit. (ARM_AEXT2_V8M_MAIN): New architecture extension feature set. (ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M for the high core bits. opcodes/ * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M Mainline Security Extensions instructions. (thumb_opcodes): Add entries for narrow ARMv8-M Security Extensions instructions. (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions instructions. (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions special registers.
2016-05-04[ARC] Add SYNTAX_NOP and SYNTAX_1OP for extension instructionsClaudiu Zissulescu2-2/+18
gas/ 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (syntaxclass): Add SYNTAX_NOP and SYNTAX_1OP. (arc_extinsn): Handle new introduced syntax. * testsuite/gas/arc/textinsn1op.d: New file. * testsuite/gas/arc/textinsn1op.s: Likewise. * doc/c-arc.texi: Document SYNTAX_NOP and SYNTAX_1OP. opcodes/ 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com> * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP. (arcExtMap_genOpcode): Likewise. * arc-opc.c (arg_32bit_rc): Define new variable. (arg_32bit_u6): Likewise. (arg_32bit_limm): Likewise. include/ 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (ARC_SYNTAX_1OP): Declare (ARC_SYNTAX_NOP): Likewsie. (ARC_OP1_MUST_BE_IMM): Update defined value. (ARC_OP1_IMM_IMPLIED): Likewise. (arg_32bit_rc, arg_32bit_u6, arg_32bit_limm): Declare.
2016-04-28Add support to AArch64 disassembler for verifying instructions. Add ↵Nick Clifton2-0/+8
verifier for LDPSW. PR target/19722 opcodes * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present. * aarch64-opc.c (verify_ldpsw): New function. * aarch64-opc.h (verify_ldpsw): New prototype. * aarch64-tbl.h: Add initialiser for verifier field. (LDPSW): Set verifier to verify_ldpsw. binutils* testsuite/binutils-all/aarch64/illegal.s: New test. * testsuite/binutils-all/aarch64/illegal.d: New test driver. include * opcode/aarch64.h (struct aarch64_opcode): Add verifier field.
2016-04-27Cache result of scan for __start_* and __stop_* sectionsAlan Modra2-6/+20
include/ * bfdlink.h (struct bfd_link_hash_entry): Add "section" field to undef. Formatting. bfd/ * elflink.c (_bfd_elf_is_start_stop): New function. (_bfd_elf_gc_mark_rsec): Use it. * elf-bfd.h (_bfd_elf_is_start_stop): Declare.
2016-04-21Add support for non-ELF targets to check their relocs.Nick Clifton2-0/+9
bfd * aout-adobe.c: Use _bfd_generic_link_check_relocs. * aout-target.h: Likewise. * aout-tic30.c: Likewise. * binary.c: Likewise. * bout.c: Likewise. * coff-alpha.c: Likewise. * coff-rs6000.c: Likewise. * coff64-rs6000.c: Likewise. * coffcode.h: Likewise. * i386msdos.c: Likewise. * i386os9k.c: Likewise. * ieee.c: Likewise. * ihex.c: Likewise. * libbfd-in.h: Likewise. * libecoff.h: Likewise. * mach-o-target.c: Likewise. * mmo.c: Likewise. * nlm-target.h: Likewise. * oasys.c: Likewise. * pef.c: Likewise. * plugin.c: Likewise. * ppcboot.c: Likewise. * som.c: Likewise. * srec.c: Likewise. * tekhex.c: Likewise. * versados.c: Likewise. * vms-alpha.c: Likewise. * xsym.c: Likewise. * elfxx-target.h: Use _bfd_elf_link_check_relocs. * linker.c (bfd_link_check_relocs): New function. (_bfd_generic_link_check_relocs): New function. * targets.c (BFD_JUMP_TABLE_LINK): Add initialization of _bfd_link_check_relocs field. (struct bfd_target)L Add _bfd_link_check_relocs field. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. ld * ldlang.c (lang_check_relocs): Use bfd_link_check_relocs in prefernce to _bfd_elf_link_check_relocs. Drop test for ELF targets. Do not stop the checks when problems are encountered. include * bfdlink.h: Add prototype for bfd_link_check_relocs.
2016-04-20Check ELF relocs after opening all input filesH.J. Lu2-0/+8
Delaying checking ELF relocations until opening all input files so that symbol information is final when relocations are checked. This is only enabled for x86 targets. bfd/ * elf-bfd.h (_bfd_elf_link_check_relocs): New. * elflink.c (_bfd_elf_link_check_relocs): New function. (elf_link_add_object_symbols): Call _bfd_elf_link_check_relocs if check_relocs_after_open_input is FALSE. include/ * bfdlink.h (bfd_link_info): Add check_relocs_after_open_input. ld/ * emulparams/elf32_x86_64.sh (CHECK_RELOCS_AFTER_OPEN_INPUT): New. * emulparams/elf_i386.sh (CHECK_RELOCS_AFTER_OPEN_INPUT): Likewise. * emulparams/elf_i386_be.sh (CHECK_RELOCS_AFTER_OPEN_INPUT): Likewise. * emulparams/elf_i386_chaos.sh (CHECK_RELOCS_AFTER_OPEN_INPUT): Likewise. * emulparams/elf_i386_ldso.sh (CHECK_RELOCS_AFTER_OPEN_INPUT): Likewise. * emulparams/elf_i386_vxworks.sh (CHECK_RELOCS_AFTER_OPEN_INPUT): Likewise. * emulparams/elf_x86_64.sh (CHECK_RELOCS_AFTER_OPEN_INPUT): Likewise. * emulparams/i386nto.sh (CHECK_RELOCS_AFTER_OPEN_INPUT): Likewise. * emultempl/elf32.em (gld${EMULATION_NAME}_before_parse): Set check_relocs_after_open_input to TRUE if CHECK_RELOCS_AFTER_OPEN_INPUT is yes. (gld${EMULATION_NAME}_after_open): Call _bfd_elf_link_check_relocs on all inputs if check_relocs_after_open_input is TRUE.
2016-04-20arc: Fix relocation formula for ARC_NPS_CMEM16 relocationAndrew Burgess2-1/+5
The ME modifier was missing from the relocation formula for the ARC_NPS_CMEM16 relocation, and as such the relocation would not patch correctly on little endian targets. include/ChangeLog: * elf/arc-reloc.def (ARC_NPS_CMEM16): Add ME modifier to formula.
2016-04-19opcodes/arc: Add yet more nps instructionsAndrew Burgess2-1/+5
Add some more arc/nps400 instructions and the associated operands. There's also a test added into the assembler. gas/ChangeLog: * testsuite/gas/arc/nps400-6.d: New file. * testsuite/gas/arc/nps400-6.s: New file. include/ChangeLog: * opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8. opcodes/ChangeLog: * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb, fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, and qcmp instructions. * arc-opc.c (insert_nps_bitop_size): Delete. (extract_nps_bitop_size): Delete. (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use. (extract_nps_qcmp_m3): Define. (extract_nps_qcmp_m2): Define. (extract_nps_qcmp_m1): Define. (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL. (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE, NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST, NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and NPS_QCMP_M3.
2016-04-19opcodes/arc: Add more nps instructionsAndrew Burgess2-0/+6
Add dctcp, dcip, dcet, and dcacl instructions. gas/ChangeLog: * testsuite/gas/arc/nps400-4.d: New file. * testsuite/gas/arc/nps400-4.s: New file. * testsuite/gas/arc/nps400-5.d: New file. * testsuite/gas/arc/nps400-5.s: New file. include/ChangeLog: * opcode/arc.h (insn_class_t): Add NET and ACL class. opcodes/ChangeLog: * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
2016-04-14arc/nps400 : New cmem instructions and associated relocationAndrew Burgess3-0/+15
Add support for arc/nps400 cmem instructions, these load and store instructions are hard-wired to access "0x57f00000 + 16-bit-offset". Supporting this relocation required some additions to the arc relocation handling in the bfd library, as well as the standard changes required to add a new relocation type. There's a test of the new instructions in the assembler, and a test of the relocation in the linker. bfd/ChangeLog: * reloc.c: Add BFD_RELOC_ARC_NPS_CMEM16 entry. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf32-arc.c: Add 'opcode/arc.h' include. (struct arc_relocation_data): Add symbol_name. (arc_special_overflow_checks): New function. (arc_do_relocation): Use arc_special_overflow_checks, reindent as required, add an extra comment. (elf_arc_relocate_section): Setup symbol_name in reloc_data. gas/ChangeLog: * testsuite/gas/arc/nps400-3.d: New file. * testsuite/gas/arc/nps400-3.s: New file. include/ChangeLog: * elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc. * opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define. ld/ChangeLog: * testsuite/ld-arc/arc.exp: New file. * testsuite/ld-arc/nps-1.s: New file. * testsuite/ld-arc/nps-1a.d: New file. * testsuite/ld-arc/nps-1b.d: New file. * testsuite/ld-arc/nps-1b.err: New file. opcodes/ChangeLog: * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst instructions. * arc-opc.c (insert_nps_cmem_uimm16): New function. (extract_nps_cmem_uimm16): New function. (arc_operands): Add NPS_XLDST_UIMM16 operand.
2016-04-12Add support for .extCondCode, .extCoreRegister and .extAuxRegister.Claudiu Zissulescu2-3/+32
gas/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/textauxregister.d: New file. * testsuite/gas/arc/textauxregister.s: Likewise. * testsuite/gas/arc/textcondcode.d: Likewise. * testsuite/gas/arc/textcondcode.s: Likewise. * testsuite/gas/arc/textcoreregister.d: Likewise. * testsuite/gas/arc/textcoreregister.s: Likewise. * testsuite/gas/arc/textpseudoop.d: Likewise. * testsuite/gas/arc/textpseudoop.s: Likewise. * testsuite/gas/arc/ld2.d: Update test. * testsuite/gas/arc/st.d: Likewise. * testsuite/gas/arc/taux.d: Likewise. * doc/c-arc.texi (ARC Directives): Add .extCondCode, .extCoreRegister and .extAuxRegister documentation. * config/tc-arc.c (arc_extcorereg): New function. (md_pseudo_table): Add .extCondCode, .extCoreRegister and .extAuxRegister pseudo-ops. (extRegister_t): New type. (ext_condcode, arc_aux_hash): New global variable. (find_opcode_match): Check for extensions. (preprocess_operands): Likewise. (md_begin): Add aux registers in a hash. (assemble_insn): Update use arc_flags member. (tokenize_extregister): New function. (create_extcore_section): Likewise. * config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Increase to 10. (arc_flags): Delete code, add flgp. include/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (flag_class_t): Update. (ARC_OPCODE_NONE): Define. (ARC_OPCODE_ARCALL): Likewise. (ARC_OPCODE_ARCFPX): Likewise. (ARC_REGISTER_READONLY): Likewise. (ARC_REGISTER_WRITEONLY): Likewise. (ARC_REGISTER_NOSHORT_CUT): Likewise. (arc_aux_reg): Add cpu. opcodes/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (find_format): Check for extension flags. (print_flags): New function. (print_insn_arc): Update for .extCondCode, .extCoreRegister and .extAuxRegister. * arc-ext.c (arcExtMap_coreRegName): Use LAST_EXTENSION_CORE_REGISTER. (arcExtMap_coreReadWrite): Likewise. (dump_ARC_extmap): Update printing. * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag. (arc_aux_regs): Add cpu field. * arc-regs.h: Add cpu field, lower case name aux registers. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-12Add support for .extInstruction pseudo-op.Claudiu Zissulescu2-24/+90
gas/ 2016-04-04 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/textinsn-errors.d: New File. * testsuite/gas/arc/textinsn-errors.err: Likewise. * testsuite/gas/arc/textinsn-errors.s: Likewise. * testsuite/gas/arc/textinsn2op.d: Likewise. * testsuite/gas/arc/textinsn2op.s: Likewise. * testsuite/gas/arc/textinsn2op01.d: Likewise. * testsuite/gas/arc/textinsn2op01.s: Likewise. * testsuite/gas/arc/textinsn3op.d: Likewise. * testsuite/gas/arc/textinsn3op.s: Likewise. * doc/c-arc.texi (ARC Directives): Add .extInstruction documentation. * config/tc-arc.c (arcext_section): New variable. (arc_extinsn): New function. (md_pseudo_table): Add .extInstruction pseudo op. (attributes_t): New type. (suffixclass, syntaxclass, syntaxclassmod): New constant structures. (find_opcode_match): Remove arc_num_opcodes. (md_begin): Likewise. (tokenize_extinsn): New function. (arc_set_ext_seg): Likewise. (create_extinst_section): Likewise. include/ 2016-04-04 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (arc_num_opcodes): Remove. (ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM) (ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND) (ARC_SUFFIX_FLAG): Define. (flags_none, flags_f, flags_cc, flags_ccf): Declare. (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc) (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6) (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm) (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm) (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12) (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc) (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm) (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6) (arg_32bit_limms12, arg_32bit_limmlimm): Likewise. opcodes/ 2016-04-04 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf): Initialize. (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc) (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6) (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm) (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm) (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12) (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc) (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm) (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6) (arg_32bit_limms12, arg_32bit_limmlimm): Likewise. (arc_opcode arc_opcodes): Null terminate the array. (arc_num_opcodes): Remove. * arc-ext.h (INSERT_XOP): Define. (extInstruction_t): Likewise. (arcExtMap_instName): Delete. (arcExtMap_insn): New function. (arcExtMap_genOpcode): Likewise. * arc-ext.c (ExtInstruction): Remove. (create_map): Zero initialize instruction fields. (arcExtMap_instName): Remove. (arcExtMap_insn): New function. (dump_ARC_extmap): More info while debuging. (arcExtMap_genOpcode): New function. * arc-dis.c (find_format): New function. (print_insn_arc): Use find_format. (arc_get_disassembler): Enable dump_ARC_extmap only when debugging. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-05[ARC] Fix support for double assist instructions.Claudiu Zissulescu2-3/+16
opcodes/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * arc-regs.h: Add a new subclass field. Add double assist accumulator register values. * arc-tbl.h: Use DPA subclass to mark the double assist instructions. Use DPX/SPX subclas to mark the FPX instructions. * arc-opc.c (RSP): Define instead of SP. (arc_aux_regs): Add the subclass field. include/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (DPA, DPX, SPX): New subclass enums. (ARC_FPUDA): Define. (arc_aux_reg): Add new field. gas/ 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (is_code_density_p): Compare directly the subclass field. (is_spfp_p, is_dpfp_p, is_spfp_p): Define. (check_cpu_feature): New function. (find_opcode_match): Use check_cpu_feature function. (preprocess_operands): Likewise. (md_parse_option): Use mfpuda, mdpfp, mspfp options. * testsuite/gas/arc/tdpfp.d: New file. * testsuite/gas/arc/tfpuda.d: Likewise. * testsuite/gas/arc/tfpx.s: Likewise.
2016-04-05[ARC] 24 bit reloc and overflow detection fix.Claudiu Zissulescu2-1/+21
bfd/ 2016-04-05 Cupertino Miranda <cmiranda@synopsys.com> * elf32-arc.c (name_for_global_symbol): Changed assert. (get_replace_function): Created.: (struct arc_relocation_data): Changed to signed types. (defines S, L, P, PDATA): Casted to signed type. (defines SECTSTART, _SDA_BASE_, TLS_REL): Likewise. (PRINT_DEBUG_RELOC_INFO_BEFORE): Changed. (arc_do_relocation): Changed. include/ 2016-04-05 Cupertino Miranda <cmiranda@synopsys.com> * opcode/arc-func.h (replace_bits24): Changed. (replace_bits24_be): Created.
2016-03-29[ARC] Add support for Quarkse opcodes.Claudiu Zissulescu2-0/+89
gas/ 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/ext2op.d: New file. * testsuite/gas/arc/ext2op.s: Likewise. * testsuite/gas/arc/ext3op.d: Likewise. * testsuite/gas/arc/ext3op.s: Likewise. opcodes/ 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com> * arc-tbl.h (invld07): Remove. * arc-ext-tbl.h: New file. * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove. * arc-opc.c (arc_opcodes): Add ext-tbl include. include/ 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (insn_subclass_t): Add QUARKSE subclass. (FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP) (INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL) (INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU) (INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS) (INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL) (INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC) (MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC) (MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU) (MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS) (MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL) (MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C) (INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL) (MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
2016-03-22make more variables constTrevor Saunders3-2/+7
gas/ChangeLog: 2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-h8300.c (h8300_elf_section): Add const qualifiers. * config/tc-ia64.c (obj_elf_vms_common): Likewise. * config/tc-m68hc11.c (md_begin): Likewise. (print_opcode_list): Likewise. * config/tc-msp430.c (msp430_section): Likewise. * config/tc-score.c (struct s3_insn_to_dependency): Likewise. (s3_build_dependency_insn_hsh): Likewise. * config/tc-score7.c (struct s7_insn_to_dependency): Likewise. (s7_build_dependency_insn_hsh): Likewise. * config/tc-tic4x.c: Likewise. * config/tc-tic54x.c (tic54x_set_default_include): Likewise. (subsym_get_arg): Likewise. * config/tc-xtensa.c (struct suffix_reloc_map): Likewise. (get_directive): Likewise. (cache_literal_section): Likewise. * config/xtensa-relax.c: Likewise. * symbols.c (symbol_create): Likewise. (local_symbol_make): Likewise. (symbol_relc_make_expr): Likewise. include/ChangeLog: 2016-03-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * opcode/i960.h: Add const qualifiers. * opcode/tic4x.h (struct tic4x_inst): Likewise.
2016-03-21arc/nps400: Add first nps400 instructionsAndrew Burgess2-0/+5
Adds the first few nps400 instructions. gas/ChangeLog: * testsuite/gas/arc/nps400-0.d: New file. * testsuite/gas/arc/nps400-0.s: New file. * testsuite/gas/arc/nps400-1.d: New file. * testsuite/gas/arc/nps400-1.s: New file. include/ChangeLog: * opcodes/arc.h (insn_class_t): Add BITOP type. opcodes/ChangeLog: * arc-nps400-tbl.h: New file. * arc-opc.c: Add top level comment. (insert_nps_3bit_dst): New function. (extract_nps_3bit_dst): New function. (insert_nps_3bit_src2): New function. (extract_nps_3bit_src2): New function. (insert_nps_bitop_size): New function. (extract_nps_bitop_size): New function. (arc_flag_operands): Add nps400 entries. (arc_flag_classes): Add nps400 entries. (arc_operands): Add nps400 entries. (arc_opcodes): Add nps400 include.
2016-03-21arc/opcodes: Use flag operand class to handle multiple flag matchesAndrew Burgess2-9/+14
When parsing the operand instruction flags we don't currently detect the case where multiple flags are provided from the same class set, these will be accepted and the bit values merged together, resulting in the wrong instruction being assembled. For example: adc.n.eq r0,r0,r2 Will assemble without error, yet, upon disassembly, the instruction will actually be: adc.c r0,r0,r2 In a later commit the concept of required flags will be introduced. Required flags are just like normal instruction flags, except that they must be present for the instruction to match. Adding this will allow for simpler instructions in the instruction table, and allow for more sharing of operand extraction and insertion functions. To solve both of the above issues (multiple flags being invalid, and required flags), this commit reworks the flag class mechanism. Currently the flag class is never used. Each instruction can reference multiple flag classes, each flag class has a class type and a set of flags. However, at present, the class type is never used. The current values identify the type of instruction that the flag will be used in, but this is not required information. Instead, this commit discards the old flag classes, and introduces 3 new classes. The first F_CLASS_NONE, is just a NULL marker value, and is only used in the NULL marker flag class. The other two flag classes are F_FLAG_OPTIONAL, and F_FLAG_REQUIRED. The class F_FLAG_OPTIONAL has the property that at most one of the flags in the flag set for that class must be present in the instruction. The "at most" one means that no flags being present is fine. The class F_FLAG_REQUIRED is not currently used, but will be soon. With this class, exactly one of the flags from this class must be present in the instruction. If the flag class contains a single flag, then of course that flag must be present. However, if the flag class contained two or more, then one, and only one of them must be present. gas/ChangeLog: * config/tc-arc.c (find_opcode_match): Move lnflg, and i declarations to start of block. Reset code on all flags before attempting to match them. Handle multiple hits on the same flag. Handle flag class. * testsuite/gas/arc/asm-errors.d: New file. * testsuite/gas/arc/asm-errors.err: New file. * testsuite/gas/arc/asm-errors.s: New file. include/ChangeLog: * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3 new classes instead. opcodes/ChangeLog: * arc-opc.c (arc_flag_classes): Convert all flag classes to use the new class enum values.
2016-03-21arc: Add nps400 machine type, and assembler flag.Andrew Burgess3-0/+7
This commit introduces the nps400 machine type as a variant of arc. There's a new flag in the assembler to select this machine type. All other changes are just adding handling of the new machine type into the relevant places. The nps400 is an arc700 variant with some vendor specific instructions added into the instruction set. This commit does not add any of the new instructions, this is just laying the groundwork for future commits. However, in preparation for these new instructions a new opcode define for nps400 has been added to include/opcode/arc.h, this new opcode define is used in the assembler and disassembler along with the existing define for arc700 such that when assembling and disassembling for nps400 the user will have access to all arc700 instructions and all the nps400 vendor extension instructions. bfd/ChangeLog: * archures.c (bfd_mach_arc_nps400): Define. * bfd-in2.h: Regenerate. * cpu-arc.c (arch_info_struct): New entry for nps400, renumber some existing entries to make space. * elf32-arc.c (arc_elf_object_p): Add nps400 case. (arc_elf_final_write_processing): Likewise. binutils/ChangeLog: * readelf.c (decode_ARC_machine_flags): Handle nps400. gas/ChangeLog: * config/tc-arc.c (cpu_types): Add nps400 entry. (check_zol): Handle nps400. include/ChangeLog: * elf/arc.h (E_ARC_MACH_NPS400): Define. * opcode/arc.h (ARC_OPCODE_NPS400): Define. opcodes/ChangeLog: * arc-dis.c (print_insn_arc): Handle nps400.
2016-03-21arc: Remove EF_ARC_CPU_GENERIC constant.Andrew Burgess2-4/+6
The constant EF_ARC_CPU_GENERIC is defined in the include/elf/arc.h file, and is used in a few places in binutils, however, this constant should never make it into the elf header flags; we always set a valid cpu type in the assembler, which should then be copied over during linking. There are some non-gnu arc compilers that don't write an architecture type into the e_flags field, instead leaving the field as 0, which is the EF_ARC_CPU_GENERIC value. This non-gnu compiler uses the machine type to distinguish between the old and newer arc architectures, setting the machine type to EM_ARC_COMPACT for old arc600, arc601, and arc700 architectures, while using EM_ARC_COMPACT2 for newer arcem and archs architectures. Previously when displaying the machine flags for an older EM_ARC_COMPACT machine, if the e_flags had not been filled in, then we relied on the default case statement to display the message "Generic ARCompact", while in the EM_ARC_COMPACT2 case we specifically handled EF_ARC_CPU_GENERIC to print "ARC Generic", leaving the default case to print a message about unrecognised cpu flag. After this commit EF_ARC_CPU_GENERIC has been removed, for both machine types EM_ARC_COMPACT and EM_ARC_COMPACT2 we now rely on the default case statement to handle the situation where the e_flags has not been filled in. The message displayed is now "Unknown ARCompact" (for older arc architectures) and "Unknown ARC" (for the newer architectures). The switch from "Generic" to "Unknown" in the message string is for clarity, calling the file "Generic" can give the impression that the file is compiled for a common sub-set of the architectures, and would therefore run on any type of machine (or at least any type of new or old machine depending on if the machine type is ARC or ARCv2). However, this was not what "Generic" meant, it really meant "Unknown", so that's what we now say. As part of the merging of the readelf flag reading code, I have unified the strings used in displaying the ELF ABI. This means that for older arc machines (arc600, arc601, and arc700) the string used for the original ABI, and ABIv2 have changed, the current ABIv3 remains the same. For the newer architectures (arcem and archs) the abi strings remain unchanged in all cases. bfd/ChangeLog: * elf32-arc.c (arc_elf_print_private_bfd_data): Remove use of EF_ARC_CPU_GENERIC. (arc_elf_final_write_processing): Don't bother setting cpu field in e_flags, this will have been set elsewhere. binutils/ChangeLog: * readelf.c (get_machine_flags): Move arc processing into... (decode_ARC_machine_flags): ... new function. Remove use of EF_ARC_CPU_GENERIC, change default case from "generic arc" to "unknown arc". Merged ABI printing between two machine types. gas/ChangeLog: * config/tc-arc.c (arc_select_cpu): Remove use of EF_ARC_CPU_GENERIC. include/ChangeLog: * elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
2016-03-21arc: Remove duplicated constant in include/elf/arc.hAndrew Burgess2-5/+5
In the include/elf/arc.h there are two constants that mask out the machine architecture field. One is used lots (EF_ARC_MACH_MSK), the other is used only once (EF_ARC_MACH). Remove EF_ARC_MACH. bfd/ChangeLog: * elf32-arc.c (arc_elf_final_write_processing): Switch to using EF_ARC_MACH_MSK. include/ChangeLog: * elf/arc.h (EF_ARC_MACH): Delete. (EF_ARC_MACH_MSK): Remove out of date comment.
2016-03-21arc/gas: default mach is arc700, initialised in md_beginAndrew Burgess2-5/+4
This commit restructures the selection of the default cpu/mach so that the choice is made from md_begin (if the user has not provided a command line choice). This will reduce the amount of change needed in a later patch. At the request of Synopsys, the default architecture changes to ARC700 from this commit, previously the default was a non-existent super-architecture that contained all instructions from all arc variants. There's some clean up associated with removing the default merged architecture, and a small test fix now that the default is ARC700. binutils/ChangeLog: * testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700 to the architecture list. gas/ChangeLog: * config/tc-arc.c (arc_target): Delay initialisation until arc_select_cpu. (arc_target_name): Likewise. (arc_features): Likewise. (arc_mach_type): Likewise. (cpu_types): Remove "all" entry. (arc_select_cpu): New function, most of the content is from... (md_parse_option): ... here. Call new arc_select_cpu. (md_begin): Call arc_select_cpu if needed, default is now arc700. include/ChangeLog: * opcode/arc.h (ARC_OPCODE_BASE): Delete. opcodes/ChangeLog: * arc-opc.c (BASE): Delete.
2016-03-15Add -z noreloc-overflow option to x86-64 ldH.J. Lu2-0/+8
Add -z noreloc-overflow command-line option to the x86-64 ELF linker to disable relocation overflow check. This can be used to avoid relocation overflow check if there will be no dynamic relocation overflow at run-time. bfd/ PR ld/19807 * elf64-x86-64.c (elf_x86_64_relocate_section): Check no_reloc_overflow_check to diable R_X86_64_32/R_X86_64_32S relocation overflow check. include/ PR ld/19807 * bfdlink.h (bfd_link_info): Add no_reloc_overflow_check. ld/ PR ld/19807 * Makefile.am (ELF_X86_DEPS): Add $(srcdir)/emulparams/reloc_overflow.sh. * Makefile.in: Regenerated. * NEWS: Mention -z noreloc-overflow. * ld.texinfo: Document -z noreloc-overflow. * emulparams/elf32_x86_64.sh: Source ${srcdir}/emulparams/reloc_overflow.sh. * emulparams/elf_x86_64.sh: Likewise. * emulparams/reloc_overflow.sh: New file. * testsuite/ld-x86-64/pr19807-1.s: New file. * testsuite/ld-x86-64/pr19807-1a.d: Likewise. * testsuite/ld-x86-64/pr19807-1b.d: Likewise. * testsuite/ld-x86-64/pr19807-2.s: Likewise. * testsuite/ld-x86-64/pr19807-2a.d: Likewise. * testsuite/ld-x86-64/pr19807-2b.d: Likewise. * testsuite/ld-x86-64/pr19807-2c.d: Likewise. * testsuite/ld-x86-64/pr19807-2d.d: Likewise. * testsuite/ld-x86-64/pr19807-2e.d: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run PR ld/19807 tests.
2016-03-08[ARC] Allow non-instruction relocations within .text sectionsClaudiu Zissulescu3-41/+77
bfd/ 2016-03-08 Cupertino Miranda <Cupertino.Miranda@synopsys.com> Andrew Burgess <andrew.burgess@embecosm.com> * elf32-arc.c (arc_bfd_get_32): Becomes an alias for bfd_get_32. (arc_bfd_put_32): Becomes an alias for bfd_put_32. (arc_elf_howto_init): Added assert to validate relocations. (get_middle_endian_relocation): Delete. (middle_endian_convert): New function. (ME): Redefine, now does nothing. (IS_ME): New define. (arc_do_relocation): Extend the attached 'ARC_RELOC_HOWTO' definition to call middle_endian_convert. Add a new local variable and make use of this throughout. Added call to arc_bfd_get_8 and arc_bfd_put_8 for 8 bit relocations. gas/ 2016-03-08 Andrew Burgess <andrew.burgess@embecosm.com> * testsuite/gas/arc/inline-data-1.d: New file. * testsuite/gas/arc/inline-data-1.s: New file. include/ 2016-03-08 Cupertino Miranda <Cupertino.Miranda@synopsys.com> Andrew Burgess <andrew.burgess@embecosm.com> * elf/arc-reloc.def: Add a call to ME within the formula for each relocation that requires middle-endian correction.
2016-03-07Add const qualifiers at various places.Trevor Saunders9-17/+31
opcodes * mcore-opc.h: Add const qualifiers. * microblaze-opc.h (struct op_code_struct): Likewise. * sh-opc.h: Likewise. * tic4x-dis.c (tic4x_print_indirect): Likewise. (tic4x_print_op): Likewise. include * opcode/dlx.h (struct dlx_opcode): Add const qualifiers. * opcode/h8300.h (struct h8_opcode): Likewise. * opcode/hppa.h (struct pa_opcode): Likewise. * opcode/msp430.h: Likewise. * opcode/spu.h (struct spu_opcode): Likewise. * opcode/tic30.h (struct _register): Likewise. * opcode/tic4x.h (struct tic4x_register): Likewise. (struct tic4x_cond): Likewise. (struct tic4x_indirect): Likewise. (struct tic4x_inst): Likewise. * opcode/visium.h (struct reg_entry): Likewise. gas * config/tc-arc.c: Add const qualifiers. * config/tc-h8300.c (md_begin): Likewise. * config/tc-ia64.c (print_prmask): Likewise. * config/tc-msp430.c (msp430_operands): Likewise. * config/tc-nds32.c (struct suffix_name): Likewise. (struct nds32_parse_option_table): Likewise. (struct nds32_set_option_table): Likewise. (do_pseudo_pushpopm): Likewise. (do_pseudo_pushpop_stack): Likewise. (nds32_relax_relocs): Likewise. (nds32_flag): Likewise. (struct nds32_hint_map): Likewise. (nds32_find_reloc_table): Likewise. (nds32_match_hint_insn): Likewise. * config/tc-s390.c: Likewise. * config/tc-sh.c (get_specific): Likewise. * config/tc-tic30.c: Likewise. * config/tc-tic4x.c (tic4x_inst_add): Likewise. (tic4x_indirect_parse): Likewise. * config/tc-vax.c (vax_cons): Likewise. * config/tc-z80.c (struct reg_entry): Likewise. * config/tc-epiphany.c (md_assemble): Adjust. (epiphany_assemble): New function. (epiphany_elf_section_rtn): Call do_align directly. (epiphany_elf_section_text): Likewise. * config/tc-ip2k.c (ip2k_elf_section_rtn): Likewise. (ip2k_elf_section_text): Likewise. * read.c (do_align): Make it not static. * read.h (do_align): New prototype.
2016-03-04Fix datestamps on ChangeLog entries to read 2015 instead of 2016.Cary Coutant1-1/+1
2016-03-04Add missing ChangeLog entries for commit 82838H.J. Lu1-0/+11
Fix gold/testsuite/plugin_layout_with_alignment.sh permission.
2016-03-04[ARM] Add feature check for ARMv8.1 AdvSIMD instructions.Matthew Wahab2-1/+7
gas/ 2016-03-04 Matthew Wahab <matthew.wahab@arm.com> * config/gas/tc-arm.c (fpu_neon_ext_v8_1): Restrict to the ARMv8.1 RDMA feature. (record_feature_use): New. (mark_feature_used): Use record_feature_use. (do_neon_qrdmlah): New. (insns): Use do_neon_qrdmlah for vqrdmlah and vqrdmlsh and variants. (arm_extensions): Put into alphabetical order. Re-indent "simd" and "rdma" entries. Fix the incorrect merge value for "+rdma". * testsuite/gas/arm/armv8-a+rdma-warning.d: New. * testsuite/gas/arm/armv8-a+rdma.d: Add assembler command line options. Make source file explicit. * testsuite/gas/arm/armv8-a+rdma.l: New. * testsuite/gas/arm/armv8-a+rdma.s: Remove .arch and .arch_extension directives. Fix white-space. * testsuite/gas/arm/armv8_1-a+simd.d: New. include/opcode 2016-03-04 Matthew Wahab <matthew.wahab@arm.com> * arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA. (ARM_CPU_HAS_FEATURE): Add comment. Change-Id: Ie19250e8fa50aed44e44ab40ff30b04b38bc1a3d
2016-03-03Add new plugin hooks to support querying section alignment and size.Cary Coutant1-1/+25
include/ 2016-03-03 Than McIntosh <thanm@google.com> * plugin-api.h: Add new hooks to the plugin transfer vector to to support querying section alignment and section size. (ld_plugin_get_input_section_alignment): New hook. (ld_plugin_get_input_section_size): New hook. (ld_plugin_tag): Add LDPT_GET_INPUT_SECTION_ALIGNMENT and LDPT_GET_INPUT_SECTION_SIZE. (ld_plugin_tv): Add tv_get_input_section_alignment and tv_get_input_section_size. gold/ 2016-03-03 Than McIntosh <thanm@google.com> * plugin.cc (Plugin::load): Include hooks for get_input_section_size and get_input_section_alignment in transfer vector. (get_input_section_alignment): New function. (get_input_section_size): New function. * testsuite/Makefile.am: Add plugin_layout_with_alignment.sh test. * testsuite/Makefile.in: [Regenerate.] * testsuite/plugin_section_alignment.cc: New test file. * testsuite/plugin_layout_with_alignment.cc: New test file. * testsuite/plugin_layout_with_alignment.sh: New test file.
2016-03-03get_symbols() plugin API tweak to support --start-lib/--end-lib.Evgenii Stepanov2-1/+6
Let the plugin know that a file is not being included in the link by returning LDPS_NO_SYMS from get_symbols(). include/ * plugin-api.h (enum ld_plugin_tag): Add LDPT_GET_SYMBOLS_V3. gold/ * plugin.h (Pluginobj::get_symbol_resolution_info): Add version parameter. * plugin.cc (get_symbols_v3): New function. (Plugin::load): Add LDPT_GET_SYMBOLS_V3. (Pluginobj::get_symbol_resolution_info): Return LDPS_NO_SYMS when using new version.
2016-02-26Add ChangeLog entries for PR ld/19645H.J. Lu1-0/+6
2016-02-26Properly implement STT_COMMONH.J. Lu1-0/+12
The BFD configure option, --enable-elf-stt-common, can't be to used to verify STT_COMMON implementation with the normal binutils build. Instead, this patch removes it from BFD. It adds --elf-stt-common=[no|yes] to ELF assembler/objcopy and adds -z common/-z nocommon to ld. A configure option, --enable-elf-stt-common, is added to gas to specify whether ELF assembler should generate common symbols with the STT_COMMON type by default. Since BSF_KEEP_G is never used, it is renamed to BSF_ELF_COMMON for ELF common symbols. bfd/ PR ld/19645 * bfd.c (bfd): Change flags to 20 bits. (BFD_CONVERT_ELF_COMMON): New. (BFD_USE_ELF_STT_COMMON): Likewise. (BFD_FLAGS_SAVED): Add BFD_CONVERT_ELF_COMMON and BFD_USE_ELF_STT_COMMON. (BFD_FLAGS_FOR_BFD_USE_MASK): Likewise. * configure.ac: Remove --enable-elf-stt-common. * elf.c (swap_out_syms): Choose STT_COMMON or STT_OBJECT for common symbol depending on BFD_CONVERT_ELF_COMMON and BFD_USE_ELF_STT_COMMON. * elfcode.h (elf_slurp_symbol_table): Set BSF_ELF_COMMON for STT_COMMON. * elflink.c (bfd_elf_link_mark_dynamic_symbol): Also check STT_COMMON. (elf_link_convert_common_type): New function. (elf_link_output_extsym): Choose STT_COMMON or STT_OBJECT for common symbol depending on BFD_CONVERT_ELF_COMMON and BFD_USE_ELF_STT_COMMON. Set sym.st_info after sym.st_shndx. * elfxx-target.h (TARGET_BIG_SYM): Add BFD_CONVERT_ELF_COMMON and BFD_USE_ELF_STT_COMMON to object_flags. (TARGET_LITTLE_SYM): Likewise. * syms.c (BSF_KEEP_G): Renamed to ... (BSF_ELF_COMMON): This. * bfd-in2.h: Regenerated. * config.in: Likewise. * configure: Likewise. binutils/ PR ld/19645 * NEWS: Mention --elf-stt-common= for objcopy. * doc/binutils.texi: Document --elf-stt-common= for objcopy. * objcopy.c (do_elf_stt_common): New. (command_line_switch): Add OPTION_ELF_STT_COMMON. (copy_options): Add --elf-stt-common=. (copy_usage): Add --elf-stt-common=. (copy_object): Also check do_elf_stt_common for ELF targets. (copy_file): Handle do_elf_stt_common. (copy_main): Handle OPTION_ELF_STT_COMMON. * readelf.c (apply_relocations): Support STT_COMMON. * testsuite/binutils-all/common-1.s: New file. * testsuite/binutils-all/common-1a.d: Likewise. * testsuite/binutils-all/common-1b.d: Likewise. * testsuite/binutils-all/common-1c.d: Likewise. * testsuite/binutils-all/common-1d.d: Likewise. * testsuite/binutils-all/common-1e.d: Likewise. * testsuite/binutils-all/common-1f.d: Likewise. * testsuite/binutils-all/common-2.s: Likewise. * testsuite/binutils-all/common-2a.d: Likewise. * testsuite/binutils-all/common-2b.d: Likewise. * testsuite/binutils-all/common-2c.d: Likewise. * testsuite/binutils-all/common-2d.d: Likewise. * testsuite/binutils-all/common-2e.d: Likewise. * testsuite/binutils-all/common-2f.d: Likewise. * testsuite/binutils-all/objcopy.exp (objcopy_test_elf_common_symbols): New proc. Run objcopy_test_elf_common_symbols for ELF targets gas/ PR ld/19645 * NEWS: Mention --enable-elf-stt-common and --elf-stt-common= for ELF assemblers. * as.c (flag_use_elf_stt_common): New. (show_usage): Add --elf-stt-common=. (option_values): Add OPTION_ELF_STT_COMMON. (std_longopts): Add --elf-stt-common=. (parse_args): Handle --elf-stt-common=. * as.h (flag_use_elf_stt_common): New. * config.in: Regenerated. * configure: Likewise. * configure.ac: Add --enable-elf-stt-common and define DEFAULT_GENERATE_ELF_STT_COMMON. * gas/write.c (write_object_file): Set BFD_CONVERT_ELF_COMMON and BFD_USE_ELF_STT_COMMON if flag_use_elf_stt_common is set. * doc/as.texinfo: Document --elf-stt-common=. * testsuite/gas/elf/common3.s: New file. * testsuite/gas/elf/common3a.d: Likewise. * testsuite/gas/elf/common3b.d: Likewise. * testsuite/gas/elf/common4.s: Likewise. * testsuite/gas/elf/common4a.d: Likewise. * testsuite/gas/elf/common4b.d: Likewise. * testsuite/gas/i386/dw2-compress-3b.d: Likewise. * testsuite/gas/i386/dw2-compressed-3b.d: Likewise. * testsuite/gas/elf/elf.exp: Run common3a, common3b, common4a and common4b. * testsuite/gas/i386/dw2-compress-3.d: Renamed to ... * testsuite/gas/i386/dw2-compress-3a.d: This. Pass --elf-stt-common=no to as. * testsuite/gas/i386/dw2-compressed-3.d: Renamed to ... * testsuite/gas/i386/dw2-compressed-3a.d: This. Pass --elf-stt-common=no to as. * testsuite/gas/i386/i386.exp: Run dw2-compress-3a, dw2-compress-3b, dw2-compressed-3a and dw2-compressed-3b instead of dw2-compress-3 and dw2-compressed-3. include/ PR ld/19645 * bfdlink.h (bfd_link_elf_stt_common): New enum. (bfd_link_info): Add elf_stt_common. ld/ PR ld/19645 * NEWS: Mention -z common/-z nocommon for ELF targets. * emultempl/elf32.em (gld${EMULATION_NAME}_handle_option): Handle -z common and -z nocommon. * ld.texinfo: Document -z common/-z nocommon. * lexsup.c (elf_shlib_list_options): Add -z common/-z nocommon. * testsuite/ld-elf/tls_common.exp: Test --elf-stt-common=no and --elf-stt-common=yes with assembler. * testsuite/ld-elfcomm/common-1.s: New file. * testsuite/ld-elfcomm/common-1a.d: Likewise. * testsuite/ld-elfcomm/common-1b.d: Likewise. * testsuite/ld-elfcomm/common-1c.d: Likewise. * testsuite/ld-elfcomm/common-1d.d: Likewise. * testsuite/ld-elfcomm/common-1e.d: Likewise. * testsuite/ld-elfcomm/common-1f.d: Likewise. * testsuite/ld-elfcomm/common-2.s: Likewise. * testsuite/ld-elfcomm/common-2a.d: Likewise. * testsuite/ld-elfcomm/common-2b.d: Likewise. * testsuite/ld-elfcomm/common-2c.d: Likewise. * testsuite/ld-elfcomm/common-2d.d: Likewise. * testsuite/ld-elfcomm/common-2e.d: Likewise. * testsuite/ld-elfcomm/common-2f.d: Likewise. * testsuite/ld-elfcomm/common-3a.rd: Likewise. * testsuite/ld-elfcomm/common-3b.rd: Likewise. * testsuite/ld-i386/pr19645.d: Likewise. * testsuite/ld-i386/pr19645.s: Likewise. * testsuite/ld-x86-64/largecomm-1.s: Likewise. * testsuite/ld-x86-64/largecomm-1a.d: Likewise. * testsuite/ld-x86-64/largecomm-1b.d: Likewise. * testsuite/ld-x86-64/largecomm-1c.d: Likewise. * testsuite/ld-x86-64/largecomm-1d.d: Likewise. * testsuite/ld-x86-64/largecomm-1e.d: Likewise. * testsuite/ld-x86-64/largecomm-1f.d: Likewise. * testsuite/ld-x86-64/pr19645.d: Likewise. * testsuite/ld-x86-64/pr19645.s: Likewise. * testsuite/ld-elfcomm/elfcomm.exp: Test --elf-stt-common=yes with assembler. (assembler_generates_commons): Removed. Run -z common/-z nocommon tests. Run *.d tests. * testsuite/ld-i386/i386.exp: Run pr19645. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-x86-64/dwarfreloc.exp: Test --elf-stt-common with assembler. Test STT_COMMON with readelf.
2016-02-26[x86] Resolve non-PIC undefweak symbols in executableH.J. Lu2-0/+11
For i386 and x86-64, non-PIC references to undefined weak symbols are resolved without dynamic relocation when creating executable. Resolved undefined weak symbols are removed from the dynamic symbol table in executable. One exception is on i386, we need resolved undefined weak symbols in the dynamic symbol table in PIE if input relocatable files contain branchs without PLT so that we can branch to 0 with dynamic relocation in text section. This makes behaviors of dynamic executable and position independent executable predictable with mixed PIC and non-PIC references to undefined weak symbols. If all references to undefined weak symbols are PIC, dynamic relocations against undefined weak symbols will be generated in executable unless -z nodynamic-undefined-weak is passed to linker. bfd/ PR ld/19636 PR ld/19704 PR ld/19719 * elf32-i386.c (UNDEFINED_WEAK_RESOLVED_TO_ZERO): New. (elf_i386_link_hash_entry): Add has_got_reloc and has_non_got_reloc. (elf_i386_link_hash_table): Add interp. (elf_i386_link_hash_newfunc): Initialize has_got_reloc and has_non_got_reloc. (elf_i386_copy_indirect_symbol): Copy has_got_reloc and has_non_got_reloc. (elf_i386_check_relocs): Set has_got_reloc and has_non_got_reloc. (elf_i386_fixup_symbol): New function. (elf_i386_pie_finish_undefweak_symbol): Likewise. (elf_i386_allocate_dynrelocs): Don't allocate space for dynamic relocations and discard relocations against resolved undefined weak symbols in executable. Don't make resolved undefined weak symbols in executable dynamic. Keep dynamic non-GOT/non-PLT relocation against undefined weak symbols in PIE. (elf_i386_size_dynamic_sections): Set interp to .interp section. (elf_i386_relocate_section): Don't generate dynamic relocations against resolved undefined weak symbols in PIE, except for R_386_PC32. (elf_i386_finish_dynamic_symbol): Keep PLT/GOT entries without dynamic PLT/GOT relocations for resolved undefined weak symbols. Don't generate dynamic relocation against resolved undefined weak symbol in executable. (elf_i386_finish_dynamic_sections): Call elf_i386_pie_finish_undefweak_symbol on all symbols in PIE. (elf_backend_fixup_symbol): New. * elf64-x86-64.c (UNDEFINED_WEAK_RESOLVED_TO_ZERO): New. (elf_x86_64_link_hash_entry): Add has_got_reloc and has_non_got_reloc. (elf_x86_64_link_hash_table): Add interp. (elf_x86_64_link_hash_newfunc): Initialize has_got_reloc and has_non_got_reloc. (elf_x86_64_copy_indirect_symbol): Copy has_got_reloc and has_non_got_reloc. (elf_x86_64_check_relocs): Set has_got_reloc and has_non_got_reloc. (elf_x86_64_fixup_symbol): New function. (elf_x86_64_pie_finish_undefweak_symbol): Likewise. (elf_x86_64_allocate_dynrelocs): Don't allocate space for dynamic relocations and discard relocations against resolved undefined weak symbols in executable. Don't make resolved undefined weak symbols in executable dynamic. (elf_x86_64_size_dynamic_sections): Set interp to .interp section. (elf_x86_64_relocate_section): Check relocation overflow for dynamic relocations against unresolved weak undefined symbols. Don't generate dynamic relocations against resolved weak undefined symbols in PIE. (elf_x86_64_finish_dynamic_symbol): Keep PLT/GOT entries without dynamic PLT/GOT relocations for resolved undefined weak symbols. Don't generate dynamic relocation against resolved undefined weak symbol in executable. (elf_x86_64_finish_dynamic_sections): Call elf_x86_64_pie_finish_undefweak_symbol on all symbols in PIE. (elf_backend_fixup_symbol): New. include/ PR ld/19636 PR ld/19704 PR ld/19719 * bfdlink.h (bfd_link_info): Add dynamic_undefined_weak. ld/ PR ld/19636 PR ld/19704 PR ld/19719 * Makefile.am (ELF_X86_DEPS): Add dynamic_undefined_weak.sh. * Makefile.in: Regenerated. * NEWS: Mention -z nodynamic-undefined-weak. * ld.texinfo: Document -z nodynamic-undefined-weak. * ldmain.c (main): Initialize dynamic_undefined_weak to -1. * emulparams/dynamic_undefined_weak.sh: New file. * emulparams/elf32_x86_64.sh: Source dynamic_undefined_weak.sh. * emulparams/elf_i386.sh: Likewise. * emulparams/elf_i386_be.sh: Likewise. * emulparams/elf_i386_chaos.sh: Likewise. * emulparams/elf_i386_ldso.sh: Likewise. * emulparams/elf_i386_vxworks.sh: Likewise. * emulparams/elf_iamcu.sh: Likewise. * emulparams/elf_k1om.sh: Likewise. * emulparams/elf_l1om.sh: Likewise. * emulparams/elf_x86_64.sh: Likewise. * emulparams/extern_protected_data.sh (PARSE_AND_LIST_OPTIONS): Append. (PARSE_AND_LIST_ARGS_CASE_Z): Likewise. * testsuite/ld-elf/pr19719a.c: New file. * testsuite/ld-elf/pr19719b.c: Likewise. * testsuite/ld-elf/pr19719c.c: Likewise. * testsuite/ld-elf/pr19719d.c: Likewise. * testsuite/ld-i386/pr19636-1.s: Likewise. * testsuite/ld-i386/pr19636-1a.d: Likewise. * testsuite/ld-i386/pr19636-1b.d: Likewise. * testsuite/ld-i386/pr19636-1c.d: Likewise. * testsuite/ld-i386/pr19636-1d-nacl.d: Likewise. * testsuite/ld-i386/pr19636-1d.d: Likewise. * testsuite/ld-i386/pr19636-1e.d: Likewise. * testsuite/ld-i386/pr19636-1f.d: Likewise. * testsuite/ld-i386/pr19636-1g.d: Likewise. * testsuite/ld-i386/pr19636-1h.d: Likewise. * testsuite/ld-i386/pr19636-1i.d: Likewise. * testsuite/ld-i386/pr19636-2.s: Likewise. * testsuite/ld-i386/pr19636-2a.d: Likewise. * testsuite/ld-i386/pr19636-2b.d: Likewise. * testsuite/ld-i386/pr19636-2c-nacl.d: Likewise. * testsuite/ld-i386/pr19636-2c.d: Likewise. * testsuite/ld-i386/pr19636-2d-nacl.d: Likewise. * testsuite/ld-i386/pr19636-2d.d: Likewise. * testsuite/ld-i386/pr19636-2e-nacl.d: Likewise. * testsuite/ld-i386/pr19636-2e.d: Likewise. * testsuite/ld-i386/pr19636-3.s: Likewise. * testsuite/ld-i386/pr19636-3a.d: Likewise. * testsuite/ld-i386/pr19636-3b.d: Likewise. * testsuite/ld-i386/pr19636-3c.d: Likewise. * testsuite/ld-i386/pr19636-3d.d: Likewise. * testsuite/ld-i386/pr19636-3e.d: Likewise. * testsuite/ld-i386/pr19636-3f.d: Likewise. * testsuite/ld-i386/pr19636-3g.d: Likewise. * testsuite/ld-i386/pr19636-4.s: Likewise. * testsuite/ld-i386/pr19636-4a.d: Likewise. * testsuite/ld-i386/pr19636-4b.d: Likewise. * testsuite/ld-i386/pr19636-4c.d: Likewise. * testsuite/ld-i386/pr19636-4d.d: Likewise. * testsuite/ld-i386/pr19704.out: Likewise. * testsuite/ld-i386/pr19704a.c: Likewise. * testsuite/ld-i386/pr19704b.c: Likewise. * testsuite/ld-x86-64/pr19636-1.s: Likewise. * testsuite/ld-x86-64/pr19636-1a.d: Likewise. * testsuite/ld-x86-64/pr19636-1b.d: Likewise. * testsuite/ld-x86-64/pr19636-1c.d: Likewise. * testsuite/ld-x86-64/pr19636-1d.d: Likewise. * testsuite/ld-x86-64/pr19636-1e.d: Likewise. * testsuite/ld-x86-64/pr19636-1f.d: Likewise. * testsuite/ld-x86-64/pr19636-1g.d: Likewise. * testsuite/ld-x86-64/pr19636-2.s: Likewise. * testsuite/ld-x86-64/pr19636-2a.d: Likewise. * testsuite/ld-x86-64/pr19636-2b.d: Likewise. * testsuite/ld-x86-64/pr19636-2c.d: Likewise. * testsuite/ld-x86-64/pr19636-2d-nacl.d: Likewise. * testsuite/ld-x86-64/pr19636-2d.d: Likewise. * testsuite/ld-x86-64/pr19636-2e.d: Likewise. * testsuite/ld-x86-64/pr19636-2f.d: Likewise. * testsuite/ld-x86-64/pr19636-2g.d: Likewise. * testsuite/ld-x86-64/pr19636-2h.d: Likewise. * testsuite/ld-x86-64/pr19636-2i.d: Likewise. * testsuite/ld-x86-64/pr19636-3.s: Likewise. * testsuite/ld-x86-64/pr19636-3a.d: Likewise. * testsuite/ld-x86-64/pr19636-3b.d: Likewise. * testsuite/ld-x86-64/pr19636-3c.d: Likewise. * testsuite/ld-x86-64/pr19636-3d.d: Likewise. * testsuite/ld-x86-64/pr19704.out: Likewise. * testsuite/ld-x86-64/pr19704a.c: Likewise. * testsuite/ld-x86-64/pr19704b.c: Likewise. * testsuite/ld-elf/shared.exp (mix_pic_and_non_pic): New. Run mix_pic_and_non_pic. * testsuite/ld-i386/i386.exp (undefined_weak): New. Run undefined_weak and PR ld/19636 tests. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-x86-64/pr13082-3b.d: Updated. * testsuite/ld-x86-64/pr13082-4b.d: Likewise.
2016-02-19[ARM] Add FP16 feature extension for ARMv8.2 architectureJiong Wang2-1/+7
include/ * opcode/arm.h (ARM_EXT2_FP16_INSN): New. gas/ * config/tc-arm.c (arm_ext_fp16): New. (arm_extensions): New entry for "fp16".
2016-02-10Add support for ARC instruction relaxation in the assembler.Claudiu Zissulescu2-0/+14
gas/ 2016-01-26 Claudiu Zissulescu <claziss@synopsys.com> Janek van Oirschot <jvanoirs@synopsys.com> * config/tc-arc.h (TC_FRAG_TYPE, TC_PCREL_ADJUST, MAX_INSN_ARGS) (MAX_INSN_FLGS, MAX_FLAG_NAME_LENGHT, TC_GENERIC_RELAX_TABLE): Define. (arc_flags, arc_relax_type): New structure. * config/tc-arc.c (FRAG_MAX_GROWTH, RELAX_TABLE_ENTRY) (RELAX_TABLE_ENTRY_MAX): New define. (relaxation_state, md_relax_table, arc_relaxable_insns) (arc_num_relaxable_ins): New variable. (rlx_operand_type, arc_rlx_types): New enums. (arc_relaxable_ins): New structure. (OPTION_RELAX): New option. (arc_insn): New relax member. (arc_flags): Remove. (relax_insn_p): New function. (apply_fixups): Likewise. (relaxable_operand): Likewise. (may_relax_expr): Likewise. (relaxable_flag): Likewise. (arc_pcrel_adjust): Likewise. (md_estimate_size_before_relax): Implement. (md_convert_frag): Likewise. (md_parse_option): Handle new mrelax option. (md_show_usage): Likewise. (assemble_insn): Set relax member. (emit_insn0): New function. (emit_insn1): Likewise. (emit_insn): Handle relaxation case. * NEWS: Mention the new relaxation option. * doc/c-arc.texi (ARC Options): Document new mrelax option. gas/testsuite 2016-01-26 Claudiu Zissulescu <claziss@synopsys.com> * gas/arc/relax-avoid1.d: New file. * gas/arc/relax-avoid1.s: Likewise. * gas/arc/relax-avoid2.d: Likewise. * gas/arc/relax-avoid2.s: Likewise. * gas/arc/relax-avoid3.d: Likewise. * gas/arc/relax-avoid3.s: Likewise. * gas/arc/relax-b.d: Likewise. * gas/arc/relax-b.s: Likewise. include/opcode/ 2016-01-26 Claudiu Zissulescu <claziss@synopsys.com> Janek van Oirschot <jvanoirs@synopsys.com> * arc.h (arc_opcode arc_relax_opcodes, arc_num_relax_opcodes): Declare. opcodes/ 2016-01-26 Claudiu Zissulescu <claziss@synopsys.com> Janek van Oirschot <jvanoirs@synopsys.com> * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New variable.
2016-02-09Fix compile time warnings building the binutils with a gcc6 compiler.Nick Clifton4-7/+16
include * opcode/metag.h (metag_scondtab): Mark as possibly unused. * opcode/nds32.h (nds32_r45map): Likewise. (nds32_r54map): Likewise. * opcode/visium.h (gen_reg_table): Likewise. (fp_reg_table, cc_table, opcode_table): Likewise. bfd * oasys.c (oasys_archive_p): Fix indentation. * elf32-nds32.c (nds32_elf_relax_section): Use an unsigned constant for left shifting.
2016-02-09Fix macro redefinition error on SolarisAlan Modra2-0/+6
PR 16583 * elf/common.h (AT_SUN_HWCAP): Undef before defining.
2016-02-04Fix the encoding of the MSP430's RRUX instruction.Nick Clifton2-5/+16
PR target/19561 opcdoe * msp430-dis.c (print_insn_msp430): Add a special case for decoding an RRC instruction with the ZC bit set in the extension word. include * opcode/msp430.h (IGNORE_CARRY_BIT): New define. (RRUX): Synthesise using case 2 rather than 7. gas * config/tc-msp430.c (msp430_operands): Remove case 7. Use case 2 to handle encoding of RRUX instruction. * testsuite/gas/msp430/msp430x.s: Add more tests of the extended shift instructions. * testsuite/gas/msp430/msp430x.d: Update expected disassembly.
2016-01-19Add support to readelf for reading FreeBSD ELF core notes.John Baldwin2-0/+27
binutils/ChangeLog: * readelf.c (get_freebsd_elfcore_note_type): New (process_note): Add support for FreeBSD core notes. include/ChangeLog: * elf/common.h (NT_FREEBSD_THRMISC): Define. (NT_FREEBSD_PROCSTAT_PROC): Define. (NT_FREEBSD_PROCSTAT_FILES): Define. (NT_FREEBSD_PROCSTAT_VMMAP): Define. (NT_FREEBSD_PROCSTAT_GROUPS): Define. (NT_FREEBSD_PROCSTAT_UMASK): Define. (NT_FREEBSD_PROCSTAT_RLIMIT): Define. (NT_FREEBSD_PROCSTAT_OSREL): Define. (NT_FREEBSD_PROCSTAT_PSSTRINGS): Define. (NT_FREEBSD_PROCSTAT_AUXV): Define.
2016-01-19Add PIC and TLS support to the ARC target.Miranda Cupertino3-10/+37
bfd/ChangeLog: * arc-plt.def: New file. * arc-plt.h: Likewise. * elf32-arc.c (elf_arc_abs_plt0_entry, elf_arc_abs_pltn_entry, elf_arcV2_abs_plt0_entry, elf_arcV2_abs_pltn_entry, elf_arc_pic_plt0_entry, elf_arc_pic_pltn_entry, elf_arcV2_pic_plt0_entry, elf_arcV2_pic_pltn_entry): Remove. (name_for_global_symbol): Added. (ADD_RELA): Helper to create dynamic relocs. (new_got_entry_to_list): Create a new got entry in linked list. (symbol_has_entry_of_type): Search for specific type of entry in list. (is_reloc_for_GOT): return FALSE for any TLS related relocs. (is_reloc_for_TLS, arc_elf_set_private_flags) (arc_elf_print_private_bfd_data, arc_elf_copy_private_bfd_data) (arc_elf_merge_private_bfd_data): New functions. (debug_arc_reloc): Cleaned debug info printing. (PDATA reloc): Changed not to perform address alignment. (reverse_me): Added. Fix for ARC_32 relocs. (arc_do_relocation): Return bfd_reloc_of when no relocation should occur. (arc_get_local_got_ents): Renamed from arc_get_local_got_offsets. Changed function to access an array of list of GOT entries instead of just an array of offsets. (elf_arc_relocate_section): Added support for PIC and TLS related relocations. (elf_arc_check_relocs): Likewise. (elf_arc_adjust_dynamic_symbol, elf_arc_finish_dynamic_symbol, (elf_arc_finish_dynamic_sections): Likewise (arc_create_dynamic_sections): Modified conditions to create dynamic sections. (ADD_SYMBOL_REF_SEC_AND_RELOC): New macro. (plt_do_relocs_for_symbol, relocate_plt_for_symbol) (relocate_plt_for_entry): Changed to support new way to define PLT related code. (add_symbol_to_plt): Likewise. (arc_elf_link_hash_table_create): New function. include/ChangeLog: * elf/arc-reloc.def (ARC_32, ARC_GOTPC, ARC_TLS_GD_GOT) (ARC_TLS_IE_GOT, ARC_TLS_DTPOFF, ARC_TLS_DTPOFF_S9, ARC_TLS_LE_S9) (ARC_TLS_LE_32): Fixed formula. (ARC_TLS_GD_LD): Use new special function. * opcode/arc-func.h: Changed all the replacement functions to clear the patching bits before doing an or it with the value argument.
2016-01-18Use a 32-bit value to hold the section number in the internal COFF symbol ↵Nick Clifton2-6/+17
structure. PR ld/19440 inc * coff/internal.h (internal_syment): Use int to hold section number. (N_UNDEF): Cast to int not short. (N_ABS): Likewise. (N_DEBUG): Likewise. (N_TV): Likewise. (P_TV): Likewise. bfd PR ld/19440 * coff-rs6000.c (_bfd_xcoff_swap_sym_in): Sign extend external section number into internal section number. * coff64-rs6000.c (_bfd_xcoff64_swap_sym_in): Likewise. * coffswap.h (coff_swap_sym_in): Likewise. * peXXigen.c (_bfd_XXi_swap_sym_in): Likewise. * coffcode.h (_coff_bigobj_swap_sym_in): Make sure that internal section number field is big enough to hold the external value.
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