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2006-07-142006-07-14 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-12/+18
* i386.h (i386_optab): Remove InvMem from maskmovq, movhlps, movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu, movdq2q and movq2dq.
2006-07-13Add amdfam10 instructionsMichael Meissner2-0/+19
2006-07-10include/Jakub Jelinek4-0/+17
* bfdlink.h (struct bfd_link_info): Add emit_hash and emit_gnu_hash bitfields. include/elf/ * common.h (SHT_GNU_HASH, DT_GNU_HASH): Define. ld/ * scripttempl/elf.sc: Add .gnu.hash section. * emultempl/elf32.em (OPTION_HASH_STYLE): Define. (gld${EMULATION_NAME}_add_options): Register --hash-style option. (gld${EMULATION_NAME}_handle_option): Handle it. (gld${EMULATION_NAME}_list_options): Document it. * ldmain.c (main): Initialize emit_hash and emit_gnu_hash. * ld.texinfo: Document --hash-style option. bfd/ * elf.c (_bfd_elf_print_private_bfd_data): Handle DT_GNU_HASH. (bfd_section_from_shdr, elf_fake_sections, assign_section_numbers): Handle SHT_GNU_HASH. (special_sections_g): Include .gnu.hash section. (bfd_elf_gnu_hash): New function. * elf-bfd.h (bfd_elf_gnu_hash, _bfd_elf_hash_symbol): New prototypes. (struct elf_backend_data): Add elf_hash_symbol method. * elflink.c (_bfd_elf_link_create_dynamic_sections): Create .hash only if info->emit_hash, create .gnu.hash section if info->emit_gnu_hash. (struct collect_gnu_hash_codes): New type. (elf_collect_gnu_hash_codes, elf_renumber_gnu_hash_syms, _bfd_elf_hash_symbol): New functions. (compute_bucket_count): Don't compute HASHCODES array, instead add that and NSYMS as arguments. Use bed->s->sizeof_hash_entry instead of bed->s->arch_size / 8. Fix .hash size estimation. When not optimizing, use the number of hashed symbols rather than dynsymcount. (bfd_elf_size_dynamic_sections): Only add DT_HASH if info->emit_hash, and ADD DT_GNU_HASH if info->emit_gnu_hash. (bfd_elf_size_dynsym_hash_dynstr): Size .hash only if info->emit_hash, adjust compute_bucket_count caller. Create and populate .gnu.hash section if info->emit_gnu_hash. (elf_link_output_extsym): Only populate .hash section if finfo->hash_sec != NULL. (bfd_elf_final_link): Adjust assertion. Handle DT_GNU_HASH. * elfxx-target.h (elf_backend_hash_symbol): Define if not yet defined. (elfNN_bed): Add elf_backend_hash_symbol. * elf64-x86-64.c (elf64_x86_64_hash_symbol): New function. (elf_backend_hash_symbol): Define. * elf32-i386.c (elf_i386_hash_symbol): New function. (elf_backend_hash_symbol): Define. binutils/ * readelf.c (get_dynamic_type): Handle DT_GNU_HASH. (get_section_type_name): Handle SHT_GNU_HASH. (dynamic_info_DT_GNU_HASH): New variable. (process_dynamic_section): Handle DT_GNU_HASH. (process_symbol_table): Print also DT_GNU_HASH histogram. ld/testsuite/ * ld-powerpc/tlsso32.r: Adjust. * ld-powerpc/tlsso32.d: Adjust. * ld-powerpc/tlsso32.g: Adjust. * ld-powerpc/tlsso.r: Adjust. * ld-powerpc/tlsso.g: Adjust. * ld-powerpc/tlstocso.g: Adjust.
2006-06-15 * include/elf/arm.h: Correct names of R_ARM_LDC_G{0,1,2}Mark Shinwell1-4/+3
to R_ARM_LDC_SB_G{0,1,2} respectively. bfd/ * bfd-in2.h: Regenerate. * elf32-arm.c (R_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0, R_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1, R_ARM_ALU_PC_G2, R_ARM_LDR_PC_G1, R_ARM_LDR_PC_G2, R_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G2, R_ARM_LDC_PC_G0, R_ARM_LDC_PC_G1, R_ARM_LDC_PC_G2, R_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0, R_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1, R_ARM_ALU_SB_G2, R_ARM_LDR_SB_G0, R_ARM_LDR_SB_G1, R_ARM_LDR_SB_G2, R_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G2, R_ARM_LDC_SB_G0, R_ARM_LDC_SB_G1, R_ARM_LDC_SB_G2): New relocation types. (R_ARM_PC13): Rename to AAELF name R_ARM_LDR_PC_G0 and adjust HOWTO entry to be consistent with R_ARM_LDR_PC_G1 and friends. (elf32_arm_howto_table_3): Delete; contents merged into elf32_arm_howto_table_2. (elf32_arm_howto_from_type): Adjust correspondingly. (elf32_arm_reloc_map): Extend with the above relocations. (calculate_group_reloc_mask): New function. (identify_add_or_sub): New function. (elf32_arm_final_link_relocate): Support for the above relocations. * reloc.c: Add enumeration entries for BFD_RELOC_ARM_... codes to correspond to the above relocations. gas/ * config/tc-arm.c (enum parse_operand_result): New. (struct group_reloc_table_entry): New. (enum group_reloc_type): New. (group_reloc_table): New array. (find_group_reloc_table_entry): New function. (parse_shifter_operand_group_reloc): New function. (parse_address_main): New function, incorporating code from the old parse_address function. To be used via... (parse_address): wrapper for parse_address_main; and (parse_address_group_reloc): new function, likewise. (enum operand_parse_code): New codes OP_SHG, OP_ADDRGLDR, OP_ADDRGLDRS, OP_ADDRGLDC. (parse_operands): Support for these new operand codes. New macro po_misc_or_fail_no_backtrack. (encode_arm_cp_address): Preserve group relocations. (insns): Modify to use the above operand codes where group relocations are permitted. (md_apply_fix): Handle the group relocations ALU_PC_G0_NC through LDC_SB_G2. (tc_gen_reloc): Likewise. (arm_force_relocation): Leave group relocations for the linker. (arm_fix_adjustable): Likewise. gas/testsuite/ * gas/arm/group-reloc-alu.d: New test. * gas/arm/group-reloc-alu-encoding-bad.d: New test. * gas/arm/group-reloc-alu-encoding-bad.l: New test. * gas/arm/group-reloc-alu-encoding-bad.s: New test. * gas/arm/group-reloc-alu-parsing-bad.d: New test. * gas/arm/group-reloc-alu-parsing-bad.l: New test. * gas/arm/group-reloc-alu-parsing-bad.s: New test. * gas/arm/group-reloc-alu.s: New test. * gas/arm/group-reloc-ldc.d: New test. * gas/arm/group-reloc-ldc-encoding-bad.d: New test. * gas/arm/group-reloc-ldc-encoding-bad.l: New test. * gas/arm/group-reloc-ldc-encoding-bad.s: New test. * gas/arm/group-reloc-ldc-parsing-bad.d: New test. * gas/arm/group-reloc-ldc-parsing-bad.l: New test. * gas/arm/group-reloc-ldc-parsing-bad.s: New test. * gas/arm/group-reloc-ldc.s: New test. * gas/arm/group-reloc-ldr.d: New test. * gas/arm/group-reloc-ldr-encoding-bad.d: New test. * gas/arm/group-reloc-ldr-encoding-bad.l: New test. * gas/arm/group-reloc-ldr-encoding-bad.s: New test. * gas/arm/group-reloc-ldr-parsing-bad.d: New test. * gas/arm/group-reloc-ldr-parsing-bad.l: New test. * gas/arm/group-reloc-ldr-parsing-bad.s: New test. * gas/arm/group-reloc-ldr.s: New test. * gas/arm/group-reloc-ldrs.d: New test. * gas/arm/group-reloc-ldrs-encoding-bad.d: New test. * gas/arm/group-reloc-ldrs-encoding-bad.l: New test. * gas/arm/group-reloc-ldrs-encoding-bad.s: New test. * gas/arm/group-reloc-ldrs-parsing-bad.d: New test. * gas/arm/group-reloc-ldrs-parsing-bad.l: New test. * gas/arm/group-reloc-ldrs-parsing-bad.s: New test. * gas/arm/group-reloc-ldrs.s: New test. ld/testsuite/ * ld-arm/group-relocs-alu-bad.d: New test. * ld-arm/group-relocs-alu-bad.s: New test. * ld-arm/group-relocs.d: New test. * ld-arm/group-relocs-ldc-bad.d: New test. * ld-arm/group-relocs-ldc-bad.s: New test. * ld-arm/group-relocs-ldr-bad.d: New test. * ld-arm/group-relocs-ldr-bad.s: New test. * ld-arm/group-relocs-ldrs-bad.d: New test. * ld-arm/group-relocs-ldrs-bad.s: New test. * ld-arm/group-relocs.s: New test. * ld-arm/arm-elf.exp: Wire in new tests.
2006-06-12gas/testsuite/H.J. Lu2-1/+9
2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run nops and x86-64-nops. * gas/i386/nops.d: New file. * gas/i386/nops.s: Likewise. * gas/i386/x86-64-nops.d: Likewise. * gas/i386/x86-64-nops.s: Likewise. include/opcode/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Add "nop" with memory reference. opcodes/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f. (twobyte_has_modrm): Set 1 for 0x1f.
2006-06-12gas/H.J. Lu2-9/+5
2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_suffix): Don't add rex64 for "xchg %rax,%rax". gas/testsuite/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/opcode.s: Add "xchg %ax,%ax". * gas/i386/opcode.d: Updated. * gas/i386/x86-64-opcode.s: Add xchg %ax,%ax, xchg %eax,%eax, xchg %rax,%rax, rex64 xchg %rax,%rax and xchg %rax,%r8. * gas/i386/x86-64-opcode.d: Updated. include/opcode/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Update comment for 64bit NOP. opcodes/ 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (NOP_Fixup): Removed. (NOP_Fixup1): New. (NOP_Fixup2): Likewise. (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
2006-06-07include/opcode/Alan Modra2-3/+13
* ppc.h (PPC_OPCODE_POWER6): Define. Adjust whitespace. gas/ * config/tc-ppc.c (parse_cpu): Handle "-mpower6". (md_show_usage): Document it. (ppc_setup_opcodes): Test power6 opcode flag bits. * doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6". opcodes/ * ppc-dis.c (powerpc_dialect): Handle power6 option. (print_ppc_disassembler_options): Mention power6.
2006-06-06 [ gas/ChangeLog ]Thiemo Seufer1-8/+8
* config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro. (CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete. (macro_build): Update comment. (mips_ip): Allow DSP64 instructions for MIPS64R2. (mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and CPU_HAS_MDMX. (mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and MIPS_CPU_ASE_MDMX flags for sb1. [ gas/testsuite/ChangeLog ] * gas/mips/mips64-dsp.s, gas/mips/mips64-dsp.d: New DSP64 tests. * gas/mips/mips.exp: Run DSP64 tests. [ opcodes/ChangeLog ] * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2. * mips-opc.c: Add DSP64 instructions.
2006-06-05 [ gas/ChangeLog ]Thiemo Seufer2-2/+6
* config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew appropriate. (mips16_macro_build): Use MIPS16_INSERT_OPERAND where appropriate. (mips_ip): Make overflowed/underflowed constant arguments in DSP and MT instructions a fatal error. Use INSERT_OPERAND where appropriate. Improve warnings for break and wait code overflows. Use symbolic constant of OP_MASK_COPZ. (mips16_ip): Use MIPS16_INSERT_OPERAND where appropriate. [ gas/testsuite/ChangeLog ] * gas/mips/mips32-dsp.d, gas/mips/mips32-dsp.s, gas/mips/mips32-mt.d, gas/mips/mips32-mt.s: Remove instructions with invalid arguments. * gas/mips/mips32-dsp.l, gas/mips/mips32-mt.l: Delete file. [ include/opcode/ChangeLog ] * mips.h: Improve description of MT flags.
2006-06-01merge from gccDJ Delorie1-0/+17
2006-06-01include/elf/H.J. Lu2-15/+35
2006-05-31 H.J. Lu <hongjiu.lu@intel.com> * internal.h (ELF_SECTION_SIZE): New. (ELF_IS_SECTION_IN_SEGMENT): Likewise. (ELF_IS_SECTION_IN_SEGMENT_FILE): Updated. (ELF_IS_SECTION_IN_SEGMENT_MEMORY): Likewise. ld/testsuite/ 2006-05-31 H.J. Lu <hongjiu.lu@intel.com> * ld-elf/binutils.exp: Make it Linux only. (strip_test): Renamed to binutils_test. Check for unsupported options. Add more tests. * ld-elf/commonpage1.d: Make it Linux only. * ld-elf/maxpage1.d: Likewise. * ld-elf/maxpage1.s: Add main, start and __start. * ld-elf/maxpage2.d: New file. * ld-elf/tbss1.s: Likewise. * ld-elf/tbss2.s: Likewise. * ld-elf/tdata1.s: Likewise. * ld-elf/tdata2.s: Likewise.
2006-05-27bfd/Alan Modra2-1/+10
* elf.c (assign_file_positions_for_load_sections): Retrieve maxpagesize from m->p_align if it is valid. Set p_vaddr, p_paddr and p_align earlier. Revert 2006-05-19 change to p_align. (copy_elf_program_header): Copy p_align. Set p_align_valid. include/elf/ * internal.h (elf_segment_map): Add p_align and p_align_valid.
2006-05-25include/opcodes/Richard Sandiford2-0/+5
* m68k.h (mcf_mask): Define. opcodes/ * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd and fmovem entries. Put register list entries before immediate mask entries. Use "l" rather than "L" in the fmovem entries. * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it out from INFO. (m68k_scan_mask): New function, split out from... (print_insn_m68k): ...here. If no architecture has been set, first try printing an m680x0 instruction, then try a Coldfire one. gas/testsuite/ * gas/m68k/mcf-fpu.s: Add fmovemd and fmovem instructions. * gas/m68k/mcf-fpu.d: Adjust accordingly.
2006-05-24Add TLS support for hppa-linuxNick Clifton2-15/+46
2006-05-24Add support for AVR6 familyNick Clifton2-1/+8
2006-05-05 [ gas/ChangeLog ]Thiemo Seufer2-0/+6
* config/tc-mips.c (macro_build): Add case 'k' to handle cache instruction. (macro): Add new case M_CACHE_AB. [ opcodes/ChangeLog ] * mips-opc.c: Add macro for cache instruction. [ include/opcode/ChangeLog ] * mips.h (enum): Add macro M_CACHE_AB.
2006-05-04[ gas/testsuite/ChangeLog ]Thiemo Seufer2-1/+11
2006-05-04 Thiemo Seufer <ths@mips.com> Nigel Stephens <nigel@mips.com> * gas/mips/mips.exp: Run mips32-dsp tests only for mips32r2. * gas/mips/set-arch.d: Adjust according to opcode table changes. [ include/opcode/ChangeLog ] 2006-05-04 Thiemo Seufer <ths@mips.com> Nigel Stephens <nigel@mips.com> David Ung <davidu@mips.com> * mips.h: Add INSN_SMARTMIPS define. [ opcodes/ChangeLog ] 2006-05-04 Thiemo Seufer <ths@mips.com> Nigel Stephens <nigel@mips.com> David Ung <davidu@mips.com> * mips-dis.c (mips_arch_choices): Add smartmips instruction decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to MIPS64R2. * mips-opc.c: fix random typos in comments. (INSN_SMARTMIPS): New defines. (mips_builtin_opcodes): Add paired single support for MIPS32R2. Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd, flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the FP_S and FP_D flags to denote single and double register accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards. Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1 for MIPS32R2. Add SmartMIPS instructions. Add two-argument variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to release 2 ISAs. * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
2006-04-30[ gas/ChangeLog ]Thiemo Seufer2-0/+24
2006-04-30 Thiemo Seufer <ths@mips.com> David Ung <davidu@mips.com> * config/tc-mips.c (validate_mips_insn): Handling of udi cases. (mips_immed): New table that records various handling of udi instruction patterns. (mips_ip): Adds udi handling. [ include/opcode/ChangeLog ] 2006-04-30 Thiemo Seufer <ths@mips.com> David Ung <davidu@mips.com> * mips.h: Defines udi bits and masks. Add description of characters which may appear in the args field of udi instructions. [ opcodes/ChangeLog ] 2006-04-30 Thiemo Seufer <ths@mips.com> David Ung <davidu@mips.com> * mips-opc.c (mips_builtin_opcodes): Add udi instructions "udi0" to "udi15". * mips-dis.c (print_insn_args): Adds udi argument handling.
2006-04-29Move opcode ChangeLog entry to opcode/ChangeLog.H.J. Lu2-8/+8
2006-04-26 * mips.h: Improve comments describing the bitfield instructionThiemo Seufer2-6/+12
fields.
2006-04-26 * opcode/arm.h (FPU_VFP_EXT_V3): Define constant.Julian Brown2-1/+17
(FPU_NEON_EXT_V1): Likewise. (FPU_VFP_HARD): Update. (FPU_VFP_V3): Define macro. (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
2006-04-26Add missing changelog entryAndreas Jaeger1-0/+5
2006-04-12merge from gccDJ Delorie2-0/+45
2006-04-07Add support for attiny261, attiny461, attiny861, attiny25, attiny45,Nick Clifton2-13/+18
attiny85, attiny24, attiny44, attiny84, at90pwm2, at90pwm3, atmega164, atmega324, atmega644, atmega329, atmega3290, atmega649, atmega6490, atmega406, atmega640, atmega1280, atmega1281, at90can32, at90can64, at90usb646, at90usb647, at90usb1286 and at90usb1287. Move atmega48 and atmega88 from AVR_ISA_M8 to AVR_ISA_PWMx.
2006-04-06bfd/H.J. Lu2-3/+11
2006-04-06 H.J. Lu <hongjiu.lu@intel.com> * elfxx-ia64.c (elfNN_ia64_relax_section): Skip unneeded passes with the skip_relax_pass_0 and skip_relax_pass_1 bits in the section structure. include/ 2006-04-06 H.J. Lu <hongjiu.lu@intel.com> * bfdlink.h (bfd_link_info): Replace need_relax_finalize with relax_pass. ld/ 2006-04-06 H.J. Lu <hongjiu.lu@intel.com> * emultempl/ia64elf.em: Set link_info.relax_pass to 2. Remove link_info.need_relax_finalize. * ldlang.c (relax_sections): New. (lang_process): Use. Call relax_sections link_info.relax_pass times. * ldmain.c (main): Set link_info.relax_pass to 1. Remove link_info.need_relax_finalize.
2006-03-28 gas:Nathan Sidwell2-38/+8
* config/tc-m68k.c (m68000_control_regs, m68010_control_regs, m68020_control_regs, m68040_control_regs, m68060_control_regs, mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs, mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs, mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ... (m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl, mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl, mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl, mcf5282_ctrl, mcfv4e_ctrl): ... these. (mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New. (struct m68k_cpu): Change chip field to control_regs. (current_chip): Remove. (control_regs): New. (m68k_archs, m68k_extensions): Adjust. (m68k_cpus): Reorder to be in cpu number order. Adjust. (CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove. (find_cf_chip): Reimplement for new organization of cpu table. (select_control_regs): Remove. (mri_chip): Adjust. (struct save_opts): Save control regs, not chip. (s_save, s_restore): Adjust. (m68k_lookup_cpu): Give deprecated warning when necessary. (m68k_init_arch): Adjust. (md_show_usage): Adjust for new cpu table organization. include/opcodes: * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010, cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851, cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e, cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x, cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
2006-03-25 * elf/bfin.h (R_BFIN_GOT17M4, R_BFIN_GOTHI, R_BFIN_GOTLO,Bernd Schmidt2-0/+30
R_BFIN_FUNCDESC, R_BFIN_FUNCDESC_GOT17M4, R_BFIN_FUNCDESC_GOTHI, R_BFIN_FUNCDESC_GOTLO, R_BFIN_FUNCDESC_VALUE, R_BFIN_FUNCDESC_GOTOFF17M4, R_BFIN_FUNCDESC_GOTOFFHI, R_BFIN_FUNCDESC_GOTOFFLO, R_BFIN_GOTOFF17M4, R_BFIN_GOTOFFHI, R_BFIN_GOTOFFLO): New relocs. (EF_BFIN_PIC, EF_BFIN_FDPIC, EF_BFIN_PIC_FLAGS): New macros.
2006-03-23Patch by matz@suse.de:Andreas Jaeger1-1/+10
bfd/ChangeLog: * reloc.c: Add BFD_RELOC_X86_64_GOT64, BFD_RELOC_X86_64_GOTPCREL64, BFD_RELOC_X86_64_GOTPC64, BFD_RELOC_X86_64_GOTPLT64, BFD_RELOC_X86_64_PLTOFF64. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * elf64-x86-64.c (x86_64_elf_howto_table): Correct comment. Add howtos for above relocs. (x86_64_reloc_map): Add mappings for new relocs. (elf64_x86_64_check_relocs): R_X86_64_GOT64, R_X86_64_GOTPCREL64, R_X86_64_GOTPLT64 need a got entry. R_X86_64_GOTPLT64 also a PLT entry. R_X86_64_GOTPC64 needs a .got section. R_X86_64_PLTOFF64 needs a PLT entry. (elf64_x86_64_gc_sweep_hook): Reflect changes from elf64_x86_64_check_relocs for the new relocs. (elf64_x86_64_relocate_section): Handle new relocs. gas/ChangeLog: * config/tc-i386.c (type_names): Correct placement of 'static'. (reloc): Map some more relocs to their 64 bit counterpart when size is 8. (output_insn): Work around breakage if DEBUG386 is defined. (output_disp): A BFD_RELOC_64 with GOT_symbol as operand also needs to be mapped to BFD_RELOC_X86_64_GOTPC64 or BFD_RELOC_X86_64_GOTPC32. Also x86-64 handles pcrel addressing different from i386. (output_imm): Ditto. (lex_got): Recognize @PLTOFF and @GOTPLT. Make @GOT accept also Imm64. (md_convert_frag): Jumps can now be larger than 2GB away, error out in that case. (tc_gen_reloc): New relocs are passed through. BFD_RELOC_64 and BFD_RELOC_64_PCREL are mapped to BFD_RELOC_X86_64_GOTPC64. gas/testsuite/ChangeLog: * gas/i386/reloc64.s: Accept 64-bit forms. * gas/i386/reloc64.d: Adjust. * gas/i386/reloc64.l: Adjust. include/ChangeLog: * elf/x86-64.h: Add the new relocations with their official numbers.
2006-03-22 Richard Sandiford <richard@codesourcery.com>Richard Sandiford2-0/+12
Daniel Jacobowitz <dan@codesourcery.com> Phil Edwards <phil@codesourcery.com> Zack Weinberg <zack@codesourcery.com> Mark Mitchell <mark@codesourcery.com> Nathan Sidwell <nathan@codesourcery.com> bfd/ * bfd-in2.h: Regenerate. * config.bfd (mips*-*-vxworks*, mips*el-*-vxworks*): New stanzas. * configure.in (bfd_elf32_bigmips_vxworks_vec): New stanza. (bfd_elf32_littlemips_vxworks_vec): Likewise. (bfd_elf32_bigmips_vec): Add elf-vxworks.lo. (bfd_elf32_littlemips_vec): Likewise. (bfd_elf32_nbigmips_vec): Likewise. (bfd_elf32_nlittlemips_vec): Likewise. (bfd_elf32_ntradbigmips_vec): Likewise. (bfd_elf32_ntradlittlemips_vec): Likewise. (bfd_elf32_tradbigmips_vec): Likewise. (bfd_elf32_tradlittlemips_vec): Likewise. (bfd_elf64_bigmips_vec): Likewise. (bfd_elf64_littlemips_vec): Likewise. (bfd_elf64_tradbigmips_vec): Likewise. (bfd_elf64_tradlittlemips_vec): Likewise. * elf32-mips.c: Include elf-vxworks.h. (mips_info_to_howto_rel): Use elf_backend_mips_rtype_to_howto instead of calling mips_elf32_rtype_to_howto directly. (mips_vxworks_copy_howto_rela): New reloc howto. (mips_vxworks_jump_slot_howto_rela): Likewise. (mips_vxworks_bfd_reloc_type_lookup): New function. (mips_vxworks_rtype_to_howto): Likewise. (mips_vxworks_final_write_processing): Likewise. (TARGET_LITTLE_SYM, TARGET_LITTLE_NAME): Override for VxWorks. (TARGET_BIG_SYM, TARGET_BIG_NAME, elf_bed, ELF_MAXPAGESIZE): Likewise. (elf_backend_want_got_plt): Likewise. (elf_backend_want_plt_sym): Likewise. (elf_backend_got_symbol_offset): Likewise. (elf_backend_want_dynbss): Likewise. (elf_backend_may_use_rel_p): Likewise. (elf_backend_may_use_rela_p): Likewise. (elf_backend_default_use_rela_p): Likewise. (elf_backend_got_header_size: Likewise. (elf_backend_plt_readonly): Likewise. (bfd_elf32_bfd_reloc_type_lookup): Likewise. (elf_backend_mips_rtype_to_howto): Likewise. (elf_backend_adjust_dynamic_symbol): Likewise. (elf_backend_finish_dynamic_symbol): Likewise. (bfd_elf32_bfd_link_hash_table_create): Likewise. (elf_backend_add_symbol_hook): Likewise. (elf_backend_link_output_symbol_hook): Likewise. (elf_backend_emit_relocs): Likewise. (elf_backend_final_write_processing: Likewise. (elf_backend_additional_program_headers): Likewise. (elf_backend_modify_segment_map): Likewise. (elf_backend_symbol_processing): Likewise. * elfxx-mips.c: Include elf-vxworks.h. (mips_elf_link_hash_entry): Add is_relocation_target and is_branch_target fields. (mips_elf_link_hash_table): Add is_vxworks, srelbss, sdynbss, srelplt, srelplt2, sgotplt, splt, plt_header_size and plt_entry_size fields. (MIPS_ELF_RELA_SIZE, MIPS_ELF_REL_DYN_NAME): New macros. (MIPS_RESERVED_GOTNO): Take a mips_elf_link_hash_table argument. Return 3 for VxWorks. (ELF_MIPS_GP_OFFSET): Change the argument from a bfd to a mips_elf_link_hash_table. Return 0 for VxWorks. (MIPS_ELF_GOT_MAX_SIZE): Change the argument from a bfd to a mips_elf_link_hash_table. Update the call to ELF_MIPS_GP_OFFSET. (mips_vxworks_exec_plt0_entry): New variable. (mips_vxworks_exec_plt_entry): Likewise. (mips_vxworks_shared_plt0_entry): Likewise. (mips_vxworks_shared_plt_entry): Likewise. (mips_elf_link_hash_newfunc): Initialize the new hash_entry fields. (mips_elf_rel_dyn_section): Change the bfd argument to a mips_elf_link_hash_table. Use MIPS_ELF_REL_DYN_NAME to get the name of the section. (mips_elf_initialize_tls_slots): Update the call to mips_elf_rel_dyn_section. (mips_elf_gotplt_index): New function. (mips_elf_local_got_index): Add an input_section argument. Update the call to mips_elf_create_local_got_entry. (mips_elf_got_page): Likewise. (mips_elf_got16_entry): Likewise. (mips_elf_create_local_got_entry): Add bfd_link_info and input_section arguments. Create dynamic relocations for each entry on VxWorks. (mips_elf_merge_gots): Update the use of MIPS_ELF_GOT_MAX_SIZE. (mips_elf_multi_got): Update the uses of MIPS_ELF_GOT_MAX_SIZE and MIPS_RESERVED_GOTNO. (mips_elf_create_got_section): Update the uses of MIPS_ELF_GOT_MAX_SIZE. Create .got.plt on VxWorks. (is_gott_symbol): New function. (mips_elf_calculate_relocation): Use a dynobj local variable. Update the calls to mips_elf_local_got_index, mips_elf_got16_entry and mips_elf_got_page_entry. Set G to the .got.plt entry when calculating VxWorks R_MIPS_CALL* relocations. Calculate and use G for all GOT relocations on VxWorks. Add dynamic relocations for references to the VxWorks __GOTT_BASE__ and __GOTT_INDEX__ symbols. Don't create dynamic relocations for R_MIPS_32, R_MIPS_REL32 or R_MIPS_64 in VxWorks executables. (mips_elf_allocate_dynamic_relocations): Add a bfd_link_info argument. Use MIPS_ELF_RELA_SIZE to calculate the size of a VxWorks entry. Don't allocate a null entry on VxWorks. (mips_elf_create_dynamic_relocation): Update the call to mips_elf_rel_dyn_section. Use absolute rather than relative relocations for VxWorks, and make them RELA rather than REL. (_bfd_mips_elf_create_dynamic_sections): Don't make .dynamic read-only on VxWorks. Update the call to mips_elf_rel_dyn_section. Create the .plt, .rela.plt, .dynbss and .rela.bss sections on VxWorks. Likewise create the _PROCEDURE_LINKAGE_TABLE symbol. Call elf_vxworks_create_dynamic_sections for VxWorks and initialize the plt_header_size and plt_entry_size fields. (_bfd_mips_elf_check_relocs): Don't allow GOT relocations to be used in VxWorks executables. Don't allocate dynamic relocations for R_MIPS_32, R_MIPS_REL32 or R_MIPS_64 in VxWorks executables. Set is_relocation_target for each symbol referenced by a relocation. Allocate .rela.dyn entries for relocations against the special VxWorks __GOTT_BASE__ and __GOTT_INDEX__ symbols. Create GOT entries for all VxWorks R_MIPS_GOT16 relocations. Don't allocate a global GOT entry for symbols mentioned in VxWorks R_MIPS_CALL*, R_MIPS_32, R_MIPS_REL32 or R_MIPS_64 relocations. Update the calls to mips_elf_rel_dyn_section and mips_elf_allocate_dynamic_relocations. Set is_branch_target for symbols mentioned in R_MIPS_PC16 or R_MIPS_26 relocations. Don't set no_fn_stub on VxWorks. (_bfd_mips_elf_adjust_dynamic_symbol): Update the call to mips_elf_allocate_dynamic_relocations. (_bfd_mips_vxworks_adjust_dynamic_symbol): New function. (_bfd_mips_elf_always_size_sections): Do not allocate GOT page entries for VxWorks, and do not create multiple GOTs. (_bfd_mips_elf_size_dynamic_sections): Use MIPS_ELF_REL_DYN_NAME. Handle .got specially for VxWorks. Update the uses of MIPS_RESERVED_GOTNO and mips_elf_allocate_dynamic_relocations. Check for sgotplt and splt. Allocate the .rel(a).dyn contents last, once its final size is known. Set DF_TEXTREL for VxWorks. Add DT_RELA, DT_RELASZ, DT_RELAENT, DT_PLTREL, DT_PLTRELSZ and DT_JMPREL tags on VxWorks. Do not add the MIPS-specific tags for VxWorks. (_bfd_mips_vxworks_finish_dynamic_symbol): New function. (mips_vxworks_finish_exec_plt): Likewise. (mips_vxworks_finish_shared_plt): Likewise. (_bfd_mips_elf_finish_dynamic_sections): Remove an unncessary call to mips_elf_rel_dyn_section. Use a VxWorks-specific value of DT_PLTGOT. Handle DT_RELA, DT_RELASZ, DT_RELAENT, DT_PLTREL, DT_PLTRELSZ and DT_JMPREL. Update the uses of MIPS_RESERVED_GOTNO and mips_elf_rel_dyn_section. Use a different GOT header for VxWorks. Don't sort .rela.dyn on VxWorks. Finish the PLT on VxWorks. (_bfd_mips_elf_link_hash_table_create): Initialize the new mips_elf_link_hash_table fields. (_bfd_mips_vxworks_link_hash_table_create): New function. (_bfd_mips_elf_final_link): Set the GP value to _GLOBAL_OFFSET_TABLE_ on VxWorks. Update the call to ELF_MIPS_GP_OFFSET. * elfxx-mips.h (_bfd_mips_vxworks_adjust_dynamic_symbol): Declare. (_bfd_mips_vxworks_finish_dynamic_symbol): Likewise. (_bfd_mips_vxworks_link_hash_table_create): Likewise. * libbfd.h: Regenerate. * Makefile.am (elfxx-mips.lo): Depend on elf-vxworks.h. (elf32-mips.lo): Likewise. * Makefile.in: Regenerate. * reloc.c (BFD_RELOC_MIPS_COPY, BFD_RELOC_MIPS_JUMP_SLOT): Declare. * targets.c (bfd_elf32_bigmips_vxworks_vec): Declare. (bfd_elf32_littlemips_vxworks_vec): Likewise. (_bfd_target_vector): Add entries for them. gas/ * config/tc-mips.c (mips_target_format): Handle vxworks targets. (md_begin): Complain about -G being used for PIC. Don't change the text, data and bss alignments on VxWorks. (reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when generating VxWorks PIC. (load_address): Extend SVR4_PIC handling to VXWORKS_PIC. (macro): Likewise, but do not treat la $25 specially for VxWorks PIC, and do not handle jal. (OPTION_MVXWORKS_PIC): New macro. (md_longopts): Add -mvxworks-pic. (md_parse_option): Don't complain about using PIC and -G together here. Handle OPTION_MVXWORKS_PIC. (md_estimate_size_before_relax): Always use the first relaxation sequence on VxWorks. * config/tc-mips.h (VXWORKS_PIC): New. gas/testsuite/ * gas/mips/vxworks1.s, gas/mips/vxworks1.d, * gas/mips/vxworks1-xgot.d: New tests. * gas/mips/mips.exp: Run them. Do not run other tests on VxWorks. include/elf/ * mips.h (R_MIPS_COPY, R_MIPS_JUMP_SLOT): New relocs. ld/ * configure.tgt (mips*el-*-vxworks*, mips*-*-vxworks*): Use separate VxWorks emulations. * emulparams/elf32ebmipvxworks.sh: New file. * emulparams/elf32elmipvxworks.sh: New file. * Makefile.am (ALL_EMULATIONS): Add eelf32ebmipvxworks.o and eelf32elmipvxworks.o. (eelf32ebmipvxworks.c, eelf32elmipvxworks.c): New rules. * Makefile.in: Regenerate. ld/testsuite/ * ld-mips/vxworks1.dd, ld-mips/vxworks1.ld, ld-mips/vxworks1-lib.dd, * ld-mips/vxworks1-lib.nd, ld-mips/vxworks1-lib.rd, * ld-mips/vxworks1-lib.s, ld-mips/vxworks1.rd, ld-mips/vxworks1.s, * ld-mips/vxworks1-static.d, ld-mips/vxworks2.s, ld-mips/vxworks2.sd, * ld-mips/vxworks2-static.sd: New tests. * ld-mips/mips-elf.exp: Run them.
2006-03-20 * hppa.h (SHF_HP_TLS, SHF_HP_NEAR_SHARED, SHF_HP_FAR_SHARED,Dave Anglin2-0/+35
SHF_HP_COMDAT, SHF_HP_CONST, SHN_TLS_COMMON, SHN_NS_COMMON, SHN_NS_UNDEF, SHN_FS_UNDEF, SHN_HP_EXTERN, SHN_HP_EXTHINT, SHN_HP_UNDEF_BIND_IMM, SHT_HP_OVLBITS, SHT_HP_DLKM, SHT_HP_COMDAT, SHT_HP_OBJDICT, SHT_HP_ANNOT, STB_HP_ALIAS): Define.
2006-03-102006-03-10 Paul Brook <paul@codesourcery.com>Paul Brook2-0/+5
bfd/ * elf32-arm.c (INTERWORK_FLAG): Handle EABIv5. (elf32_arm_print_private_bfd_data): Ditto. binutils/ * readelf.c (decode_ARM_machine_flags): Handle EABIv5. gas/ * config/tc-arm.c (md_begin): Handle EABIv5. (arm_eabis): Add EF_ARM_EABI_VER5. * doc/c-arm.texi: Document -meabi=5. include/elf/ * arm.h (EF_ARM_EABI_VER5): Define.
2006-03-102006-03-10 Paul Brook <paul@codesourcery.com>Paul Brook2-1/+5
include/opcode/ * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
2006-03-06missing changelog entry for my 2006-02-07 patchNathan Sidwell1-0/+8
* m68k.h (m68008, m68ec030, m68882): Remove. (m68k_mask): New. (cpu_m68k, cpu_cf): New. (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407
2006-03-06 bfd:Nathan Sidwell2-9/+20
* archures.c (bfd_mach_mcf_isa_a_nodiv, bfd_mach_mcf_isa_b_nousp): New. Adjust other variants. (bfd_default_scan): Update. * bfd-in2.h: Rebuilt. * cpu-m68k.c: Adjust. (bfd_m68k_compatible): New. Use it for architectures. * elf32-m68k.c (elf32_m68k_object_p): Adjust. (elf32_m68k_merge_private_bfd_data): Adjust. Correct isa-a/b mismatch. (elf32_m68k_print_private_bfd_data): Adjust. * ieee.c (ieee_write_processor): Adjust. binutils: * readelf.c (get_machine_flags): Adjust. gas: * config/tc-m68k.c (m68k_extensions): Allow 'float' on both m68k and cf. (m68k_ip): <case 'J'> Check we have some control regs. (md_parse_option): Allow raw arch switch. (m68k_init_arch): Better detection of arch/cpu mismatch. Detect whether 68881 or cfloat was meant by -mfloat. (md_show_usage): Adjust extension display. (m68k_elf_final_processing): Adjust. gas/testsuite: * gas/m68k/arch-cpu-1.s: Tweak. * gas/m68k/arch-cpu-1.d: Tweak. include/elf: * m68k.h (EF_M68K_ISA_MASK, EF_M68K_ISA_A, EF_M68K_ISA_A_PLUS, EF_M68K_ISA_B, EF_M68K_ISA_C): Adjust. (EF_M68K_ISA_A_NODIV, EF_M68K_ISA_B_NOUSP): New. (EF_M68K_HW_DIV, EF_M68K_USP): Remove. (EF_M68K_MAC, EF_M68K_EMAC, EF_M68K_FLOAT): Adjust. (EF_M68K_EMAC_B): New. ld/testsuite: * ld-m68k: New tests.
2006-03-04 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes comeDave Anglin2-2/+7
first. Correct mask of bb "B" opcode.
2006-03-03Add linker relaxation support for the AVRNick Clifton2-0/+11
2006-03-02 Import from the GCC tree:Ben Elliston2-4/+87
2006-03-01 Jakub Jelinek <jakub@redhat.com> * dwarf2.h (DW_TAG_condition, DW_TAG_shared_type): New constants from DWARF 3. (DW_AT_description, DW_AT_binary_scale, DW_AT_decimal_scale, DW_AT_small, DW_AT_decimal_sign, DW_AT_digit_count, DW_AT_picture_string, DW_AT_mutable, DW_AT_threads_scaled, DW_AT_explicit, DW_AT_object_pointer, DW_AT_endianity, DW_AT_elemental, DW_AT_pure, DW_AT_recursive): New. (DW_OP_form_tls_address, DW_OP_call_frame_cfa, DW_OP_bit_piece): New. (DW_ATE_packed_decimal, DW_ATE_numeric_string, DW_ATE_edited, DW_ATE_signed_fixed, DW_ATE_unsigned_fixed): New. (DW_DS_unsigned, DW_DS_leading_overpunch, DW_DS_trailing_overpunch, DW_DS_leading_separate, DW_DS_trailing_separate): New. (DW_END_default, DW_END_big, DW_END_little): New. (DW_END_lo_user, DW_END_hi_user): Define. (DW_LNE_lo_user, DW_LNE_hi_user): Define. (DW_CFA_val_offset, DW_CFA_val_offset_sf, DW_CFA_val_expression): New. (DW_LANG_PLI, DW_LANG_ObjC, DW_LANG_ObjC_plus_plus, DW_LANG_UPC, DW_LANG_D): New.
2006-02-27gas/H.J. Lu2-0/+39
2006-02-27 H.J. Lu <hongjiu.lu@intel.com> * gas/config/tc-i386.c (output_insn): Support Intel Merom New Instructions. * gas/config/tc-i386.h (CpuMNI): New. (CpuUnknownFlags): Add CpuMNI. gas/testsuite/ 2006-02-27 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Add merom and x86-64-merom. * gas/i386/merom.d: New file. * gas/i386/merom.s: Likewise. * gas/i386/x86-64-merom.d: Likewise. * gas/i386/x86-64-merom.s: Likewise. include/opcode/ 2006-02-27 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Support Intel Merom New Instructions. opcodes/ 2006-02-27 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by Intel Merom New Instructions. (THREE_BYTE_0): Likewise. (THREE_BYTE_1): Likewise. (three_byte_table): Likewise. (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use THREE_BYTE_1 for entry 0x3a. (twobyte_has_modrm): Updated. (twobyte_uses_SSE_prefix): Likewise. (print_insn): Handle 3-byte opcodes used by Intel Merom New Instructions.
2006-02-24[include/elf]DJ Delorie2-0/+12
* m32c.h: Add relax relocs. [cpu] * m32c.cpu (RL_TYPE): New attribute, with macros. (Lab-8-24): Add RELAX. (unary-insn-defn-g, binary-arith-imm-dst-defn, binary-arith-imm4-dst-defn): Add 1ADDR attribute. (binary-arith-src-dst-defn): Add 2ADDR attribute. (jcnd16-5, jcnd16, jcnd32, jmp16.s, jmp16.b, jmp16.w, jmp16.a, jmp32.s, jmp32.b, jmp32.w, jmp32.a, jsr16.w, jsr16.a): Add JUMP attribute. (jsri16, jsri32): Add 1ADDR attribute. (jsr32.w, jsr32.a): Add JUMP attribute. [opcodes] * m32c-desc.c: Regenerate with linker relaxation attributes. * m32c-desc.h: Likewise. * m32c-dis.c: Likewise. * m32c-opc.c: Likewise. [gas] * config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix. (tc_gen_reloc): Don't define. * config/tc-m32c.c (rl_for, relaxable): New convenience macros. (OPTION_LINKRELAX): New. (md_longopts): Add it. (m32c_relax): New. (md_parse_options): Set it. (md_assemble): Emit relaxation relocs as needed. (md_convert_frag): Emit relaxation relocs as needed. (md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16. (m32c_apply_fix): New. (tc_gen_reloc): New. (m32c_force_relocation): Force out jump relocs when relaxing. (m32c_fix_adjustable): Return false if relaxing. [bfd] * elf32-m32c.c (m32c_elf_howto_table): Add relaxation relocs. (m32c_elf_relocate_section): Don't relocate them. (compare_reloc): New. (relax_reloc): Remove. (m32c_offset_for_reloc): New. (m16c_addr_encodings): New. (m16c_jmpaddr_encodings): New. (m32c_addr_encodings): New. (m32c_elf_relax_section): Relax jumps and address displacements. (m32c_elf_relax_delete_bytes): Adjust for internal syms. Fix up short jumps. * reloc.c: Add m32c relax relocs. * libbfd.h: Regenerate.
2006-02-242006-02-24 Paul Brook <paul@codesourcery.com>Paul Brook2-5/+30
gas/ * config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7, arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables. (struct asm_barrier_opt): Define. (arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables. (parse_psr): Accept V7M psr names. (parse_barrier): New function. (enum operand_parse_code): Add OP_oBARRIER. (parse_operands): Implement OP_oBARRIER. (do_barrier): New function. (do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions. (do_t_cpsi): Add V7M restrictions. (do_t_mrs, do_t_msr): Validate V7M variants. (md_assemble): Check for NULL variants. (v7m_psrs, barrier_opt_names): New tables. (insns): Add V7 instructions. Mark V6 instructions absent from V7M. (md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh. (arm_cpu_option_table): Add Cortex-M3, R4 and A8. (arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m. (struct cpu_arch_ver_table): Define. (cpu_arch_ver): New. (aeabi_set_public_attributes): Use cpu_arch_ver. Set Tag_CPU_arch_profile. * doc/c-arm.texi: Document new cpu and arch options. gas/testsuite/ * gas/arm/thumb32.d: Fix expected msr and mrs output. * gas/arm/arch7.d: New test. * gas/arm/arch7.s: New test. * gas/arm/arch7m-bad.l: New test. * gas/arm/arch7m-bad.d: New test. * gas/arm/arch7m-bad.s: New test. include/opcode/ * arm.h: Add V7 feature bits. opcodes/ * arm-dis.c (arm_opcodes): Add V7 instructions. (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants. (print_arm_address): New function. (print_insn_arm): Use it. Add 'P' and 'U' cases. (psr_name): New function. (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-23bfd/H.J. Lu2-2/+8
2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * cpu-ia64-opc.c (ins_immu5b): New. (ext_immu5b): Likewise. (elf64_ia64_operands): Add IMMU5b. gas/ 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b. gas/testsuite/ 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * gas/ia64/opc-i.s: Add tests for tf. * gas/ia64/pseudo.s: Likewise. * gas/ia64/opc-i.d: Updated. * gas/ia64/pseudo.d: Likewise. include/opcode/ 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b. opcodes/ 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * ia64-opc-i.c (bXc): New. (mXc): Likewise. (OpX2TaTbYaXcC): Likewise. (TF). Likewise. (TFCM). Likewise. (ia64_opcodes_i): Add instructions for tf. * ia64-opc.h (IMMU5b): New. * ia64-asmtab.c: Regenerated.
2006-02-17Add support for the Infineon XC16X.Nick Clifton5-57/+114
2006-02-10bfd/H.J. Lu2-0/+31
2006-02-10 H.J. Lu <hongjiu.lu@intel.com> PR binutils/2258 * elf.c (copy_private_bfd_data): Renamed to ... (rewrite_elf_program_header): This. (copy_elf_program_header): New function. (copy_private_bfd_data): Likewise. binutils/ 2006-02-10 H.J. Lu <hongjiu.lu@intel.com> PR binutils/2258 * readelf.c (process_program_headers): Use ELF_IS_SECTION_IN_SEGMENT_MEMORY. include/elf/ 2006-02-10 H.J. Lu <hongjiu.lu@intel.com> PR binutils/2258 * internal.h (ELF_IS_SECTION_IN_SEGMENT_FILE): New. (ELF_IS_SECTION_IN_SEGMENT_MEMORY): Likewise.
2006-02-07 * bfd/archures.c (bfd_mach_mcf5200, bfd_mach_mcf5206e,Nathan Sidwell3-22/+72
bfd_mach_mcf5307, bfd_mach_mcf5407, bfd_mach_mcf528x, bfd_mach_mcfv4e, bfd_mach_mcf521x, bfd_mach_mcf5249, bfd_mach_mcf547x, bfd_mach_mcf548x): Remove. (bfd_mach_mcf_isa_a, bfd_mach_mcf_isa_a_div, bfd_mach_mcf_isa_a_div_mac, bfd_mach_mcf_isa_a_div_emac, bfd_mach_mcf_isa_aplus, bfd_mach_mcf_isa_aplus_mac, bfd_mach_mcf_isa_aplus_emac, bfd_mach_mcf_isa_aplus_usp, bfd_mach_mcf_isa_aplus_usp_mac, bfd_mach_mcf_isa_aplus_usp_emac, bfd_mach_mcf_isa_b, bfd_mach_mcf_isa_b_mac, bfd_mach_mcf_isa_b_emac, bfd_mach_mcf_isa_b_usp_float, bfd_mach_mcf_isa_b_usp_float_mac, bfd_mach_mcf_isa_b_usp_float_emac): New. (bfd_default_scan): Update coldfire mapping. * bfd/bfd-in.h (bfd_m68k_mach_to_features, bfd_m68k_features_to_mach): Declare. * bfd/bfd-in2.h: Rebuilt. * bfd/cpu-m68k.c (arch_info_struct): Add new coldfire machines, adjust legacy names. (m68k_arch_features): New. (bfd_m68k_mach_to_features, bfd_m68k_features_to_mach): Define. * bfd/elf32-m68k.c (elf32_m68k_object_p): New. (elf32_m68k_merge_private_bfd_data): Merge the CF EF flags. (elf32_m68k_print_private_bfd_data): Print the CF EF flags. (elf_backend_object_p): Define. * bfd/ieee.c (ieee_write_processor): Update coldfire machines. * bfd/libbfd.h: Rebuilt. * gas/config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs, mcf5329_control_regs): New. (not_current_architecture, selected_arch, selected_cpu): New. (m68k_archs, m68k_extensions): New. (archs): Renamed to ... (m68k_cpus): ... here. Adjust. (n_arches): Remove. (md_pseudo_table): Add arch and cpu directives. (find_cf_chip, m68k_ip): Adjust table scanning. (no_68851, no_68881): Remove. (md_assemble): Lazily initialize. (select_control_regs): Adjust cpu names. Add 5208, 5213, 5329. (md_init_after_args): Move functionality to m68k_init_arch. (mri_chip): Adjust table scanning. (md_parse_option): Reimplement 'm' processing to add -march & -mcpu options with saner parsing. (m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension, m68k_init_arch): New. (s_m68k_cpu, s_m68k_arch): New. (md_show_usage): Adjust. (m68k_elf_final_processing): Set CF EF flags. * gas/config/tc-m68k.h (m68k_init_after_args): Remove. (tc_init_after_args): Remove. * gas/doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options. (M68k-Directives): Document .arch and .cpu directives. * gas/testsuite/gas/m68k/all.exp: Add arch-cpu-1 test. * gas/testsuite/gas/m68k/arch-cpu-1.[sd]: New. * include/elf/m68k.h (EF_CPU32, EF_M68000, EF_CFV4E): Rename to ... (EF_M68K_CPU32, EF_M68K_M68000, EF_M68K_CFV4E): ... here. (EF_M68K_ISA_MASK, EF_M68K_ISA_A, EF_M68K_M68K_ISA_A_PLUS, EF_M68K_ISA_B, EF_M68K_HW_DIV, EF_M68K_MAC_MASK, EF_M68K_MAC, EF_M68K_EMAC, EF_M68K_USP, EF_M68K_FLOAT): New. * include/opcode/m68k.h (m68008, m68ec030, m68882): Remove. (m68k_mask): New. (cpu_m68k, cpu_cf): New. (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407, mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants. * opcodes/m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features. * binutils/readelf.c (get_machine_flags): Add logic for EF_M68K flags.
2006-02-06 * elf/ia64.h (SHF_IA_64_HP_TLS): New.Steve Ellcey2-0/+6
2006-02-05Cleanup of pseudo-ops for constants and new def24,def32 pseudo-ops on z80Arnold Metselaar2-0/+5
2006-01-312006-01-31 Paul Brook <paul@codesourcery.com>Paul Brook2-48/+121
Richard Earnshaw <rearnsha@arm.com> * gas/config/tc-arm.c: Use arm_feature_set. (arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none, arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1, fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2): New variables. (insns): Use them. (md_atof, opcode_select, opcode_select, md_assemble, md_assemble, md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch, arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes, s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU feature flags. (arm_legacy_option_table, arm_option_cpu_value_table): New types. (arm_opts): Move old cpu/arch options from here... (arm_legacy_opts): ... to here. (md_parse_option): Search arm_legacy_opts. (arm_cpus, arm_archs, arm_extensions, arm_fpus) (arm_float_abis, arm_eabis): Make const. * include/opcode/arm.h: Use ARM_CPU_FEATURE. (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New. (arm_feature_set): Change to a structure. (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE, ARM_FEATURE): New macros.
2006-01-18include/elf/ChangeLog:Alexandre Oliva4-3/+28
Introduce TLS descriptors for i386 and x86_64. * common.h (DT_TLSDESC_GOT, DT_TLSDESC_PLT): New. * i386.h (R_386_TLS_GOTDESC, R_386_TLS_DESC_CALL, R_386_TLS_DESC): New. * x86-64.h (R_X86_64_GOTPC32_TLSDESC, R_X86_64_TLSDESC_CALL, R_X86_64_TLSDESC): New. bfd/ChangeLog: Introduce TLS descriptors for i386 and x86_64. * reloc.c (BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC, BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_GOTPC32_TLSDESC, BFD_RELOC_X86_64_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL): New. * libbfd.h, bfd-in2.h: Rebuilt. * elf32-i386.c (elf_howto_table): New relocations. (R_386_tls): Adjust. (elf_i386_reloc_type_lookup): Map new relocations. (GOT_TLS_GDESC, GOT_TLS_GD_BOTH_P): New macros. (GOT_TLS_GD_P, GOT_TLS_GDESC_P, GOT_TLS_GD_ANY_P): New macros. (struct elf_i386_link_hash_entry): Add tlsdesc_got field. (struct elf_i386_obj_tdata): Add local_tlsdesc_gotent field. (elf_i386_local_tlsdesc_gotent): New macro. (struct elf_i386_link_hash_table): Add sgotplt_jump_table_size. (elf_i386_compute_jump_table_size): New macro. (link_hash_newfunc): Initialize tlsdesc_got. (elf_i386_link_hash_table_create): Set sgotplt_jump_table_size. (elf_i386_tls_transition): Handle R_386_TLS_GOTDESC and R_386_TLS_DESC_CALL. (elf_i386_check_relocs): Likewise. Allocate space for local_tlsdesc_gotent. (elf_i386_gc_sweep_hook): Handle R_386_TLS_GOTDESC and R_386_TLS_DESC_CALL. (allocate_dynrelocs): Count function PLT relocations. Reserve space for TLS descriptors and relocations. (elf_i386_size_dynamic_sections): Reserve space for TLS descriptors and relocations. Set up sgotplt_jump_table_size. Don't zero reloc_count in srelplt. (elf_i386_always_size_sections): New. Set up _TLS_MODULE_BASE_. (elf_i386_relocate_section): Handle R_386_TLS_GOTDESC and R_386_TLS_DESC_CALL. (elf_i386_finish_dynamic_symbol): Use GOT_TLS_GD_ANY_P. (elf_backend_always_size_sections): Define. * elf64-x86-64.c (x86_64_elf_howto): Add R_X86_64_GOTPC32_TLSDESC, R_X86_64_TLSDESC, R_X86_64_TLSDESC_CALL. (R_X86_64_standard): Adjust. (x86_64_reloc_map): Map new relocs. (elf64_x86_64_rtype_to_howto): New, split out of... (elf64_x86_64_info_to_howto): ... this function, and... (elf64_x86_64_reloc_type_lookup): ... use it to map elf_reloc_val. (GOT_TLS_GDESC, GOT_TLS_GD_BOTH_P): New macros. (GOT_TLS_GD_P, GOT_TLS_GDESC_P, GOT_TLS_GD_ANY_P): New macros. (struct elf64_x86_64_link_hash_entry): Add tlsdesc_got field. (struct elf64_x86_64_obj_tdata): Add local_tlsdesc_gotent field. (elf64_x86_64_local_tlsdesc_gotent): New macro. (struct elf64_x86_64_link_hash_table): Add tlsdesc_plt, tlsdesc_got and sgotplt_jump_table_size fields. (elf64_x86_64_compute_jump_table_size): New macro. (link_hash_newfunc): Initialize tlsdesc_got. (elf64_x86_64_link_hash_table_create): Initialize new fields. (elf64_x86_64_tls_transition): Handle R_X86_64_GOTPC32_TLSDESC and R_X86_64_TLSDESC_CALL. (elf64_x86_64_check_relocs): Likewise. Allocate space for local_tlsdesc_gotent. (elf64_x86_64_gc_sweep_hook): Handle R_X86_64_GOTPC32_TLSDESC and R_X86_64_TLSDESC_CALL. (allocate_dynrelocs): Count function PLT relocations. Reserve space for TLS descriptors and relocations. (elf64_x86_64_size_dynamic_sections): Reserve space for TLS descriptors and relocations. Set up sgotplt_jump_table_size, tlsdesc_plt and tlsdesc_got. Make room for them. Don't zero reloc_count in srelplt. Add dynamic entries for DT_TLSDESC_PLT and DT_TLSDESC_GOT. (elf64_x86_64_always_size_sections): New. Set up _TLS_MODULE_BASE_. (elf64_x86_64_relocate_section): Handle R_386_TLS_GOTDESC and R_386_TLS_DESC_CALL. (elf64_x86_64_finish_dynamic_symbol): Use GOT_TLS_GD_ANY_P. (elf64_x86_64_finish_dynamic_sections): Set DT_TLSDESC_PLT and DT_TLSDESC_GOT. Set up TLS descriptor lazy resolver PLT entry. (elf_backend_always_size_sections): Define. binutils/ChangeLog: Introduce TLS descriptors for i386 and x86_64. * readelf.c (get_dynamic_type): Handle DT_TLSDESC_GOT and DT_TLSDESC_PLT. gas/ChangeLog: Introduce TLS descriptors for i386 and x86_64. * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_GOTPC32_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL. (optimize_disp): Emit fix up for BFD_RELOC_386_TLS_DESC_CALL and BFD_RELOC_X86_64_TLSDESC_CALL immediately, and clear the displacement bits. (build_modrm_byte): Set up zero modrm for TLS desc calls. (lex_got): Handle @tlsdesc and @tlscall. (md_apply_fix, tc_gen_reloc): Handle the new relocations. ld/testsuite/ChangeLog: Introduce TLS descriptors for i386 and x86_64. * ld-i386/i386.exp: Run on x86_64-*-linux* and amd64-*-linux*. Add new tests. * ld-i386/pcrel16.d: Add -melf_i386. * ld-i386/pcrel8.d: Likewise. * ld-i386/tlsbindesc.dd: New. * ld-i386/tlsbindesc.rd: New. * ld-i386/tlsbindesc.s: New. * ld-i386/tlsbindesc.sd: New. * ld-i386/tlsbindesc.td: New. * ld-i386/tlsdesc.dd: New. * ld-i386/tlsdesc.rd: New. * ld-i386/tlsdesc.s: New. * ld-i386/tlsdesc.sd: New. * ld-i386/tlsdesc.td: New. * ld-i386/tlsgdesc.dd: New. * ld-i386/tlsgdesc.rd: New. * ld-i386/tlsgdesc.s: New. * ld-x86-64/x86-64.exp: Run new tests. * ld-x86-64/tlsbindesc.dd: New. * ld-x86-64/tlsbindesc.rd: New. * ld-x86-64/tlsbindesc.s: New. * ld-x86-64/tlsbindesc.sd: New. * ld-x86-64/tlsbindesc.td: New. * ld-x86-64/tlsdesc.dd: New. * ld-x86-64/tlsdesc.pd: New. * ld-x86-64/tlsdesc.rd: New. * ld-x86-64/tlsdesc.s: New. * ld-x86-64/tlsdesc.sd: New. * ld-x86-64/tlsdesc.td: New. * ld-x86-64/tlsgdesc.dd: New. * ld-x86-64/tlsgdesc.rd: New. * ld-x86-64/tlsgdesc.s: New.
2006-01-18merge from gccDJ Delorie2-0/+6
2006-01-17 PR binutils/1486Andreas Schwab2-0/+9
binutils/: * configure.in: Don't define DISASSEMBLER_NEEDS_RELOCS. * configure: Regenerate. * objdump.c (struct objdump_disasm_info): Don't check for DISASSEMBLER_NEEDS_RELOCS. (objdump_print_addr): Likewise. (disassemble_bytes): Check disassembler_needs_relocs from disassemble_info at run-time instead of DISASSEMBLER_NEEDS_RELOCS at compile-time. (disassemble_section): Likewise. (disassemble_data): Initialize it. include/: * dis-asm.h (struct disassemble_info): Add disassembler_needs_relocs. objdump/: * disassemble.c (disassemble_init_for_target): Set disassembler_needs_relocs for bfd_arch_arm.
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