| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
* ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
opcodes/
* ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
* ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
(PPCVEC2, PPCTMR, E6500): New short names.
(powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
optional operands on sync instruction for E6500 target.
bfd/
* archures.c: Add bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500.
* bfd-in2.h: Regenerate.
* cpu-powerpc.c (bfd_powerpc_archs): Add entryies for
bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500.
gas/
* config/tc-ppc.c (md_show_usage): Document -me5500 and -me6500.
(ppc_handle_align): Add termination nop opcode for e500mc family.
* doc/as.texinfo: Document options -me5500 and -me6500.
* doc/c-ppc.texi: Likewise.
gas/testsuite/
* gas/ppc/e500mc64_nop.s: New test case for e500mc family
termination nops.
* gas/ppc/e500mc64_nop.d: Likewise.
* gas/ppc/e5500_nop.s: Likewise.
* gas/ppc/e5500_nop.d: Likewise.
* gas/ppc/e6500_nop.s: Likewise.
* gas/ppc/e6500_nop.d: Likewise.
* gas/ppc/e6500.s: New.
* gas/ppc/e6500.d: Likewise.
* gas/ppc/ppc.exp: Run e6500, e500mc64_nop, e5500_nop, and e6500_nop.
|
|
* lbr.h (struct vms_lhd): Add comments.
|
|
|
|
R_MN10300_TLS_LD, R_MN10300_TLS_LDO, R_MN10300_TLS_GOTIE,
R_MN10300_TLS_IE, R_MN10300_TLS_LE, R_MN10300_TLS_DPTMOD,
R_MN10300_TLS_DTPOFF and R_MN10300_TLS_TPOFF.
* elf-m10300.c (elf32_mn10300_link_hash_entry): Add tls_type
field.
(elf32_mn10300_link_hash_table): Add tls_ldm_got entry;
(elf_mn10300_tdata): Define.
(elf_mn10300_local_got_tls_type): Define.
(elf_mn10300_howto_table): Add entries for R_MN10300_TLS_GD,
R_MN10300_TLS_LD, R_MN10300_TLS_LDO, R_MN10300_TLS_GOTIE,
R_MN10300_TLS_IE, R_MN10300_TLS_LE, R_MN10300_TLS_DPTMOD,
R_MN10300_TLS_DTPOFF, R_MN10300_TLS_TPOFF relocs.
(mn10300_reloc_map): Likewise.
(elf_mn10300_tls_transition): New function.
(dtpoff, tpoff, mn10300_do_tls_transition): New functions.
(mn10300_elf_check_relocs): Add TLS support.
(mn10300_elf_final_link_relocate): Likewise.
(mn10300_elf_relocate_section): Likewise.
(mn10300_elf_relax_section): Likewise.
(elf32_mn10300_link_hash_newfunc): Initialise new field.
(_bfd_mn10300_copy_indirect_symbol): New function.
(elf32_mn10300_link_hash_table_create): Initialise new fields.
(_bfd_mn10300_elf_size_dynamic_sections): Add TLS support.
(_bfd_mn10300_elf_finish_dynamic_symbol): Likewise.
(_bfd_mn10300_elf_reloc_type_class): Allocate an
elf_mn10300_obj_tdata structure.
(elf_backend_copy_indirect_symbol): Define.
* reloc.c (BFD_MN10300_TLS_GD, BFD_MN10300_TLS_LD,
BFD_MN10300_TLS_LDO, BFD_MN10300_TLS_GOTIE, BFD_MN10300_TLS_IE,
BFD_MN10300_TLS_LE, BFD_MN10300_TLS_DPTMOD,
BFD_MN10300_TLS_DTPOFF, BFD_MN10300_TLS_TPOFF): New relocations.
(BFD_RELOC_MN10300_32_PCREL, BFD_RELOC_MN10300_16_PCREL): Move to
alongside other MN10300 relocations.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* config/tc-mn10300.c (other_registers): Add SSP and USP.
(md_assemble): Add support for TLS relocs.
(mn10300_parse_name): Likewise.
* readelf.c (is_16bit_abs_reloc): Add detection of R_MN10300_16.
|
|
* config/tc-crx.c: Include bfd_stdint.h.
(getconstant): Remove irrelevant comment. Don't fail due to
sign-extension of int mask.
(check_range): Rewrite using unsigned arithmetic throughout.
opcodes/
* crx-dis.c (print_arg): Mask constant to 32 bits.
* crx-opc.c (cst4_map): Use int array.
include/opcode/
* crx.h (cst4_map): Update declaration.
|
|
- Add support for TLS LE references.
- Support linker optimization of TLS references.
- Delete relocations of GOT/tp relative offsets beyond 32-bits.
This brings binutils in line with the support expected in gcc 4.7, for
TILE-Gx/TILEPro.
bfd/
* reloc.c: Add BFD_RELOC_TILEPRO_TLS_GD_CALL,
BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD,
BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD,
BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD,
BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD,
BFD_RELOC_TILEPRO_TLS_IE_LOAD, BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE,
BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE,
BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO,
BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO,
BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI,
BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI,
BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA,
BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA,
BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE,
BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE,
BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE,
BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE,
BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE,
BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE,
BFD_RELOC_TILEGX_TLS_GD_CALL, BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD,
BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD,
BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD,
BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD, BFD_RELOC_TILEGX_TLS_IE_LOAD,
BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD,
BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD,
BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD, BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD.
Delete BFD_RELOC_TILEGX_IMM16_X0_HW1_GOT,
BFD_RELOC_TILEGX_IMM16_X1_HW1_GOT,
BFD_RELOC_TILEGX_IMM16_X0_HW2_GOT,
BFD_RELOC_TILEGX_IMM16_X1_HW2_GOT,
BFD_RELOC_TILEGX_IMM16_X0_HW3_GOT,
BFD_RELOC_TILEGX_IMM16_X1_HW3_GOT,
BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_GOT,
BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_GOT,
BFD_RELOC_TILEGX_IMM16_X0_HW1_TLS_GD,
BFD_RELOC_TILEGX_IMM16_X1_HW1_TLS_GD,
BFD_RELOC_TILEGX_IMM16_X0_HW2_TLS_GD,
BFD_RELOC_TILEGX_IMM16_X1_HW2_TLS_GD,
BFD_RELOC_TILEGX_IMM16_X0_HW3_TLS_GD,
BFD_RELOC_TILEGX_IMM16_X1_HW3_TLS_GD,
BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_TLS_GD,
BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_TLS_GD,
BFD_RELOC_TILEGX_IMM16_X0_HW1_TLS_IE,
BFD_RELOC_TILEGX_IMM16_X1_HW1_TLS_IE,
BFD_RELOC_TILEGX_IMM16_X0_HW2_TLS_IE,
BFD_RELOC_TILEGX_IMM16_X1_HW2_TLS_IE,
BFD_RELOC_TILEGX_IMM16_X0_HW3_TLS_IE,
BFD_RELOC_TILEGX_IMM16_X1_HW3_TLS_IE,
BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_TLS_IE,
BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_TLS_IE.
* elf32-tilepro.c (tilepro_elf_howto_table): Update tilepro
relocations.
(tilepro_reloc_map): Ditto.
(tilepro_info_to_howto_rela): Ditto.
(reloc_to_create_func): Ditto.
(tilepro_tls_translate_to_le): New.
(tilepro_tls_translate_to_ie): New.
(tilepro_elf_tls_transition): New.
(tilepro_elf_check_relocs): Handle new tls relocations.
(tilepro_elf_gc_sweep_hook): Ditto.
(allocate_dynrelocs): Ditto.
(tilepro_elf_relocate_section): Ditto.
(tilepro_replace_insn): New.
(insn_mask_X1): New.
(insn_mask_X0_no_dest_no_srca): New
(insn_mask_X1_no_dest_no_srca): New
(insn_mask_Y0_no_dest_no_srca): New
(insn_mask_Y1_no_dest_no_srca): New
(srca_mask_X0): New
(srca_mask_X1): New
(insn_tls_le_move_X1): New
(insn_tls_le_move_zero_X0X1): New
(insn_tls_ie_lw_X1): New
(insn_tls_ie_add_X0X1): New
(insn_tls_ie_add_Y0Y1): New
(insn_tls_gd_add_X0X1): New
(insn_tls_gd_add_Y0Y1): New
* elfxx-tilegx.c (tilegx_elf_howto_table): Update tilegx
relocations.
(tilegx_reloc_map): Ditto.
(tilegx_info_to_howto_rela): Ditto.
(reloc_to_create_func): Ditto.
(tilegx_elf_link_hash_table): New field disable_le_transition.
(tilegx_tls_translate_to_le): New.
(tilegx_tls_translate_to_ie): New.
(tilegx_elf_tls_transition): New.
(tilegx_elf_check_relocs): Handle new tls relocations.
(tilegx_elf_gc_sweep_hook): Ditto.
(allocate_dynrelocs): Ditto.
(tilegx_elf_relocate_section): Ditto.
(tilegx_copy_bits): New.
(tilegx_replace_insn): New.
(insn_mask_X1): New.
(insn_mask_X0_no_dest_no_srca): New.
(insn_mask_X1_no_dest_no_srca): New.
(insn_mask_Y0_no_dest_no_srca): New.
(insn_mask_Y1_no_dest_no_srca): New.
(insn_mask_X0_no_operand): New.
(insn_mask_X1_no_operand): New.
(insn_mask_Y0_no_operand): New.
(insn_mask_Y1_no_operand): New.
(insn_tls_ie_ld_X1): New.
(insn_tls_ie_ld4s_X1): New.
(insn_tls_ie_add_X0X1): New.
(insn_tls_ie_add_Y0Y1): New.
(insn_tls_ie_addx_X0X1): New.
(insn_tls_ie_addx_Y0Y1): New.
(insn_tls_gd_add_X0X1): New.
(insn_tls_gd_add_Y0Y1): New.
(insn_move_X0X1): New.
(insn_move_Y0Y1): New.
(insn_add_X0X1): New.
(insn_add_Y0Y1): New.
(insn_addx_X0X1): New.
(insn_addx_Y0Y1): New.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* tc-tilepro.c (O_tls_le): Define operator.
(O_tls_le_lo16): Ditto.
(O_tls_le_hi16): Ditto.
(O_tls_le_ha16): Ditto.
(O_tls_gd_call): Ditto.
(O_tls_gd_add): Ditto.
(O_tls_ie_load): Ditto.
(md_begin): Delete old operators; handle new operators.
(emit_tilepro_instruction): Ditto.
(md_apply_fix): Ditto.
* tc-tilegx.c (O_hw1_got): Delete operator.
(O_hw2_got): Ditto.
(O_hw3_got): Ditto.
(O_hw2_last_got): Ditto.
(O_hw1_tls_gd): Ditto.
(O_hw2_tls_gd): Ditto.
(O_hw3_tls_gd): Ditto.
(O_hw2_last_tls_gd): Ditto.
(O_hw1_tls_ie): Ditto.
(O_hw2_tls_ie): Ditto.
(O_hw3_tls_ie): Ditto.
(O_hw2_last_tls_ie): Ditto.
(O_hw0_tls_le): Define operator.
(O_hw0_last_tls_le): Ditto.
(O_hw1_last_tls_le): Ditto.
(O_tls_gd_call): Ditto.
(O_tls_gd_add): Ditto.
(O_tls_ie_load): Ditto.
(O_tls_add): Ditto.
(md_begin): Delete old operators; handle new operators.
(emit_tilegx_instruction): Ditto.
(md_apply_fix): Ditto.
* doc/c-tilegx.texi: Delete old operators; document new operators.
* doc/c-tilepro.texi: Ditto.
include/elf/
* tilegx.h (R_TILEGX_IMM16_X0_HW1_GOT): Delete.
(R_TILEGX_IMM16_X1_HW1_GOT): Ditto.
(R_TILEGX_IMM16_X0_HW2_GOT): Ditto.
(R_TILEGX_IMM16_X1_HW2_GOT): Ditto.
(R_TILEGX_IMM16_X0_HW3_GOT): Ditto.
(R_TILEGX_IMM16_X1_HW3_GOT): Ditto.
(R_TILEGX_IMM16_X0_HW2_LAST_GOT): Ditto.
(R_TILEGX_IMM16_X1_HW2_LAST_GOT): Ditto.
(R_TILEGX_IMM16_X0_HW1_TLS_GD): Ditto.
(R_TILEGX_IMM16_X1_HW1_TLS_GD): Ditto.
(R_TILEGX_IMM16_X0_HW2_TLS_GD): Ditto.
(R_TILEGX_IMM16_X1_HW2_TLS_GD): Ditto.
(R_TILEGX_IMM16_X0_HW3_TLS_GD): Ditto.
(R_TILEGX_IMM16_X1_HW3_TLS_GD): Ditto.
(R_TILEGX_IMM16_X0_HW2_LAST_TLS_GD): Ditto.
(R_TILEGX_IMM16_X1_HW2_LAST_TLS_GD): Ditto.
(R_TILEGX_IMM16_X0_HW1_TLS_IE): Ditto.
(R_TILEGX_IMM16_X1_HW1_TLS_IE): Ditto.
(R_TILEGX_IMM16_X0_HW2_TLS_IE): Ditto.
(R_TILEGX_IMM16_X1_HW2_TLS_IE): Ditto.
(R_TILEGX_IMM16_X0_HW3_TLS_IE): Ditto.
(R_TILEGX_IMM16_X1_HW3_TLS_IE): Ditto.
(R_TILEGX_IMM16_X0_HW2_LAST_TLS_IE): Ditto.
(R_TILEGX_IMM16_X1_HW2_LAST_TLS_IE): Ditto.
(R_TILEGX_IMM16_X0_HW0_TLS_LE): New relocation.
(R_TILEGX_IMM16_X1_HW0_TLS_LE): Ditto.
(R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE): Ditto.
(R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE): Ditto.
(R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE): Ditto.
(R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE): Ditto.
(R_TILEGX_TLS_GD_CALL): Ditto.
(R_TILEGX_IMM8_X0_TLS_GD_ADD): Ditto.
(R_TILEGX_IMM8_X1_TLS_GD_ADD): Ditto.
(R_TILEGX_IMM8_Y0_TLS_GD_ADD): Ditto.
(R_TILEGX_IMM8_Y1_TLS_GD_ADD): Ditto.
(R_TILEGX_TLS_IE_LOAD): Ditto.
(R_TILEGX_IMM8_X0_TLS_ADD): Ditto.
(R_TILEGX_IMM8_X1_TLS_ADD): Ditto.
(R_TILEGX_IMM8_Y0_TLS_ADD): Ditto.
(R_TILEGX_IMM8_Y1_TLS_ADD): Ditto.
* tilepro.h (R_TILEPRO_TLS_GD_CALL): New relocation.
(R_TILEPRO_IMM8_X0_TLS_GD_ADD): Ditto.
(R_TILEPRO_IMM8_X1_TLS_GD_ADD): Ditto.
(R_TILEPRO_IMM8_Y0_TLS_GD_ADD): Ditto.
(R_TILEPRO_IMM8_Y1_TLS_GD_ADD): Ditto.
(R_TILEPRO_TLS_IE_LOAD): Ditto.
(R_TILEPRO_IMM16_X0_TLS_LE): Ditto.
(R_TILEPRO_IMM16_X1_TLS_LE): Ditto.
(R_TILEPRO_IMM16_X0_TLS_LE_LO): Ditto.
(R_TILEPRO_IMM16_X1_TLS_LE_LO): Ditto.
(R_TILEPRO_IMM16_X0_TLS_LE_HI): Ditto.
(R_TILEPRO_IMM16_X1_TLS_LE_HI): Ditto.
(R_TILEPRO_IMM16_X0_TLS_LE_HA): Ditto.
(R_TILEPRO_IMM16_X1_TLS_LE_HA): Ditto.
include/opcode/
* tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
TILEGX_OPC_LD_TLS.
* tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
TILEPRO_OPC_LW_TLS_SN.
opcodes/
* tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
* tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
TILEPRO_OPC_LW_TLS_SN.
|
|
BFD:
* mach-o.c (bfd_mach_o_swap_in_non_scattered_reloc): New.
(bfd_mach_o_canonicalize_one_reloc): Swap non-scattered reloc
bit-fields when target and host differ in endian-ness. When
PAIRs are non-scattered find the 'symbol' from the preceding
reloc. Add FIXME re. reloc symbols on section boundaries.
(bfd_mach_o_swap_out_non_scattered_reloc): New.
(bfd_mach_o_write_relocs): Use bfd_mach_o_encode_non_scattered_reloc.
include/mach-o:
* external.h: Add comments about relocations fields. Add macros
for non-scattered relocations. Move scattered relocation macros to here.
* reloc.h: Remove macros related to external representation of reloc fields.
|
|
gas/
2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (HLE_PREFIX): New.
(check_hle): Likewise.
(_i386_insn): Add have_hle.
(cpu_arch): Add .hle and .rtm.
(md_assemble): Call check_hle if i.have_hle isn't zero.
(parse_insn): Set i.have_hle to 1 for HLE prefix.
(output_jump): Support up to 2 byte opcode.
* doc/c-i386.texi: Document hle/.hle and rtm/.rtm.
gas/testsuite/
2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/hle-intel.d: New.
* gas/i386/hle.d: Likewise.
* gas/i386/hle.s: Likewise.
* gas/i386/hlebad.l: Likewise.
* gas/i386/hlebad.s: Likewise.
* gas/i386/rtm-intel.d: Likewise.
* gas/i386/rtm.d: Likewise.
* gas/i386/rtm.s: Likewise.
* gas/i386/x86-64-hle-intel.d: Likewise.
* gas/i386/x86-64-hle.d: Likewise.
* gas/i386/x86-64-hle.s: Likewise.
* gas/i386/x86-64-hlebad.l: Likewise.
* gas/i386/x86-64-hlebad.s: Likewise.
* gas/i386/x86-64-rtm-intel.d: Likewise.
* gas/i386/x86-64-rtm.d: Likewise.
* gas/i386/x86-64-rtm.s: Likewise.
* gas/i386/i386.exp: Run hle, hle-intel, hlebad x86-64-hle, rtm,
rtm-intel, x86-64-hle-intel, x86-64-hlebad, x86-64-rtm and
x86-64-rtm-intel.
include/opcode/
2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (XACQUIRE_PREFIX_OPCODE): New.
(XRELEASE_PREFIX_OPCODE): Likewise.
opcodes/
2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (HLE_Fixup1): New.
(HLE_Fixup2): Likewise.
(HLE_Fixup3): Likewise.
(Ebh1): Likewise.
(Evh1): Likewise.
(Ebh2): Likewise.
(Evh2): Likewise.
(Ebh3): Likewise.
(Evh3): Likewise.
(MOD_C6_REG_7): Likewise.
(MOD_C7_REG_7): Likewise.
(RM_C6_REG_7): Likewise.
(RM_C7_REG_7): Likewise.
(XACQUIRE_PREFIX): Likewise.
(XRELEASE_PREFIX): Likewise.
(dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
(reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
MOD_C6_REG_7 and MOD_C7_REG_7.
(mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
(rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
xtest.
(prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
(CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
* i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
CPU_RTM_FLAGS.
(cpu_flags): Add CpuHLE and CpuRTM.
(opcode_modifiers): Add HLEPrefixOk.
* i386-opc.h (CpuHLE): New.
(CpuRTM): Likewise.
(HLEPrefixOk): Likewise.
(i386_cpu_flags): Add cpuhle and cpurtm.
(i386_opcode_modifier): Add hleprefixok.
* i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
operand. Add xacquire, xrelease, xabort, xbegin, xend and
xtest.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
|
|
|
|
|
|
bfd/
2012-01-31 H.J. Lu <hongjiu.lu@intel.com>
PR ld/13616
* archures.c (bfd_arch_info): Add fill.
(bfd_default_arch_struct): Add bfd_arch_default_fill.
(bfd_arch_default_fill): New.
* configure.in: Set bfd version to 2.22.52.
* configure: Regenerated.
* cpu-alpha.c: Add bfd_arch_default_fill to bfd_arch_info
initializer.
* cpu-arc.c: Likewise.
* cpu-arm.c: Likewise.
* cpu-avr.c: Likewise.
* cpu-bfin.c: Likewise.
* cpu-cr16.c: Likewise.
* cpu-cr16c.c: Likewise.
* cpu-cris.c: Likewise.
* cpu-crx.c: Likewise.
* cpu-d10v.c: Likewise.
* cpu-d30v.c: Likewise.
* cpu-dlx.c: Likewise.
* cpu-epiphany.c: Likewise.
* cpu-fr30.c: Likewise.
* cpu-frv.c: Likewise.
* cpu-h8300.c: Likewise.
* cpu-h8500.c: Likewise.
* cpu-hppa.c: Likewise.
* cpu-i370.c: Likewise.
* cpu-i860.c: Likewise.
* cpu-i960.c: Likewise.
* cpu-ia64.c: Likewise.
* cpu-ip2k.c: Likewise.
* cpu-iq2000.c: Likewise.
* cpu-lm32.c: Likewise.
* cpu-m10200.c: Likewise.
* cpu-m10300.c: Likewise.
* cpu-m32c.c: Likewise.
* cpu-m32r.c: Likewise.
* cpu-m68hc11.c: Likewise.
* cpu-m68hc12.c: Likewise.
* cpu-m68k.c: Likewise.
* cpu-m88k.c: Likewise.
* cpu-mcore.c: Likewise.
* cpu-mep.c: Likewise.
* cpu-microblaze.c: Likewise.
* cpu-mips.c: Likewise.
* cpu-mmix.c: Likewise.
* cpu-moxie.c: Likewise.
* cpu-msp430.c: Likewise.
* cpu-mt.c: Likewise.
* cpu-ns32k.c: Likewise.
* cpu-openrisc.c: Likewise.
* cpu-or32.c: Likewise.
* cpu-pdp11.c: Likewise.
* cpu-pj.c: Likewise.
* cpu-plugin.c: Likewise.
* cpu-powerpc.c: Likewise.
* cpu-rl78.c: Likewise.
* cpu-rs6000.c: Likewise.
* cpu-rx.c: Likewise.
* cpu-s390.c: Likewise.
* cpu-score.c: Likewise.
* cpu-sh.c: Likewise.
* cpu-sparc.c: Likewise.
* cpu-spu.c: Likewise.
* cpu-tic30.c: Likewise.
* cpu-tic4x.c: Likewise.
* cpu-tic54x.c: Likewise.
* cpu-tic6x.c: Likewise.
* cpu-tic80.c: Likewise.
* cpu-tilegx.c: Likewise.
* cpu-tilepro.c: Likewise.
* cpu-v850.c: Likewise.
* cpu-vax.c: Likewise.
* cpu-w65.c: Likewise.
* cpu-we32k.c: Likewise.
* cpu-xc16x.c: Likewise.
* cpu-xstormy16.c: Likewise.
* cpu-xtensa.c: Likewise.
* cpu-z80.c: Likewise.
* cpu-z8k.c: Likewise.
* cpu-i386.c: Include "libiberty.h".
(bfd_arch_i386_fill): New.
Add bfd_arch_i386_fill to bfd_arch_info initializer.
* cpu-k1om.c: Add bfd_arch_i386_fill to bfd_arch_info initializer.
* cpu-l1om.c: Likewise.
* linker.c (default_data_link_order): Call abfd->arch_info->fill
if fill size is 0.
* bfd-in2.h: Regenerated.
include/
2012-01-31 H.J. Lu <hongjiu.lu@intel.com>
PR ld/13616
* bfdlink.h (bfd_link_order): Update comments on data size.
ld/
2012-01-31 H.J. Lu <hongjiu.lu@intel.com>
PR ld/13616
* emulparams/elf32_x86_64.sh: Remove NOP.
* emulparams/elf_i386.sh: Likewise.
* emulparams/elf_i386_be.sh: Likewise.
* emulparams/elf_i386_ldso.sh: Likewise.
* emulparams/elf_i386_vxworks.sh: Likewise.
* emulparams/elf_k1om.sh: Likewise.
* emulparams/elf_l1om.sh: Likewise.
* emulparams/elf_x86_64.sh: Likewise.
* ldlang.c (zero_fill): Initialized to 0.
* ldwrite.c (build_link_order): Set data size to linker odrder
size when they are the same.
* scripttempl/elf.sc: Don't specify fill if NOP is undefined.
ld/testsuite/
2012-01-31 H.J. Lu <hongjiu.lu@intel.com>
PR ld/13616
* ld-i386/tlsbindesc.dd: Update no-op padding.
* ld-i386/tlsnopic.dd: Likewise.
* ld-i386/tlspic.dd: Likewise.
* ld-x86-64/tlsbin.dd: Likewise.
* ld-x86-64/tlsbindesc.dd: Likewise.
* ld-x86-64/tlspic.dd: Likewise.
|
|
(enum dwarf_attribute): Likewise.
|
|
bfd:
* mach-o.c (bfd_mach_o_count_indirect_symbols): New.
(bfd_mach_o_build_dysymtab_command): Populate indirect symbol table.
* mach-o.h (bfd_mach_o_asymbol): Move declaration to start of the
file. (bfd_mach_o_section): Add indirect_syms field.
gas:
* config/obj-macho.c (obj_mach_o_set_symbol_qualifier): Switch off
lazy when the symbol is private_extern.
(obj_mach_o_indirect_sym): New type.
(obj_mach_o_indirect_symbol): New.
(mach_o_pseudo_table): Use obj_mach_o_indirect_symbol.
(obj_macho_frob_label): Adjust to avoid adding bsyms for locals.
(obj_macho_frob_label): Likewise. Adjust external and comm
symbol tests.
(obj_mach_o_set_indirect_symbols): New.
(obj_mach_o_frob_file_after_relocs): New.
*config/obj-macho.h (obj_frob_file_after_relocs): Define.
(obj_mach_o_frob_file_after_relocs): Declare.
include/mach-o:
* loader.h (BFD_MACH_O_INDIRECT_SYM_LOCAL): New.
(BFD_MACH_O_INDIRECT_SYM_ABS): New
gas/testsuite:
* gas/mach-o/dysymtab-2.d: New.
* gas/mach-o/err-syms-4.s: New.
* gas/mach-o/err-syms-5.s: New.
* gas/mach-o/err-syms-6.s: New.
* gas/mach-o/symbols-6-64.d: New.
* gas/mach-o/symbols-6-64.s: New.
* gas/mach-o/symbols-6.d: New.
* gas/mach-o/symbols-6.s: New.
|
|
|
|
2012-01-04 Tristan Gingold <gingold@adacore.com>
* mach-o.h (bfd_mach_o_fvmlib_command): New structure.
(bfd_mach_o_load_command): Add fvmlib field.
* mach-o.c (bfd_mach_o_read_fvmlib): New function.
(bfd_mach_o_read_command): Handle fvmlib.
binutils/
2012-01-04 Tristan Gingold <gingold@adacore.com>
* od-macho.c (dump_load_command): Handle fvmlib.
include/mach-o/
2012-01-04 Tristan Gingold <gingold@adacore.com>
* external.h (mach_o_fvmlib_command_external): New structure.
|
|
2012-01-04 Tristan Gingold <gingold@adacore.com>
* mach-o.c (bfd_mach_o_convert_architecture): Reindent.
Decode msubtype for ARM.
include/mach-o/
2012-01-04 Tristan Gingold <gingold@adacore.com>
* loader.h: Update copyright year.
(bfd_mach_o_cpu_subtype): Add ARM subtypes.
|
|
2012-01-04 Tristan Gingold <gingold@adacore.com>
* mach-o.h: Reindent header.
(bfd_mach_o_encryption_info_command): New structure.
(bfd_mach_o_load_command): Add encryption_info field.
* mach-o.c (bfd_mach_o_read_encryption_info): New function.
(bfd_mach_o_read_command): Handle BFD_MACH_O_LC_ENCRYPTION_INFO.
(bfd_mach_o_read_command): Adjust error message.
binutils/
2012-01-04 Tristan Gingold <gingold@adacore.com>
* od-macho.c: Update copyright year.
(dump_load_command): Handle BFD_MACH_O_LC_ENCRYPTION_INFO.
include/mach-o/
2012-01-04 Tristan Gingold <gingold@adacore.com>
* external.h: Update copyright year.
(mach_o_symtab_command_external): Add comments.
(mach_o_encryption_info_command_external): New structure.
|
|
gdb/ChangeLog:
Copyright year update in most files of the GDB Project.
|
|
* elf32-rl78.c (rl78_elf_howto_table): Add R_RL78_RH_RELAX.
(rl78_reloc_map): Add BFD_RELOC_RL78_RELAX.
(rl78_elf_relocate_section): Add R_RL78_RH_RELAX, R_RL78_RH_SFR,
and R_RL78_RH_SADDR.
(rl78_elf_finish_dynamic_sections): Only validate PLT section if
we didn't relax anything, as relaxing might remove a PLT reference
after we've set up the table.
(elf32_rl78_relax_delete_bytes): New.
(reloc_bubblesort): New.
(rl78_offset_for_reloc): New.
(relax_addr16): New.
(rl78_elf_relax_section): Add support for relaxing long
instructions into short ones.
[gas]
* config/rl78-defs.h (rl78_linkrelax_addr16): Add.
(rl78_linkrelax_dsp, rl78_linkrelax_imm): Remove.
* config/rl78-parse.y: Tag all addr16 and branch patterns with
relaxation markers.
* config/tc-rl78.c (rl78_linkrelax_addr16): New.
(rl78_linkrelax_branch): New.
(OPTION_RELAX): New.
(md_longopts): Add relax option.
(md_parse_option): Add OPTION_RELAX.
(rl78_frag_init): Support relaxation.
(rl78_handle_align): New.
(md_assemble): Support relaxation.
(md_apply_fix): Likewise.
(md_convert_frag): Likewise.
* config/tc-rl78.h (MAX_MEM_FOR_RS_ALIGN_CODE): New.
(HANDLE_ALIGN): New.
(rl78_handle_align): Declare.
* config/rl78-parse.y (rl78_bit_insn): New. Set it for all bit
insn patterns.
(find_bit_index): New. Strip .BIT suffix off relevent
expressions for bit insns.
(rl78_lex): Exclude bit suffixes from expression parsing.
[include/elf]
* rl78.h (R_RL78_RH_RELAX, R_RL78_RH_SFR, R_RL78_RH_SADDR): New.
(RL78_RELAXA_BRA, RL78_RELAXA_ADDR16: New.
|
|
gas/
* config/tc-mips.c (mips_pseudo_table): Add tprelword/tpreldword
entries.
(mips16_percent_op): Add MIPS16 TLS relocation ops.
(md_apply_fix): Add BFD_RELOC_MIPS16_TLS_* switch cases.
(s_tls_rel_directive): Rename from s_dtprel_internal(). Abstract out
directive string and reloc type as function parameters. Update
comments.
(s_dtprelword,s_dtpreldword): Change to use s_tls_rel_directive().
(s_tprelword,s_tpreldword): New functions.
include/
* elf/mips.h (elf_mips_reloc_type): Add R_MIPS16_TLS_* entries.
bfd/
* reloc.c (BFD_RELOC_MIPS16_TLS_GD,BFD_RELOC_MIPS16_TLS_LDM,
BFD_RELOC_MIPS16_TLS_DTPREL_HI16,BFD_RELOC_MIPS16_TLS_DTPREL_LO16,
BFD_RELOC_MIPS16_TLS_GOTTPREL,BFD_RELOC_MIPS16_TLS_TPREL_HI16,
BFD_RELOC_MIPS16_TLS_TPREL_LO16): New relocations for MIPS16 TLS.
* bfd-in2.h (bfd_reloc_code_real): Regenerate.
* libbfd.h (bfd_reloc_code_real_names): Regenerate.
* elf32-mips.c (elf_mips16_howto_table_rel): Add R_MIPS16_TLS_*
entries.
(mips16_reloc_map): Add BFD_RELOC_MIPS16_TLS_* to R_MIPS16_TLS_*
mappings.
* elfn32-mips.c (elf_mips16_howto_table_rel,
elf_mips16_howto_table_rela): Add R_MIPS16_TLS_* entries.
(mips16_reloc_map): Add BFD_RELOC_MIPS16_TLS_* to R_MIPS16_TLS_*
mappings.
* elf64-mips.c (mips16_elf64_howto_table_rel,
mips16_elf64_howto_table_rela): Add R_MIPS16_TLS_* entries.
(mips16_reloc_map): Add BFD_RELOC_MIPS16_TLS_* to R_MIPS16_TLS_*
mappings.
* elfxx-mips.c (TLS_RELOC_P,mips16_reloc_p,
_bfd_mips_elf_check_relocs): Add cases for R_MIPS16_TLS_* relocations.
(tls_gd_reloc_p): Add R_MIPS16_TLS_GD case.
(tls_ldm_reloc_p): Add R_MIPS16_TLS_LDM case.
(tls_gottprel_reloc_p): Add R_MIPS16_TLS_GOTTPREL case.
(mips_elf_calculate_relocation): Add cases for R_MIPS16_TLS_*,
R_MIPS_TLS_DTPREL32/64, and R_MIPS_TLS_TPREL32/64 relocations.
|
|
2011-12-16 Tristan Gingold <gingold@adacore.com>
* od-macho.c: Include mach-o/codesign.h
(OPT_CODESIGN): Define.
(options): Add an entry for codesign.
(mach_o_help): Likewise.
(dump_header): Fix indentation.
(dump_thread): Do not test result of xmalloc.
(bfd_mach_o_cs_magic, bfd_mach_o_cs_hash_type): New.
(dump_code_signature_superblob): New function.
(swap_code_codedirectory_v1_in): Likewise.
(hexdump): Likewise.
(dump_code_signature_codedirectory): Likewise.
(dump_code_signature_blob, dump_code_signature): Likewise.
(dump_load_command): Dump code signature.
(mach_o_dump): Likewise.
include/mach-o/
2011-12-16 Tristan Gingold <gingold@adacore.com>
* codesign.h: New file.
|
|
2011-12-14 Iain Sandoe <iains@gcc.gnu.org>
* mach-o-i386.c (text_section_names_xlat): New table.
(data_section_names_xlat): Likewise.
(import_section_names_xlat): Likewise.
(mach_o_i386_segsec_names_xlat): Likewise.
(bfd_mach_o_tgt_seg_table): Use new tables.
* mach-o-x86-64.c (bfd_mach_o_tgt_seg_table): Set NULL.
* mach-o.c (mach_o_section_name_xlat, mach_o_segment_name_xlat):
Move to mach-o.h as typedefs.
(text_section_names_xlat): Update for current GCC usage.
(data_section_names_xlat): Likewise.
(dwarf_section_names_xlat): Likewise.
(objc_section_names_xlat): New table.
(segsec_names_xlat): Add objc table.
(bfd_mach_o_normalize_section_name): Replace with...
(bfd_mach_o_section_data_for_mach_sect): New.
(bfd_mach_o_section_data_for_bfd_name): New.
(bfd_mach_o_section_data_for_bfd_name): Update to use additional data.
(bfd_mach_o_convert_section_name_to_mach_o): Likewise.
(bfd_mach_o_bfd_copy_private_section_data): Implement.
(bfd_mach_o_write_symtab): Write a zero-length string as the first entry
for compatibility with system tools.
(bfd_mach_o_build_commands): Update section alignment info.
(bfd_mach_o_new_section_hook): Use translation table data to define
default section flags, type, attributes and alignment, when available.
(bfd_mach_o_init_section_from_mach_o): Add TODO comment.
(bfd_mach_o_section_type_name): Add 'symbol_stubs'.
(bfd_mach_o_section_attribute_name): Add 'self_modifying_code'.
(bfd_mach_o_get_section_type_from_name): Change "not-found" return
value.
(bfd_mach_o_tgt_seg_table): Set default NULL.
* mach-o.h (bfd_mach_o_segment_command): Use define for name length.
(bfd_mach_o_backend_data): Move until after contents are defined.
(bfd_mach_o_normalize_section_name): Remove.
(bfd_mach_o_convert_section_name_to_bfd): Declare.
(mach_o_section_name_xlat): Declare.
(mach_o_segment_name_xlat): Declare.
(bfd_mach_o_section_data_for_mach_sect): Declare.
(bfd_mach_o_section_data_for_bfd_name): Declare.
include/
2011-12-14 Iain Sandoe <iains@gcc.gnu.org>
* mach-o/loader.h (bfd_mach_o_section_type): define
BFD_MACH_O_S_ATTR_NONE to 0.
gas/
2011-12-14 Iain Sandoe <iains@gcc.gnu.org>
* config/obj-macho.c: Add some more top-level comments.
(collect_16char_name): New.
(obj_mach_o_section): Amend to allow syntax compatible with existing system
tools. Use section translation data when available.
(obj_mach_o_segT_from_bfd_name): New.
(known_sections): Update.
(obj_mach_o_known_section): Use obj_mach_o_segT_from_bfd_name.
(objc_sections): New.
(obj_mach_o_objc_section): New.
(debug_sections): New.
(obj_mach_o_debug_section): New.
(tgt_sections): New.
(obj_mach_o_opt_tgt_section): New.
(obj_mach_o_base_section): New.
(obj_mach_o_common_parse): Update to create BSS on demand and to handle
lcomm optional alignment param.
(obj_mach_o_comm): Update parameter name.
(obj_mach_o_placeholder): New.
(mach_o_pseudo_table): Update for GCC section directives.
* config/obj-macho.h (_OBJ_MACH_O_H): New.
(USE_ALIGN_PTWO): Define.
(S_SET_ALIGN) Define.
|
|
2011-12-08 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* archures.c (bfd_mach_mips_octeon2): New macro
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsocteon2): New enum value.
(arch_info_struct): Add bfd_mach_mips_octeon2.
* elfxx-mips.c (_bfd_elf_mips_mach): Support E_MIPS_MACH_OCTEON2.
(mips_set_isa_flags): Add bfd_mach_mips_octeon2.
(mips_mach_extensions): Add bfd_mach_mips_octeon2.
gas:
2011-12-08 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* tc-mips.c (CPU_IS_OCTEON): Add Octeon2.
(mips_cpu_info_table): Add Octeon2.
* doc/c-mips.texi: Document octeon2 as an acceptable value for -march=.
gas/testsuite:
2011-12-08 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* gas/mips/mips.exp: Add Octeon2 for an architecture.
Run octeon2 test.
* gas/mips/octeon2.d: New file.
* gas/mips/octeon2.s: New file.
include/opcode:
2011-12-08 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
(INSN_OCTEON2): New macro.
(CPU_OCTEON2): New macro.
(OPCODE_IS_MEMBER): Add Octeon2.
opcodes:
2011-12-08 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* mips-dis.c (mips_arch_choices): Add Octeon2.
For "octeon+", just include OcteonP for the insn.
* mips-opc.c (IOCT): Include Octeon2.
(IOCTP): Include Octeon2.
(IOCT2): New macro.
(mips_builtin_opcodes): Add "laa", "laad", "lac", "lacd", "lad",
"ladd", "lai", "laid", "las", "lasd", "law", "lawd".
Move "lbux", "ldx", "lhx", "lwx", and "lwux" up to where the standard
loads are, and add IOCT2 to them.
Add "lbx" and "lhux".
Add "qmac.00", "qmac.01", "qmac.02", "qmac.03", "qmacs.00",
"qmacs.01", "qmacs.01", "qmacs.02" and "qmacs.03".
Add "zcb" and "zcbt".
|
|
* common.h (NT_S390_LAST_BREAK): Define.
(NT_S390_SYSTEM_CALL): Likewise.
bfd/ChangeLog:
* elf-bfd.h (elfcore_write_s390_last_break): Add prototype.
(elfcore_write_s390_system_call): Likewise.
* elf.c (elfcore_write_s390_last_break): New function.
(elfcore_write_s390_system_call): Likewise.
(elfcore_write_register_note): Call them.
(elfcore_grok_s390_last_break): New function.
(elfcore_grok_s390_system_call): Likewise.
(elfcore_grok_note): Call them.
|
|
The common sim code provides a useful "get_string" function which reads
a C string out of the target's memory space. So rename and export it
for other people to use.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
|
2011-11-29 Andrew Pinski <apinski@cavium.com>
* mips-dis.c (mips_arch_choices): Add Octeon+.
* mips-opc.c (IOCT): Include Octeon+.
(IOCTP): New macro.
(mips_builtin_opcodes): Add "saa" and "saad".
bfd/
2011-11-29 Andrew Pinski <apinski@cavium.com>
* archures.c (bfd_mach_mips_octeonp): New macro.
* bfd-in2.h: Regenerate.
* bfd/cpu-mips.c (I_mipsocteonp): New enum value.
(arch_info_struct): Add bfd_mach_mips_octeonp.
* elfxx-mips.c (mips_set_isa_flags): Add bfd_mach_mips_octeonp.
(mips_mach_extensions): Add bfd_mach_mips_octeonp.
include/opcodes/
2011-11-29 Andrew Pinski <apinski@cavium.com>
* mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
(INSN_OCTEONP): New macro.
(CPU_OCTEONP): New macro.
(OPCODE_IS_MEMBER): Add Octeon+.
(M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
gas/
2011-11-29 Andrew Pinski <apinski@cavium.com>
* config/tc-mips.c (CPU_IS_OCTEON): New macro function.
(CPU_HAS_SEQ): Change to use CPU_IS_OCTEON.
(NO_ISA_COP): Likewise.
(macro) <ld_st>: Add support when off0 is true.
Add support for M_SAA_AB, M_SAA_OB, M_SAAD_OB and M_SAAD_AB.
(mips_cpu_info_table): Add octeon+.
* doc/c-mips.texi: Document octeon+ as an acceptable value for -march=.
gas/testsuite/
2011-11-29 Andrew Pinski <apinski@cavium.com>
* gas/mips/mips.exp: Add octeon+ for an architecture.
Run octeon-saa-saad test.
(run_dump_test_arch): For Octeon architectures, also try octeon@.
* gas/mips/octeon-pref.d: Remove -march=octeon from command line.
* gas/mips/octeon.d: Likewise.
* gas/mips/octeon-saa-saad.d: New file.
* gas/mips/octeon-saa-saad.s: New file
|
|
|
|
* configure.ac (rl78-*-*) New case.
* configure: Regenerate.
[bfd]
* Makefile.am (ALL_MACHINES): Add cpu-rl78.lo.
(ALL_MACHINES_CFILES): Add cpu-rl78.c.
(BFD32_BACKENDS): Add elf32-rl78.lo.
(BFD32_BACKENDS_CFILES): Add elf32-rl78.c.
(Makefile.in): Regenerate.
* archures.c (bfd_architecture): Define bfd_arch_rl78.
(bfd_archures_list): Add bfd_rl78_arch.
* config.bfd: Add rl78-*-elf.
* configure.in: Add bfd_elf32_rl78_vec.
* reloc.c (bfd_reloc_code_type): Add BFD_RELOC_RL78_* relocations.
* targets.c (bfd_target_vector): Add bfd_elf32_rl78_vec.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* libbfd.h: Regenerate.
* cpu-rl78.c: New file.
* elf32-rl78.c: New file.
[binutils]
* readelf.c: Include elf/rl78.h
(guess_is_rela): Handle EM_RL78.
(dump_relocations): Likewise.
(get_machine_name): Likewise.
(is_32bit_abs_reloc): Likewise.
* NEWS: Mention addition of RL78 support.
* MAINTAINERS: Add myself as RL78 port maintainer.
[gas]
* Makefile.am (TARGET_CPU_CFILES): Add tc-rl78.c.
(TARGET_CPU_HFILES): Add rc-rl78.h.
(EXTRA_DIST): Add rl78-parse.c and rl78-parse.y.
(rl78-parse.c, rl78-parse.h, rl78-parse.o, rl78-defs.h): New rules.
* Makefile.in: Regenerate.
* configure.in: Add rl78 case.
* configure: Regenerate.
* configure.tgt: Add rl78 case.
* config/rl78-defs.h: New file.
* config/rl78-parse.y: New file.
* config/tc-rl78.c: New file.
* config/tc-rl78.h: New file.
* NEWS: Add Renesas RL78.
* doc/Makefile.am (c-rl78.texi): New.
* doc/Makefile.in: Likewise.
* doc/all.texi: Enable it.
* doc/as.texi: Add it.
[include]
* dis-asm.h (print_insn_rl78): Declare.
[include/elf]
* common.h (EM_RL78, EM_78K0R): New.
* rl78.h: New.
[include/opcode]
* rl78.h: New file.
[ld]
* Makefile.am (ALL_EMULATION_SOURCES): Add eelf32rl78.c.
(+eelf32rl78.c): New rule.
* Makefile.in: Regenerate.
* configure.tgt: Add rl78-*-* case.
* emulparams/elf32rl78.sh: New file.
* NEWS: Mention addition of Renesas RL78 support.
[opcodes]
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add rl78-decode.c and
rl78-dis.c.
(MAINTAINERCLEANFILES): Add rl78-decode.c.
(rl78-decode.c): New rule, built from rl78-decode.opc and opc2c.
* Makefile.in: Regenerate.
* configure.in: Add bfd_rl78_arch case.
* configure: Regenerate.
* disassemble.c: Define ARCH_rl78.
(disassembler): Add ARCH_rl78 case.
* rl78-decode.c: New file.
* rl78-decode.opc: New file.
* rl78-dis.c: New file.
|
|
* cpu-epiphany.c: Reinstate full list of Copyright years.
* elf32-epiphany.c: Likewise.
cpu:
* epiphany.cpu, epiphany.opc: Likewise.
gas:
* config/tc-epiphany.c, config/tc-epiphany.h: Likewise.
* doc/c-epiphany.texi: Likewise.
include:
* elf/epiphany.h: Likewise.
|
|
* Makefile.am (ALL_MACHINES): Add cpu-epiphany.lo .
(ALL_MACHINES_CFILES): Add cpu-epiphany.c .
(BFD32_BACKENDS): Add elf32-epiphany.lo .
(BFD32_BACKENDS_CFILES): Add elf32-epiphany.c .
* Makefile.in, bfd-in2.h, configure, libbfd.h: Regenerate.
* archures.c (bfd_arch_epiphany): Add.
(bfd_mach_epiphany16, bfd_mach_epiphany32): Define.
(bfd_epiphany_arch): Declare.
(bfd_archures_list): Add &bfd_epiphany_arch.
* config.bfd (epiphany-*-elf): New target case.
* configure.in (bfd_elf32_epiphany_vec): New target vector case.
* reloc.c (BFD_RELOC_EPIPHANY_SIMM8): New relocation.
(BFD_RELOC_EPIPHANY_SIMM24, BFD_RELOC_EPIPHANY_HIGH): Likewise.
(BFD_RELOC_EPIPHANY_LOW, BFD_RELOC_EPIPHANY_SIMM11): Likewise.
(BFD_RELOC_EPIPHANY_IMM11, BFD_RELOC_EPIPHANY_IMM8): Likewise.
* targets.c (bfd_elf32_epiphany_vec): Declare.
(_bfd_target_vector): Add bfd_elf32_epiphany_vec.
* po/SRC-POTFILES.in, po/bfd.pot: Regenerate.
* cpu-epiphany.c, elf32-epiphany.c: New files.
binutils:
* readelf.c (include "elf/epiphany.h")
(guess_is_rela, dump_relocation): Handle EM_ADAPTEVA_EPIPHANY.
(get_machine_name, is_32bit_abs_reloc, is_32bit_pcrel_reloc): Likewise.
(is_16bit_abs_reloc, is_none_reloc): Likewise.
* po/binutils.pot: Regenerate.
cpu:
* cpu/epiphany.cpu, cpu/epiphany.opc: New files.
gas:
* NEWS: Mention addition of Adapteva Epiphany support.
* config/tc-epiphany.c, config/tc-epiphany.h: New files.
* Makefile.am (TARGET_CPU_CFILES): Add config/tc-epiphany.c .
(TARGET_CPU_HFILES): Add config/tc-epiphany.h .
* Makefile.in, configure, doc/Makefile.in, po/POTFILES.in: Regenerate.
* configure.in: Also set using_cgen for epiphany.
* configure.tgt: Handle epiphany.
* doc/Makefile.am (CPU_DOCS): Add c-epiphany.texi .
* doc/all.texi: Set EPIPHANY.
* doc/as.texinfo: Add EPIPHANY-specific text.
* doc/c-epiphany.texi: New file.
* po/gas.pot: Regenerate.
gas/testsuite:
* gas/epiphany: New directory.
include:
* dis-asm.h (print_insn_epiphany): Declare.
* elf/epiphany.h: New file.
* elf/common.h (EM_ADAPTEVA_EPIPHANY): Define.
ld:
* NEWS: Mention addition of Adapteva Epiphany support.
* Makefile.am (ALL_EMULATION_SOURCES): Add eelf32epiphany.c .
(eelf32epiphany.c): New rule.
* Makefile.in: Regenerate.
* configure.tgt: Handle epiphany-*-elf.
* po/ld.pot: Regenerate.
* testsuite/ld-srec/srec.exp: xfail epiphany.
* emulparams/elf32epiphany.sh: New file.
opcodes:
* Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
(TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c,
epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
(CLEANFILES): Add stamp-epiphany.
(EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it.
(stamp-epiphany): New rule.
* Makefile.in, configure, po/POTFILES.in, po/opcodes.pot: Regenerate.
* configure.in: Handle bfd_epiphany_arch.
* disassemble.c (ARCH_epiphany): Define.
(disassembler): Handle bfd_arch_epiphany.
* epiphany-asm.c, epiphany-desc.c, epiphany-desc.h: New files.
* epiphany-dis.c, epiphany-ibld.c, epiphany-opc.c: Likewise.
* epiphany-opc.h: Likewise.
|
|
|
|
* ansidecl.h (ENUM_BITFIELD): Always use enum in C++
|
|
include/
* bfdlink.h (struct bfd_link_info): Add error_textrel.
bfd/
* elflink.c (bfd_elf_final_link): Emit error_textrel error.
ld/
* emultempl/elf32.em (gld${EMULATION_NAME}_handle_option): Add
-z text, -z notext, -z textoff options for all targets having
shared lib support.
|
|
* ppc64.h (R_PPC64_TOCSAVE): Add.
bfd/
* elf64-ppc.c (ppc64_elf_howto_table): Add R_PPC64_TOCSAVE entry.
(struct ppc_link_hash_table): Add tocsave_htab.
(struct tocsave_entry): New.
(tocsave_htab_hash, tocsave_htab_eq, tocsave_find): New functions.
(ppc64_elf_link_hash_table_create): Create tocsave_htab..
(ppc64_elf_link_hash_table_free): ..and delete it.
(build_plt_stub): Always put STD_R2_40R1 first.
(ppc64_elf_size_stubs): Check for R_PPC64_TOCSAVE following reloc
on plt call. If present add prologue nop location to tocsave_htab.
(ppc64_elf_relocate_section): Convert prologue nop to std. Skip
first insn of plt call stub when R_PPC64_TOCSAVE present.
|
|
* ld-scripts/phdrs.exp: Expect to fail for the RX.
* elf32-rx.c: Add support for PID mode.
(rx_elf_relocate_section): Add checks for unsafe PID relocations.
Include addend in R_RX_SYM relocations.
* config/rx-defs.h (rx_pid_register): New.
(rx_gp_register): New.
* config/rx-parse.y (rx_lex): Add support for %gpreg and %pidreg.
(displacement): Add PID support.
* config/tc-rx.c (rx_pid_mode): New.
(rx_num_int_regs): New.
(rx_pid_register): New.
(rx_gp_register): New.
(options): Add -mpid and -mint-register= options.
(md_longopts): Likewise.
(md_parse_option): Likewise.
(md_show_usage): Likewise.
(rx_pid_symbol): New.
(rx_pidreg_symbol): New.
(rx_gpreg_symbol): New.
(md_begin): Support PID.
(rx_validate_fix_sub): Support PID.
(tc_gen_reloc): Support PID.
* doc/c-rx.texi: Document PID support.
* rx.h (E_FLAG_RX_PID): New.
|
|
|
|
|
|
|
|
gcc PR lto/47247
* plugin-api.h (enum ld_plugin_symbol_resolution): Add
LDPR_PREVAILING_DEF_IRONLY_EXP.
(enum ld_plugin_tag): Add LDPT_GET_SYMBOLS_V2.
gold/ChangeLog
gcc PR lto/47247
* plugin.cc (get_symbols_v2): New function.
(Plugin::load): Add LDPT_GET_SYMBOLS_V2.
(is_referenced_from_outside): New function.
(Pluginobj::get_symbol_resolution_info): Add version parameter, return
LDPR_PREVAILING_DEF_IRONLY_EXP when using new version.
(get_symbols): Pass version parameter.
(get_symbols_v2): New function.
* plugin.h (Pluginobj::get_symbol_resolution_info): Add version
parameter.
* testsuite/plugin_test.c (get_symbols_v2): New static variable.
(onload): Add LDPT_GET_SYMBOLS_V2.
(all_symbols_read_hook): Use get_symbols_v2; check for
LDPR_PREVAILING_DEF_IRONLY_EXP.
* testsuite/plugin_test_3.sh: Update expected results.
|
|
|
|
bfd/
* elfxx-sparc.c (_bfd_sparc_elf_merge_private_bfd_data): New.
* elfxx-sparc.h: Declare it.
* elf32-sparc.c (elf32_sparc_merge_private_bfd_data): Call it.
* elf64-sparc.c (elf64_sparc_merge_private_bfd_data): Likewise.
binutils/
* readelf.c (display_sparc_hwcaps): New.
(display_sparc_gnu_attribute): New.
(process_sparc_specific): New.
(process_arch_specific): When EM_SPARC, EM_SPARC32PLUS,
or EM_SPARCV9 invoke process_sparc_specific.
gas/
* config/tc-sparc.c (hwcap_seen): New bitmask, defined when
not TE_SOLARIS.
(sparc_ip): When not TE_SOLARIS, accumulate hwcap bits from
sparc_opcode->flags of instruction into hwcap_seen.
(sparc_md_end): Create Tag_GNU_Sparc_HWCAPS attribute if
hwcap_seen is non-zero and not TE_SOLARIS.
gas/testsuite/
* gas/sparc/hpcvis3.s: Update for fixed fchksum16 mnemonic.
* gas/sparc/hpcvis3.d: Likewise.
include/elf/
* sparc.h (Tag_GNU_Sparc_HWCAPS): New object attribute.
(ELF_SPARC_HWCAP_*): New HWCAPS bitmask values.
include/opcode/
* sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
(F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
opcodes/
* sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
bits. Fix "fchksm16" mnemonic.
|
|
bfd/
2011-09-15 H.J. Lu <hongjiu.lu@intel.com>
PR ld/12975
* bfd-in.h (bfd_elf_size_dynamic_sections): Remove pointer
to struct bfd_elf_version_tree.
* elflink.c (elf_info_failed): Remove verdefs.
(_bfd_elf_export_symbol): Updated.
_bfd_elf_link_assign_sym_version): Likewise.
(bfd_elf_size_dynamic_sections): Remove pointer to struct
bfd_elf_version_tree. Updated.
(bfd_elf_gc_mark_dynamic_ref_symbol): Check if a symbol is hidden
by linker script.
* linker.c (bfd_hide_sym_by_version): New.
* bfd-in2.h: Regenerated.
include/
2011-09-15 H.J. Lu <hongjiu.lu@intel.com>
PR ld/12975
* bfdlink.h (bfd_link_info): Add version_info.
ld/
2011-09-15 H.J. Lu <hongjiu.lu@intel.com>
PR ld/12975
* ldlang.c (lang_elf_version_info): Removed.
(lang_register_vers_node): Replace lang_elf_version_info with
link_info.version_info.
(lang_add_vers_depend): Likewise.
* pe-dll.c (process_def_file_and_drectve): Likewise.
* emultempl/solaris2.em (elf_solaris2_before_allocation): Likewise.
* ldlang.h (lang_elf_version_info): Removed.
* plugin.c (is_visible_from_outside): Check if symbol is hidden
by version script.
* emultempl/elf32.em (gld${EMULATION_NAME}_before_allocation):
Remove lang_elf_version_info.
ld/testsuite/
2011-09-15 H.J. Lu <hongjiu.lu@intel.com>
PR ld/12975
* ld-elf/pr12975.d: New.
* ld-elf/pr12975.s: Likewise.
* ld-elf/pr12975.t: Likewise.
|
|
2011-08-12 H.J. Lu <hongjiu.lu@intel.com>
PR ld/13082
* x86-64.h (R_X86_64_RELATIVE64): New.
|
|
* config/tc-mips.c (mips_set_options): Add ase_mcu.
(mips_opts): Initialise ase_mcu to -1.
(ISA_SUPPORTS_MCU_ASE): New macro.
(MIPS_CPU_ASE_MCU): Likewise.
(is_opcode_valid): Handle MCU.
(macro_build, macro): Likewise.
(validate_mips_insn, validate_micromips_insn): Likewise.
(mips_ip): Likewise.
(options): Add OPTION_MCU and OPTION_NO_MCU.
(md_longopts): Add mmcu and mno-mcu.
(md_parse_option): Handle OPTION_MCU and OPTION_NO_MCU.
(mips_after_parse_args): Handle MCU.
(s_mipsset): Likewise.
(md_show_usage): Handle MCU options.
* doc/as.texinfo: Document -mmcu and -mno-mcu options.
* doc/c-mips.texi: Likewise, and document ".set mcu" and
".set nomcu" directives.
gas/testsuite/
* gas/mips/micromips@mcu.d: New test.
* gas/mips/mcu.d: Likewise.
* gas/mips/mcu.s: New test source.
* gas/mips/mips.exp: Run the new tests.
include/opcode/
* mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
(OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
(INSN_ASE_MASK): Add the MCU bit.
(INSN_MCU): New macro.
(M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
opcodes/
* mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
and "mips64r2".
(print_insn_args, print_insn_micromips): Handle MCU.
* micromips-opc.c (MC): New macro.
(micromips_opcodes): Add "aclr", "aset" and "iret".
* mips-opc.c (MC): New macro.
(mips_builtin_opcodes): Add "aclr", "aset" and "iret".
|
|
* mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
(INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
(INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
(INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
(INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
(INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
(INSN2_READ_GPR_MMN): Likewise.
(INSN2_READ_FPR_D): Change the bit used.
(INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
(INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
(INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
(INSN2_COND_BRANCH): Likewise.
(INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
(INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
(INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
(INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
(INSN2_MOD_GPR_MN): Likewise.
gas/
* config/tc-mips.c (gpr_mod_mask): Remove INSN2_MOD_GPR_MB,
INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG,
INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MM,
INSN2_MOD_GPR_MN, INSN2_MOD_GPR_MP and INSN2_MOD_GPR_MQ opcode
register use checks.
(gpr_read_mask): Add INSN2_READ_GPR_MC, INSN2_READ_GPR_ME
INSN2_READ_GPR_MG, INSN2_READ_GPR_MJ, INSN2_READ_GPR_MMN,
INSN2_READ_GPR_MP and INSN2_READ_GPR_MQ opcode register use
checks.
(gpr_write_mask): Replace INSN2_WRITE_GPR_S opcode register
use flag with INSN_WRITE_GPR_S. Add INSN2_WRITE_GPR_MB,
INSN2_WRITE_GPR_MHI, INSN2_WRITE_GPR_MJ and INSN2_WRITE_GPR_MP
opcode register use checks.
(can_swap_branch_p): Enable microMIPS branch swapping.
(append_insn): Likewise.
gas/testsuite/
* gas/mips/micromips.d: Update according to changes to enable
microMIPS branch swapping.
* gas/mips/micromips-trap.d: Likewise.
* gas/mips/micromips@jal-svr4pic.d: Likewise.
* gas/mips/micromips@loc-swap.d: Likewise.
* gas/mips/micromips@loc-swap-dis.d: Likewise.
opcodes/
* micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
(MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
(MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
(WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
(RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
(RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
(WR_s): Update macro.
(micromips_opcodes): Update register use flags of: "addiu",
"addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
"and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
"jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
"lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
"nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
"swm" and "xor" instructions.
|
|
2011-08-08 Tristan Gingold <gingold@adacore.com>
* mach-o.h (bfd_mach_o_version_min_command): New structure.
(bfd_mach_o_load_command): Add version_min.
(mach_o_data_struct): Fix comment.
* mach-o.c (bfd_mach_o_read_version_min): New function.
(bfd_mach_o_read_command): Handle BFD_MACH_O_LC_FUNCTION_STARTS,
BFD_MACH_O_LC_VERSION_MIN_MACOSX and
BFD_MACH_O_LC_VERSION_MIN_IPHONEOS.
(bfd_mach_o_get_name_or_null): New function.
(bfd_mach_o_get_name): Use the above new one.
(bfd_mach_o_load_command_name): Add the above new commands.
(bfd_mach_o_bfd_print_private_bfd_data): Display numerically
unknown commands. Handle BFD_MACH_O_LC_FUNCTION_STARTS,
BFD_MACH_O_LC_VERSION_MIN_MACOSX and
BFD_MACH_O_LC_VERSION_MIN_IPHONEOS.
include/mach-o/
2011-08-08 Tristan Gingold <gingold@adacore.com>
* loader.h (bfd_mach_o_load_command_type): Add
BFD_MACH_O_LC_LOAD_UPWARD_DYLIB, BFD_MACH_O_LC_VERSION_MIN_MACOSX,
BFD_MACH_O_LC_VERSION_MIN_IPHONEOS, BFD_MACH_O_LC_FUNCTION_STARTS,
and BFD_MACH_O_LC_DYLD_ENVIRONMENT.
* external.h (mach_o_version_min_command_external): New structure.
|
|
2011-08-08 Tristan Gingold <gingold@adacore.com>
* mach-o.h: Move size macros to external.h
Move reloc macros to reloc.h and x86-64.h.
* mach-o-i386.c: Includes mach-o/reloc.h
* mach-o-x86-64.c: Ditto and includes mach-o/x86-64.h
* mach-o.c: Add includes.
(bfd_mach_o_write_header): Use structure from external.h to convert.
(bfd_mach_o_write_thread): Ditto.
(bfd_mach_o_write_relocs): Ditto.
(bfd_mach_o_write_section_32): Ditto.
(bfd_mach_o_write_section_64): Ditto.
(bfd_mach_o_write_segment_32): Ditto.
(bfd_mach_o_write_segment_64): Ditto.
(bfd_mach_o_write_symtab): Ditto.
(bfd_mach_o_write_contents): Ditto.
(bfd_mach_o_read_header): Ditto.
(bfd_mach_o_read_section_32): Ditto.
(bfd_mach_o_read_section_64): Ditto.
(bfd_mach_o_read_symtab_symbol): Ditto.
(bfd_mach_o_read_dylinker): Ditto.
(bfd_mach_o_read_dylib): Ditto.
(bfd_mach_o_read_dysymtab): Ditto.
(bfd_mach_o_read_symtab): Ditto.
(bfd_mach_o_read_linkedit): Ditto.
(bfd_mach_o_read_str): Ditto.
(bfd_mach_o_read_dyld_info): Ditto.
(bfd_mach_o_read_segment): Ditto.
(bfd_mach_o_read_command): Ditto.
(bfd_mach_o_archive_p): Ditto.
(bfd_mach_o_canonicalize_one_reloc): Ditto. Change the BUF parameter.
(bfd_mach_o_canonicalize_relocs): Adjust to call the above function.
(bfd_mach_o_read_dysymtab_symbol): Rename BUF variable.
(bfd_mach_o_read_uuid): Remove useless cast. Use a macro instead
of an hard-coded value.
include/mach-o
2011-08-08 Tristan Gingold <gingold@adacore.com>
* loader.h: Reorder declarations.
* x86-64.h: New file.
* external.h: New file.
* reloc.h: New file.
|
|
* sparc.h: Document new format codes '4', '5', and '('.
(OPF_LOW4, RS3): New macros.
opcodes/
* sparc-dis.c (v9a_ast_reg_names): Add "cps".
(X_RS3): New macro.
(print_insn_sparc): Handle '4', '5', and '(' format codes.
Accept %asr numbers below 28.
* sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
instructions.
gas/
* config/tc-sparc.c (v9a_asr_table): Add "cps".
(sparc_ip): Handle '4', '5' and '(' format codes.
gas/testsuite
* gas/sparc/hpcvis3.d: New test.
* gas/sparc/hpcvis3.s: New test source.
* gas/sparc/sparc.exp: Run new test.
|
|
order of flags documented.
|
|
* elfxx-mips.c: Adjust comments throughout.
(mips_elf_relax_delete_bytes): Reshape code.
(_bfd_mips_elf_relax_section): Remove check for
R_MICROMIPS_GPREL16 relocations. Reshape code.
gas/
* config/tc-mips.c: Adjust comments throughout.
(reglist_lookup): Reshape code.
(jmp_reloc_p, jalr_reloc_p): Reformat.
(got16_reloc_p, hi16_reloc_p, lo16_reloc_p): Handle microMIPS
relocations.
(gpr_mod_mask): Remove unused variable.
(gpr_read_mask, gpr_write_mask): Reshape code.
(fpr_read_mask, fpr_write_mask): Likewise.
(nops_for_vr4130): Ensure non-microMIPS mode.
(can_swap_branch_p): Correct pinfo2 reference. Reshape code.
(append_insn): Skip Loongson 2F workaround in MIPS16 mode. Use
the outermost operator of a compound relocation to determines
the relocated field. Fix formatting.
(md_convert_frag): Reshape code.
include/opcode/
* mips.h: Clarify the description of microMIPS instruction
manipulation macros.
(MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
|
