Age | Commit message (Expand) | Author | Files | Lines |
2024-08-06 | RISC-V: Add support for XCvBitmanip extension in CV32E40P | Mary Bennett | 2 | -2/+44 |
2024-08-06 | RISC-V: Add support for Zcmop extension | Xiao Zeng | 2 | -0/+27 |
2024-08-06 | RISC-V: Add support for Zimop extension | Xiao Zeng | 2 | -0/+123 |
2024-07-31 | libctf, include: add ctf_dict_set_flag: less enum dup checking by default | Nick Alcock | 1 | -2/+14 |
2024-07-31 | include, libctf: improve ECTF_DUPLICATE error message | Nick Alcock | 1 | -1/+1 |
2024-07-31 | libctf: improve ECTF_NOPARENT error message | Nick Alcock | 1 | -1/+1 |
2024-07-26 | microMIPS: Add MT ASE instruction set support | YunQiang Su | 1 | -3/+11 |
2024-07-23 | Improve objdump's display of PE header information. | Pali Roh?r | 2 | -3/+3 |
2024-07-20 | Add markers for 2.43 branch/release | Nick Clifton | 1 | -0/+4 |
2024-07-19 | MIPS/opcodes: Replace "y" microMIPS operand code with "x" | Maciej W. Rozycki | 1 | -2/+2 |
2024-07-19 | MIPS/opcodes: Remove the regular MIPS "+t" operand code | YunQiang Su | 1 | -2/+1 |
2024-07-19 | MIPS/opcodes: Discard unused OP_SH, OP_MASK, and OP_OP macros | Maciej W. Rozycki | 1 | -454/+0 |
2024-07-19 | MIPS/opcodes: Correct documentation for R6 operand types | Maciej W. Rozycki | 1 | -7/+6 |
2024-07-18 | opcodes: aarch64: enforce checks on subclass flags in aarch64-gen.c | Indu Bhagat | 1 | -1/+2 |
2024-07-18 | include: opcodes: aarch64: define new subclasses | Indu Bhagat | 1 | -1/+31 |
2024-07-12 | aarch64: Add support for sme2.1 zero instructions. | Srinath Parvathaneni | 1 | -1/+10 |
2024-07-12 | aarch64: Add support for sme2.1 movaz instructions. | Srinath Parvathaneni | 1 | -0/+1 |
2024-07-12 | aarch64: Add support for sme2.1 luti2 and luti4 instructions. | Srinath Parvathaneni | 1 | -0/+1 |
2024-07-09 | include: sframe: update code comments around SFrame FRE stack offsets | Indu Bhagat | 1 | -10/+12 |
2024-07-09 | LTO: Properly check wrapper symbol | H.J. Lu | 1 | -0/+3 |
2024-07-08 | aarch64: Add support for sve2p1 pmov instruction. | srinath | 1 | -0/+8 |
2024-07-05 | aarch64: add STEP2 feature and its associated registers | Matthieu Longo | 1 | -0/+3 |
2024-07-05 | aarch64: add SPMU2 feature and its associated registers | Matthieu Longo | 1 | -0/+3 |
2024-07-05 | aarch64: add E3DSE feature and its associated registers | Matthieu Longo | 1 | -1/+5 |
2024-06-28 | aarch64: Add support for Armv9.5-A architecture | Claudio Bantaloukas | 1 | -0/+8 |
2024-06-28 | RISC-V: Add Zabha extension CAS instructions. | Jiawei | 2 | -0/+7 |
2024-06-25 | aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands. | Srinath Parvathaneni | 1 | -3/+1 |
2024-06-25 | aarch64: Fix sve2p1 extq instruction operands. | Srinath Parvathaneni | 1 | -1/+1 |
2024-06-25 | aarch64: Fix sve2p1 dupq instruction operands. | Srinath Parvathaneni | 1 | -1/+1 |
2024-06-25 | aarch64: Enable mandatory feature bits for v9.4-A. | Srinath Parvathaneni | 1 | -1/+2 |
2024-06-25 | gdb: LoongArch: Add support for hardware breakpoint | Hui Li | 1 | -0/+2 |
2024-06-25 | gdb: LoongArch: Add support for hardware watchpoint | Hui Li | 1 | -0/+2 |
2024-06-24 | aarch64: Add SME FP8 multiplication instructions | Andrew Carlotti | 1 | -0/+11 |
2024-06-24 | aarch64: Add FP8 Neon and SVE multiplication instructions | Andrew Carlotti | 1 | -6/+31 |
2024-06-24 | gas, aarch64: Add SME2 lutv2 extension | saurabh.jha@arm.com | 1 | -0/+6 |
2024-06-23 | aarch64: Enable +cssc for armv8.9-a | Andrew Carlotti | 1 | -0/+1 |
2024-06-18 | libctf, include: new functions for looking up enumerators | Nick Alcock | 1 | -0/+38 |
2024-06-18 | include: libctf: comment improvements | Nick Alcock | 1 | -2/+5 |
2024-06-18 | libctf: prohibit addition of enums with overlapping enumerator constants | Nick Alcock | 1 | -6/+7 |
2024-06-18 | include: fix libctf ECTF_NOENUMNAM error message | Nick Alcock | 1 | -1/+1 |
2024-06-18 | RISC-V: Add SiFive cease extension v1.0 | Hau Hsu | 2 | -0/+4 |
2024-06-18 | RISC-V: Support Zacas extension. | Gianluca Guida | 2 | -0/+12 |
2024-06-13 | Add --rosegment option to BFD linker to stop the '-z separate-code' from gene... | Nick Clifton | 1 | -0/+3 |
2024-06-13 | MIPS/opcodes: Rework INSN_* flags into a consistent block | Maciej W. Rozycki | 1 | -28/+25 |
2024-06-13 | MIPS/opcodes: Update INSN_CHIP_MASK for INSN_ALLEGREX | Maciej W. Rozycki | 1 | -1/+1 |
2024-06-12 | aarch64: add Branch Record Buffer extension instructions | Claudio Bantaloukas | 1 | -1/+6 |
2024-06-12 | RISC-V: Support S[sm]csrind extension csrs. | Jiawei | 1 | -6/+40 |
2024-06-06 | RISC-V: Add support for Zvfbfwma extension | Xiao Zeng | 2 | -0/+9 |
2024-06-06 | RISC-V: Add support for Zvfbfmin extension | Xiao Zeng | 2 | -0/+9 |
2024-06-06 | RISC-V: Add support for Zfbfmin extension | Xiao Zeng | 2 | -0/+9 |