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2015-12-11[AArch64][Patch 5/5] Add instruction PSB CSYNCMatthew Wahab2-0/+14
The Statistical Profile Extension adds the instruction PSB CSYNC as an alias for the HINT #17 instruction. This patch adds the instruction to binutils as a HINT alias that takes an operand. A new operand type, AARCH64_OPND_BARRIER_PSB, is added to represent the operand to PSB. A parser for the operand type is added to the assembler and a printer to the disassembler. The operand name "csync" is added to the list of HINT options with HINT number #17. Encoding and decoding of the operand is handled by the ins_hint/ext_hint functions added in the preceding patches. gas/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_hint_opt_hsh): New. (parse_barrier_psb): New. (parse_operands): Add case for AARCH64_OPND_BARRIER_PSB. (md_begin): Set up aarch64_hint_opt_hsh. gas/testsuite/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/system-2.d: Enable the statistical profiling extension. Update the expected output. * gas/aarch64/system-2.s: Add tests for PSB CSYNC. * gas/aarch64/system.d: Update the expected output. include/opcode/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-opc.c (aarch64_hint_options): Add "csync". (aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB. * aarch64-tbl.h (aarch64_feature_stat_profile): New. (STAT_PROFILE): New. (aarch64_opcode_table): Add "psb". (AARCH64_OPERANDS): Add "BARRIER_PSB". Change-Id: I5ffb672d26a8b15b48785478d359350a9b70ca09
2015-12-11[AArch64][Patch 4/5] Support HINT aliases taking operands.Matthew Wahab2-0/+7
The Statistical Profile Extension adds the instruction PSB CSYNC as an alias for the HINT #17 instruction. This patch adds support for aliases of HINT which take an operand, adding a table to store operand names and their matching hint number as well as encoding and decoding functions for such operands. Parsing and printing the operands are deferred to any support added for aliases with such operands. include/opcode/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_hint_options): Declare. (aarch64_opnd_info): Add field hint_option. opcodes/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm.c (aarch64_ins_hint): New. * aarch64-asm.h (aarch64_ins_hint): Declare. * aarch64-dis.c (aarch64_ext_hint): New. * aarch64-dis.h (aarch64_ext_hint): Declare. * aarch64-opc-2.c: Regenerate. * aarch64-opc.c (aarch64_hint_options): New. * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos. Change-Id: I2205038fc1c47d3025d1f0bc2fbf405b5575b287
2015-12-11[AArch64][Patch 1/5] Support the ARMv8.2 Statistical Profiling Extension.Matthew Wahab2-0/+5
The Statistical Profile extension included in the ARMv8.2 architecture adds a number of system registers and a new instruction. This patch set adds support for the extension to binutils, enabled when -march=armv8.2-a+profile is given. The patches in this series: - Add the new command line option and feature flags. - Add the new system registers. - Adjust the maximum number of aliases permitted for an instruction. - Add support for HINT aliases which take operands. - Add the new instruction, an alias of the HINT instruction. This patch adds the option "profile" to the permitted architecture extensions, disabling it by default. gas/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_features): Add "profile". * doc/c-aarch64.texi (AArch64 Extensions): Add "profile". include/opcode/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_PROFILE): New. Change-Id: If9bb4a9b69a264180f96f8ffaf10b15ced273699
2015-12-10[AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.Matthew Wahab2-0/+7
ARMv8.2 adds the new system instruction DC CVAP. This patch adds support for the instruction to binutils, enabled when -march=armv8.2-a is selected. gas/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (parse_sys_ins_reg): Add check of architectural support for system register. gas/testsuite/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/sysreg-2.d: Add tests for dc instruction. * gas/aarch64/sysreg-2.s: Add uses of dc instruction. include/opcode/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap". (aarch64_sys_ins_reg_supported_p): New. Change-Id: I3158b97d9bbee9644c2d0e2986db807412ef1053
2015-12-10[AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction.Matthew Wahab2-1/+8
ARMv8.2 adds the new system instruction DC CVAP. This patch series adds support for this instruction to binutils, enabled when -march=armv8.2-a is selected. The AArch64 binutils record of some system registers uses a boolean value to hold the single flag currently supported for them. To allow these registers to be limited to specific architectures, the first patch in this series replaces the boolean flag with a bitset and feature test. include/opcode/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags. (aarch64_sys_ins_reg_has_xt): Declare. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt with aarch64_sys_ins_reg_has_xt. (aarch64_ext_sysins_op): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): Likewise. (F_HASXT): New. (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg. (aarch64_sys_regs_dc): Likewise. (aarch64_sys_regs_at): Likewise. (aarch64_sys_regs_tlbi): Likewise. (aarch64_sys_ins_reg_has_xt): New. Change-Id: I363637a6c3f54d7ffff953b3a0734e8139cae819
2015-12-10[AArch64][PATCH 1/2] Add support for RAS instruction ESB.Matthew Wahab2-0/+7
The ARMv8.2 RAS extension adds a new barrier instruction ESB as an alias and the preferred form of HINT 16. This patch adds an architectural feature flag for the RAS extension and includes it in the features selected enabled by -march=armv8.2-a. It also adds the ESB instruction, making it available whenever the RAS feature is enabled. Because ESB is the preferred form and because the target architecture isn't available to the disassembler, HINT 16 will be disassembled as ESB even when the target has no support for the RAS extension. gas/testsuite/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/system-2.d: New. * gas/aarch64/system-2.s: New. * gas/aarch64/system.d: Adjust expected output for HINT 16. include/opcode/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_RAS): New. (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-tbl.h (aarch64_feature_ras): New. (RAS): New. (aarch64_opcode_table): Add "esb". Change-Id: Id4713917da15cca3b977284f43febd1c9b3d9faf
2015-12-10[AArch64] Fix ARMv8.1 and ARMv8.2 feature settings.Matthew Wahab2-2/+13
ARMv8.1 includes CRC as a required extension but this isn't reflected in the features enabled by -march=armv8.1-a. The FP16 feature modifier also clashes with AARCH64_FEATURE_V8_1 and the list of features for ARMv8.2 is missing ARMv8.1 features. This patch enables +crc for -march values of armv8.1-a and later. It also fixes the values for AARCH64_FEATURE_F16 and makes AARCH64_ARCH_V8_2 and superset of AARCH64_ARCH_V8_2. gas/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * doc/c-aarch64.texi (AArch64 Extensions): Update entry for crc. include/opcode 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_F16): Fix clash with AARCH64_FEATURE_V8_1. (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC. (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and AARCH64_FEATURE_V8_1. Change-Id: I8af5369f6df2430b28f6cec92870d2a4d14a7431
2015-12-07R_PPC64_ENTRYAlan Modra2-0/+5
Add a new relocation that marks large-model entry code, for edit back to medium-model. include/elf/ * ppc64.h (R_PPC64_ENTRY): Define. bfd/ * reloc.c (BFD_RELOC_PPC64_ENTRY): New. * elf64-ppc.c (reloc_howto_type ppc64_elf_howto_raw): Add entry for R_PPC64_ENTRY. (LD_R2_0R12, ADD_R2_R2_R12, LIS_R2, ADDIS_R2_R12): Define. (ppc64_elf_reloc_type_lookup): Handle R_PPC64_ENTRY. (ppc64_elf_relocate_section): Edit code at R_PPC64_ENTTY. Use new insn defines. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate.
2015-12-04Fix failures in the GAS testsuite for the ARC architecture.Claudiu Zissulescu2-1/+5
gas * config/tc-arc.c (arc_option): Sets all internal gas options when parsing .cpu directive. (declare_register_set): Declare all 64 registers. (md_section_align): Refactor. (md_pcrel_from_section): Remove assert. (pseudo_operand_match): Fix pseudo operand match. (find_reloc): Use flags filed, extend matching. * config/tc-arc.h (TC_VALIDATE_FIX): Don't fixup any PLT relocation. testsuite * gas/arc/bic.d: Update test. * gas/arc/add_s-err.s: New file. * gas/arc/cpu-warn1.s: Likewise. * gas/arc/pcl-relocs.d: Likewise. * gas/arc/pcl-relocs.s: Likewise. * gas/arc/pcrel-relocs.d: Likewise. * gas/arc/pcrel-relocs.s: Likewise. * gas/arc/pic-relocs.d: Likewise. * gas/arc/pic-relocs.s: Likewise. * gas/arc/plt-relocs.d: Likewise. * gas/arc/plt-relocs.s: Likewise. * gas/arc/pseudos.d: Likewise. * gas/arc/pseudos.s: Likewise. * gas/arc/sda-relocs.d: Likewise. * gas/arc/sda-relocs.s: Likewise. * gas/arc/sda-relocs2.d: Likewise. * gas/arc/sda-relocs2.s: Likewise. * gas/arc/tls-relocs.d: Likewise. * gas/arc/tls-relocs.s: Likewise. opcode * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32]. opcodes * arc-dis.c (special_flag_p): Match full mnemonic. * arc-opc.c (print_insn_arc): Check section size to read appropriate number of bytes. Fix printing. * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without arguments.
2015-12-03Darwin: add new mach-o header flags.Tristan Gingold2-1/+7
binutils/ * od-macho.c (bfd_mach_o_header_flags_name): Add name for flags until BFD_MACH_O_MH_APP_EXTENSION_SAFE. include/mach-o/ * loader.h (bfd_mach_o_header_flags): Add BFD_MACH_O_MH_APP_EXTENSION_SAFE.
2015-12-01Invoke aout N_* macros with pointer to struct internal_execAlan Modra11-53/+70
No functional changes here. BTW, some of these headers don't seem to be used anywhere: include/aout/dynix3.h, include/aout/encap.h, include/aout/hp.h, gas/config/aout_gnu.h bfd/ * aout-adobe.c: Invoke aout N_* macros with pointer to struct internal_exec. * aout-arm.c: Likewise. * aout-cris.c: Likewise. * aout-target.h: Likewise. * aout-tic30.c: Likewise. * aoutf1.h: Likewise. * aoutx.h: Likewise. * bout.c: Likewise. * freebsd.h: Likewise. * gen-aout.c: Likewise. * hp300hpux.c: Likewise. * i386aout.c: Likewise. * i386linux.c: Likewise. * i386lynx.c: Likewise. * i386mach3.c: Likewise. * i386os9k.c: Likewise. * libaout.h: Likewise. * m68klinux.c: Likewise. * m88kmach3.c: Likewise. * mipsbsd.c: Likewise. * netbsd.h: Likewise. * pc532-mach.c: Likewise. * pdp11.c: Likewise. * riscix.c: Likewise. * sparclinux.c: Likewise. * sparclynx.c: Likewise. gas/ * config/aout_gnu.h: Invoke aout N_* macros with pointer to struct internal_exec. include/ * bout.h: Invoke aout N_* macros with pointer to struct internal_exec. * os9k.h: Likewise. include/aout/ * adobe.h: Invoke aout N_* macros with pointer to struct internal_exec. * aout64.h: Likewise. * dynix3.h: Likewise. * encap.h: Likewise. * hp.h: Likewise. * hp300hpux.h: Likewise. * sun4.h: Likewise.
2015-11-28Port libvtv to SolarisRainer Orth2-0/+9
libstdc++-v3: * acinclude.m4 (GLIBCXX_ENABLE_VTABLE_VERIFY) <solaris2*>: Use -Wl,-R in VTV_CXXLINKFLAGS. * configure: Regenerate. * testsuite/18_support/bad_exception/23591_thread-1.c: Use -fvtable-verify=none on Solaris 12+. libgcc: * Makefile.in (VTV_CFLAGS): New variable. (vtv_start$(objext), vtv_end$(objext), vtv_end$(objext)) (vtv_start_preinit$(objext), vtv_end_preinit$(objext)): Use it. * config.host (*-*-solaris2*): Add t-crtstuff-pic to tmake_file. Add vtv_start.o, vtv_end.o, vtv_start_preinit.o, vtv_end_preinit.o to extra_parts if $enable_vtable_verify = yes. libvtv: * configure.tgt (*-*-solaris2.[1-9]*): Declare supported. * configure.ac: Call AC_USE_SYSTEM_EXTENSIONS. <*-*-solaris2*>: Check for init priority support. Check for getexecname, __fortify_fail, _obstack_begin. (VTV_NO_OBSTACK): New conditional. * configure: Regenerate. * Makefile.am [VTV_NO_OBSTACK] (obstack.c): Use new condition. Create empty config.h * Makefile.in: Regenerate. * vtv_rts.cc [HAVE_GETEXECNAME] (program_invocation_name): New variable. (read_section_offset_and_length) [HAVE_GETEXECNAME]: Set it. (dl_iterate_phdr_callback) [HAVE_GETEXECNAME]: Set it. (__fortify_fail): Wrap in HAVE___FORTIFY_FAIL [!HAVE___FORTIFY_FAIL]: Provide non-Cygwin implementation. (read_section_offset_and_length): Assert sh_size >= VTV_PAGE_SIZE. (iterate_modules): Fix typo. Use VTV_PAGE_SIZE. (dl_iterate_phdr_callback): Fix typo. Use VTV_PAGE_SIZE. (__VLTChangePermission): Fix typos. include: * vtv-change-permission.h (VTV_PAGE_SIZE) [__sun__ && __svr4__ && __sparc__]: Define. gcc: * config/sol2.h (SUPPORTS_INIT_PRIORITY): Move up. (STARTFILE_VTV_SPEC, ENDFILE_VTV_SPEC): Define. (STARTFILE_SPEC): Use %(startfile_vtv). (ENDFILE_SPEC): Use %(endfile_vtv). (SUBTARGET_EXTRA_SPECS): Handle STARTFILE_VTV_SPEC, ENDFILE_VTV_SPEC. * gcc.c (LINK_COMMAND_SPEC): Move VTABLE_VERIFICATION_SPEC after %{L*}. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230865 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-28SH FDPIC backend supportRich Felker2-0/+36
gcc/ChangeLog * config.gcc: Handle --enable-fdpic. * config/sh/constraints.md (Ccl): New constraint. * config/sh/linux.h (SUBTARGET_LINK_EMUL_SUFFIX): Handle -mfdpic. * config/sh/sh-c.c (sh_cpu_cpp_builtins): Add __FDPIC__ and __SH_FDPIC__. * config/sh/sh-mem.cc (expand_block_move): Support FDPIC for calls to library functions. * config/sh/sh-protos.h (function_symbol_result): New struct. (function_symbol): Return function_symbol_result. (sh_get_fdpic_reg_initial_val, sh_load_function_descriptor): New declarations. * config/sh/sh.c (TARGET_ASM_INTEGER, sh_assemble_integer): Implement target hook. (TARGET_CANNOT_FORCE_CONST_MEM, sh_cannot_force_const_mem_p): Likewise. (sh_option_override): Force -fPIC if FDPIC is in effect. (sh_asm_output_addr_const_extra): Add UNSPEC_GOTFUNCDESC and UNSPEC_GOTOFFFUNCDESC cases. (prepare_move_operands): Use FDPIC initial GOT register for TLS-related GOT access; inhibit cross-section address offset constants for FDPIC. (sh_assemble_integer): New function. (sh_cannot_copy_insn_p): Inhibit copying insns that are FDPIC PC-relative call sites. (expand_ashiftrt): Adapt invocation of function_symbol. (sh_expand_prologue): Inhibit PC-relative GOT address load for FDPIC. (nonpic_symbol_mentioned_p): Add cases for UNSPEC_GOTFUNCDESC and UNSPEC_GOTOFFFUNCDESC. (legitimize_pic_address): Resolve function symbols to function descriptors for FDPIC. Do not use GOT-relative addressing for local data that may be read-only on FDPIC. (sh_emit_storesi, sh_emit_storehi): New functions. (sh_trampoline_init): Generate FDPIC trampolines. (sh_function_ok_for_sibcall): Add TARGET_FDPIC check. (sh_expand_sym_label2reg): Don't assume sibcalls are local. (sh_output_mi_thunk): Generate FDPIC call. (function_symbol): Return function_symbol_result. For SFUNC_STATIC on FDPIC, generate call site labels to use PC-relative addressing rather than GOT-relative addressing. (sh_conditional_register_usage): Make PIC register fixed and call used when FDPIC is in effect. (sh_legitimate_constant_p): Impose FDPIC constant constraints. (sh_cannot_force_const_mem_p, sh_load_function_descriptor) (sh_get_fdpic_reg_initial_val): New functions. * config/sh/sh.h (SUBTARGET_ASM_SPEC, SUBTARGET_LINK_EMUL_SUFFIX): Handle -mfdpic. (FDPIC_SELF_SPECS, SUBTARGET_DRIVER_SELF_SPECS) (PIC_OFFSET_TABLE_REG_CALL_CLOBBERED) (SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P): New macros. (DRIVER_SELF_SPECS): Add SUBTARGET_DRIVER_SELF_SPECS and FDPIC_SELF_SPECS. (TRAMPOLINE_SIZE): Select trampoline size for FDPIC. (ASM_PREFERRED_EH_DATA_FORMAT): Add EH format constraints for FDPIC. (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): Handle FDPIC case. * config/sh/sh.md (UNSPEC_GOTFUNCDESC, UNSPEC_GOTOFFFUNCDESC): New constants. (calli_fdpic, call_valuei_fdpic, sibcalli_fdpic) (sibcalli_pcrel_fdpic, sibcall_pcrel_fdpic, sibcall_valuei_fdpic) (sibcall_valuei_pcrel_fdpic, sibcall_value_pcrel_fdpic) (sym2GOTFUNCDESC, symGOTFUNCDESC2reg, sym2GOTOFFFUNCDESC) (symGOTOFFFUNCDESC2reg): New patterns. (udivsi3_i1, udivsi3_i4, udivsi3_i4_single, udivsi3, *divsi_inv_call_combine, divsi3_i4, divsi3_i4_single, divsi3) (ashlsi3, ashlsi3_d_call, ashrsi3_n, lshrsi3, lshrsi3_d_call) (calli, call_valuei, call, call_value, sibcalli, sibcalli_pcrel) (sibcall_pcrel, sibcall, sibcall_valuei, sibcall_valuei_pcrel) (sibcall_value_pcrel, sibcall_value, GOTaddr2picreg, symGOT_load) (symGOTOFF2reg, block_move_real, block_lump_real) (block_move_real_i4, block_lump_real_i4): Add support for FDPIC calls. (mulsi3, ic_invalidate_line, initialize_trampoline, call_pop, call_value_pop): Adjust for new function_symbol signature. * config/sh/sh.opt (-mfdpic): New option. * doc/install.texi (Options specification): Document --enable-fdpic. * doc/invoke.texi (SH Options): Document -mfdpic. include/ChangeLog: * longlong.h (udiv_qrnnd): Add FDPIC compatible version for SH. libitm/ChangeLog: * config/sh/sjlj.S (_ITM_beginTransaction): Bypass PLT calling GTM_begin_transaction for compatibility with FDPIC. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@229438 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-28PR other/61321 - demangler crash on casts in template parametersPedro Alves1-0/+4
The fix for bug 59195: [C++ demangler handles conversion operator incorrectly] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=59195 unfortunately makes the demangler crash due to infinite recursion, in case of casts in template parameters. For example, with: template<int> struct A {}; template <typename Y> void function_temp(A<sizeof ((Y)(999))>) {} template void function_temp<int>(A<sizeof (int)>); The 'function_temp<int>' instantiation above mangles to: _Z13function_tempIiEv1AIXszcvT_Li999EEE The demangler parses this as: typed name template name 'function_temp' template argument list builtin type int function type builtin type void argument list template (*) name 'A' template argument list unary operator operator sizeof unary operator cast template parameter 0 (**) literal builtin type int name '999' And after the fix for 59195, due to: static void d_print_cast (struct d_print_info *dpi, int options, const struct demangle_component *dc) { ... /* For a cast operator, we need the template parameters from the enclosing template in scope for processing the type. */ if (dpi->current_template != NULL) { dpt.next = dpi->templates; dpi->templates = &dpt; dpt.template_decl = dpi->current_template; } when printing the template argument list of A (what should be "<sizeof (int)>"), the template parameter 0 (that is, "T_", the '**' above) now refers to the first parameter of the the template argument list of the 'A' template (the '*' above), exactly what we were already trying to print. This leads to infinite recursion, and stack exaustion. The template parameter 0 should actually refer to the first parameter of the 'function_temp' template. Where it reads "for the cast operator" in the comment in d_print_cast (above), it's really talking about a conversion operator, like: struct A { template <typename U> explicit operator U(); }; We don't want to inject the template parameters from the enclosing template in scope when processing a cast _expression_, only when handling a conversion operator. The problem is that DEMANGLE_COMPONENT_CAST is currently ambiguous, and means _both_ 'conversion operator' and 'cast expression'. Fix this by adding a new DEMANGLE_COMPONENT_CONVERSION component type, which does what DEMANGLE_COMPONENT_CAST does today, and making DEMANGLE_COMPONENT_CAST just simply print its component subtree. I think we could instead reuse DEMANGLE_COMPONENT_CAST and in d_print_comp_inner still do: @@ -5001,9 +5013,9 @@ d_print_comp_inner (struct d_print_info *dpi, int options, d_print_comp (dpi, options, dc->u.s_extended_operator.name); return; case DEMANGLE_COMPONENT_CAST: d_append_string (dpi, "operator "); - d_print_cast (dpi, options, dc); + d_print_conversion (dpi, options, dc); return; leaving the unary cast case below calling d_print_cast, but seems to me that spliting the component types makes it easier to reason about the code. g++'s testsuite actually generates three symbols that crash the demangler in the same way. I've added those as tests in the demangler testsuite as well. And then this fixes PR other/61233 too, which happens to be a demangler crash originally reported to GDB, at: https://sourceware.org/bugzilla/show_bug.cgi?id=16957 Bootstrapped and regtested on x86_64 Fedora 20. Also ran this through GDB's testsuite. GDB will require a small update to use DEMANGLE_COMPONENT_CONVERSION in one place it's using DEMANGLE_COMPONENT_CAST in its sources. libiberty/ 2015-11-27 Pedro Alves <palves@redhat.com> PR other/61321 PR other/61233 * demangle.h (enum demangle_component_type) <DEMANGLE_COMPONENT_CONVERSION>: New value. * cp-demangle.c (d_demangle_callback, d_make_comp): Handle DEMANGLE_COMPONENT_CONVERSION. (is_ctor_dtor_or_conversion): Handle DEMANGLE_COMPONENT_CONVERSION instead of DEMANGLE_COMPONENT_CAST. (d_operator_name): Return a DEMANGLE_COMPONENT_CONVERSION component if handling a conversion. (d_count_templates_scopes, d_print_comp_inner): Handle DEMANGLE_COMPONENT_CONVERSION. (d_print_comp_inner): Handle DEMANGLE_COMPONENT_CONVERSION instead of DEMANGLE_COMPONENT_CAST. (d_print_cast): Rename as ... (d_print_conversion): ... this. Adjust comments. (d_print_cast): Rewrite - simply print the left subcomponent. * cp-demint.c (cplus_demangle_fill_component): Handle DEMANGLE_COMPONENT_CONVERSION. * testsuite/demangle-expected: Add tests. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@231020 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-28Fix PR63758 by using the _NSGetEnviron() API on DarwinIain Sandoe2-0/+38
include/ Roland McGrath <roland@gnu.org> PR other/63758 * environ.h: New file. libiberty/ Roland McGrath <roland@gnu.org> Iain Sandoe <iain@codesourcery.com> PR other/63758 * pex-unix.c: Obtain the environment interface from settings in environ.h rather than in-line code. Update copyright date. * setenv.c: Likewise. * xmalloc.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228942 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-28Implement N4514, C++ Extensions for Transactional Memory.Jason Merrill1-0/+2
gcc/ * builtins.def (BUILT_IN_ABORT): Add transaction_pure attribute. gcc/c-family/ * c-common.c (c_common_reswords): Add C++ TM TS keywords. (c_common_attribute_table): Add transaction_safe_dynamic. transaction_safe now affects type identity. (handle_tm_attribute): Handle transaction_safe_dynamic. * c-common.h (enum rid): Add RID_ATOMIC_NOEXCEPT, RID_ATOMIC_CANCEL, RID_SYNCHRONIZED. (OBJC_IS_CXX_KEYWORD): Add RID_SYNCHRONIZED. (D_TRANSMEM): New. * c-cppbuiltin.c (c_cpp_builtins): Define __cpp_transactional_memory. * c-pretty-print.c (pp_c_attributes_display): Don't print transaction_safe in C++. gcc/c/ * c-parser.c (c_lex_one_token): Handle @synchronized. * c-decl.c (match_builtin_function_types): A declaration of a built-in can change whether the function is transaction_safe. gcc/cp/ * cp-tree.h (struct cp_declarator): Add tx_qualifier field. (BCS_NORMAL, BCS_TRANSACTION): New enumerators. * lex.c (init_reswords): Limit TM kewords to -fgnu-tm. * parser.c (cp_lexer_get_preprocessor_token): Fix @synchronized. (make_call_declarator): Take tx_qualifier. (cp_parser_tx_qualifier_opt): New. (cp_parser_lambda_declarator_opt): Use it. (cp_parser_direct_declarator): Likewise. (cp_parser_statement): Handle atomic_noexcept, atomic_cancel. (cp_parser_compound_statement): Change in_try parameter to bcs_flags. (cp_parser_std_attribute): Map optimize_for_synchronized to transaction_callable. (cp_parser_transaction): Take the token. Handle atomic_noexcept. * lambda.c (maybe_add_lambda_conv_op): Handle transaction-safety. * call.c (enum conversion_kind): Add ck_tsafe. (standard_conversion): Handle transaction-safety conversion. (convert_like_real, resolve_address_of_overloaded_function): Likewise. (check_methods): Diagnose transaction_safe_dynamic on non-virtual function. (look_for_tm_attr_overrides): Don't inherit transaction_safe_dynamic. * cvt.c (tx_safe_fn_type_p, tx_unsafe_fn_variant) (can_convert_tx_safety): New. * typeck.c (composite_pointer_type): Handle transaction-safety. * name-lookup.h (enum scope_kind): Add sk_transaction. * name-lookup.c (begin_scope): Handle it. * semantics.c (begin_compound_stmt): Pass it. * decl.c (check_previous_goto_1): Check it. (struct named_label_entry): Add in_transaction_scope. (poplevel_named_label_1): Set it. (check_goto): Check it. (duplicate_decls): A specialization can be transaction_safe independently of its template. (grokdeclarator): Handle tx-qualifier. * rtti.c (ptr_initializer): Handle transaction-safe. * search.c (check_final_overrider): Check transaction_safe_dynamic. Don't check transaction_safe. * mangle.c (write_function_type): Mangle transaction_safe here. (write_CV_qualifiers_for_type): Not here. (write_type): Preserve transaction_safe when stripping attributes. * error.c (dump_type_suffix): Print transaction_safe. libiberty/ * cp-demangle.c (d_cv_qualifiers): Dx means transaction_safe. (cplus_demangle_type): Let d_cv_qualifiers handle it. (d_dump, d_make_comp, has_return_type, d_encoding) (d_count_templates_scopes, d_print_comp_inner) (d_print_mod_list, d_print_mod, d_print_function_type) (is_ctor_or_dtor): Handle DEMANGLE_COMPONENT_TRANSACTION_SAFE. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228462 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-27[AArch64] Add ARMv8.2 instructions BFC and REV64.Matthew Wahab2-0/+5
ARMv8.2 adds two new instructions: BFC as an alias for BFM and REV64 as an alias for REV. This patch set adds support for these to binutils, enabled when the -march=armv8.2-a is given. It depends on the support for an instruction being its preferred form which was added in an earlier patch. This patch adds the alias BFC <Rd>, #<imm>, #<width> as the preferred form for BFM when the source is a zero register and the conditions for using the BFI form are met (in other words, BFC is the preferred form for BFI <Rd>, <Rs>, #<imm>, #<width> when the <Rs> is a zero register). gas/testsuite/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/alias-2.d: New. * gas/aarch64/alias-2.s: New. include/opcode/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_op): Add OP_BFC. opcodes/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-asm.c (convert_bfc_to_bfm): New. (convert_to_real): Add case for OP_BFC. * aarch64-dis-2.c: Regenerate. * aarch64-dis.c: (convert_bfm_to_bfc): New. (convert_to_alias): Add case for OP_BFC. * aarch64-opc-2.c: Regenerate. * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert to allow width operand in three-operand instructions. * aarch64-tbl.h (QL_BF1): New. (aarch64_feature_v8_2): New. (ARMV8_2): New. (aarch64_opcode_table): Add "bfc". Change-Id: I6efe318b2538ba11f0caece7c6d70957441c872b
2015-11-27[AArch64] Add feature flags and command line for ARMv8.2 FP16 support.Matthew Wahab2-0/+8
ARMv8.2 adds optional support for 16-bit operations to the FP and Adv.SIMD instructions. This patch adds a feature macro for this support with a new command line option "+fp16" to enable/disable it. Although the command line option is added as an architecture extension, it only affects instructions available with when +fp or +simd is enabled. If +fp16 is specified then it will also enable +fp. There are currently no FP16 instructions implemented in binutils, this patch is to enable subsequent work on supporting the extension. gas/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_features): Add "fp16". * doc/c-aarch64.texi (Architecture Extensions): Add "fp16". include/opcode/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_F16): New. (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2 features. Change-Id: Id2021e0513946e16d0935c2a5b9605574cdff95a
2015-11-24Add an AArch64 simulator to GDB.Nick Clifton2-0/+52
sim * configure.tgt: Add aarch64 entry. * configure: Regenerate. * sim/aarch64/configure.ac: New configure template. * sim/aarch64/aclocal.m4: Generate. * sim/aarch64/config.in: Generate. * sim/aarch64/configure: Generate. * sim/aarch64/cpustate.c: New file - functions for accessing AArch64 registers. * sim/aarch64/cpustate.h: New header. * sim/aarch64/decode.h: New header. * sim/aarch64/interp.c: New file - interface between GDB and simulator. * sim/aarch64/Makefile.in: New makefile template. * sim/aarch64/memory.c: New file - functions for simulating aarch64 memory accesses. * sim/aarch64/memory.h: New header. * sim/aarch64/sim-main.h: New header. * sim/aarch64/simulator.c: New file - aarch64 simulator functions. * sim/aarch64/simulator.h: New header. include/gdb * sim-aarch64.h: New file. sim/test * configure: Regenerate. * sim/aarch64: New directory.
2015-11-20[AArch64] Add support for ARMv8.1 Virtulization Host Extensions.Matthew Wahab2-0/+7
The ARMv8.1 architecture includes the Virtualization Host Extensions which add a number of system registers. This patch adds support for these system registers, making them available when -march=armv8.1-a is selected. include/opcode/ 2015-11-20 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_V8_1): New. (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1. opcodes/ 2015-11-20 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12, sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12, tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12, amair_el12, vbar_el12, contextidr_el2, contextidr_el12, cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02, cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2, cnthv_ctl_el2, cnthv_cval_el2. (aarch64_sys_reg_supported_p): Update for the new system registers. gas/testsuite/ 2015-11-20 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/virthostext-directive.d: New. * gas/aarch64/virthostext.d: New. * gas/aarch64/virthostext.s: New. Change-Id: Iecb370591b1b6e9e00d81c8ccd9ae3b0f71794a2
2015-11-19[ARM] Add ARMv8.2 architecture feature and command line option.Matthew Wahab2-0/+8
ARMv8.2 is an architectural extension of ARMv8. This patch adds an architecture feature macro for ARMv8.2 to the binutils ARM target with GAS command line option -march=armv8.2-a. gas/ 2015-11-19 Matthew Wahab <matthew.wahab@arm.com> * config/tc-arm.c (arm_archs): Add "armv8.2-a". * doc/c-arm.texi (-march): Add "armv8.2-a". include/opcode/ 2015-11-19 Matthew Wahab <matthew.wahab@arm.com> * arm.h (ARM_EXT2_V8_2A): New. (ARM_ARCH_V8_2A): New. Change-Id: I9e0f50e3c6cea24e6b87b8b862fd4e1cdcc1052e
2015-11-19[AArch64] Add ARMv8.2 command line option and feature flag.Matthew Wahab2-1/+14
ARMv8.2 is an architectural extension of ARMv8. This patch adds an architecture feature macro for ARMv8.2 to the binutils AArch64 target with GAS command line option -march=armv8.2-a. gas/ 2015-11-19 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_archs): Add "armv8.2-a". * doc/c-aarch64.texi (-march): Likewise. include/opcode/ 2015-11-19 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_V8_2): New. (AARCH64_ARCH_V8_2): New. Change-Id: I129232ab00234a07d18ce4b619607344acb3cbaf
2015-11-17Mach-O: add new defines and struct for darwin 14.5Tristan Gingold5-2/+158
include/mach-o/ * arm64.h: New file. * unwind.h: Add arm64 encodings. * loader.h (bfd_mach_o_cpu_subtype): Add arm64 literals. (BFD_MACH_O_LC_ENCRYPTION_INFO_64, BFD_MACH_O_LC_LINKER_OPTIONS) (BFD_MACH_O_LC_LINKER_OPTIMIZATION_HINT) (BFD_MACH_O_LC_VERSION_MIN_WATCHOS): Define. * external.h (mach_o_encryption_info_64_command_external): (mach_o_linker_option_command_external) (mach_o_dyld_cache_header_external) (mach_o_dyld_cache_mapping_info_external) (mach_o_dyld_cache_image_info_external): New types.
2015-11-15sim: cr16: convert to common sim memory modulesMike Frysinger2-9/+6
The cr16 port has a lot of translation/offset logic baked into it, but it all looks like copy & paste from the d10v port rather than something the cr16 port wants.
2015-11-15sim: drop extern C linkage from most sim interface headersMike Frysinger8-59/+9
Since these headers merely have enum's, drop the extern C linkage markings. Helps to reduce the copy & paste spam.
2015-11-11Add assembler, disassembler and linker support for power9.Peter Bergner5-0/+25
include/opcode/ * ppc.h (PPC_OPCODE_POWER9): New define. (PPC_OPCODE_VSX3): Likewise. opcodes/ * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries. Add PPC_OPCODE_VSX3 to the vsx entry. (powerpc_init_dialect): Set default dialect to power9. * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1, extract_l1 insert_xtq6, extract_xtq6): New static functions. (insert_esync): Test for illegal L operand value. (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6, XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA, XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK, XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3, PPCVSX3): New defines. (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu, fcmpo, ftdiv, ftsqrt>: Use XBF_MASK. <mcrxr>: Use XBFRARB_MASK. <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq., bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc., cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first, cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx, lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll, lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw, modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last, rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx, stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx, subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh, vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh., vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd, vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d, vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx, vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq, vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd, vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait, xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp, xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp, xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz, xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp, xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp, xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo, xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo, xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo, xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp, xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp, xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp, xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw, xxinsertw, xxperm, xxpermr, xxspltib>: New instructions. <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9. <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands. include/elf/ * ppc.h (R_PPC_REL16DX_HA): New reloction. * ppc64.h (R_PPC64_REL16DX_HA): Likewise. bfd/ * elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_REL16DX_HA. (ppc_elf_reloc_type_lookup): Handle R_PPC_REL16DX_HA. (ppc_elf_addr16_ha_reloc): Likewise. (ppc_elf_check_relocs): Likewise. (ppc_elf_relocate_section): Likewise. (is_insn_dq_form): Handle lxv and stxv instructions. * elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_REL16DX_HA. (ppc64_elf_reloc_type_lookup): Handle R_PPC64_REL16DX_HA. (ppc64_elf_ha_reloc): Likewise. (ppc64_elf_check_relocs): Likewise. (ppc64_elf_relocate_section): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. * reloc.c (BFD_RELOC_PPC_REL16DX_HA): New. elfcpp/ * powerpc.h (R_POWERPC_REL16DX_HA): Define. gas/ * doc/as.texinfo (Target PowerPC): Document -mpower9 and -mpwr9. * doc/c-ppc.texi (PowerPC-Opts): Likewise. * config/tc-ppc.c (md_show_usage): Likewise. (md_assemble): Handle BFD_RELOC_PPC_REL16DX_HA. (md_apply_fix): Likewise. (ppc_handle_align): Handle power9's group ending nop. gas/testsuite/ * gas/ppc/altivec3.s: New test. * gas/ppc/altivec3.d: Likewise. * gas/ppc/vsx3.s: Likewise. * gas/ppc/vsx3.d: Likewise. * gas/ppc/power9.s: Likewise. * gas/ppc/power9.d: Likewise. * gas/ppc/ppc.exp: Run them. * gas/ppc/power8.s <lxvx, lxvd2x, stxvx, stxvd2x>: Add new tests. * gas/ppc/power8.d: Likewise. * gas/ppc/vsx.s: <lxvx, stxvx>: Rename invalid mnemonics ... <lxvd2x, stxvd2x>: ...to this. * gas/ppc/vsx.d: Likewise. gold/ * gold/powerpc.cc (Powerpc_relocate_functions::addr16_dq): New function. (Powerpc_relocate_functions::addr16dx_ha): Likewise. (Target_powerpc::Scan::local): Handle R_POWERPC_REL16DX_HA. (Target_powerpc::Scan::global): Likewise. (Target_powerpc::Relocate::relocate): Likewise. ld/testsuite/ * ld-powerpc/addpcis.d: New test. * ld-powerpc/addpcis.s: New test. * ld-powerpc/powerpc.exp: Run it.
2015-11-10sim: cr16/d10v: localize translation funcsMike Frysinger3-46/+9
These functions are only used in the interp module, so there's no point in exporting them and declaring them in the external sim interface.
2015-11-09Modify obstack.[hc] to avoid having to include other gnulib filesAlan Modra2-1/+10
Using the standard gnulib obstack source requires importing quite a lot of other files from gnulib, and requires build changes. include/ PR gdb/17133 * obstack.h (__attribute_pure__): Expand _GL_ATTRIBUTE_PURE. libiberty/ PR gdb/17133 * obstack.c (__alignof__): Expand alignof_type from alignof.h. (obstack_exit_failure): Don't use exitfail.h. (_): Include libintl.h when HAVE_LIBINTL_H and nls enabled. Provide default. Don't include gettext.h. (_Noreturn): Define. * obstacks.texi: Adjust node references to external libc info files.
2015-11-09Copy gnulib obstack filesAlan Modra2-461/+454
This copies obstack.[ch] from gnulib, and updates the docs. The next patch should be applied if someone repeats the import at a later date. include/ PR gdb/17133 * obstack.h: Import current gnulib file. libiberty/ PR gdb/17133 * obstack.c: Import current gnulib file. * obstacks.texi: Updated doc, from glibc's manual/memory.texi.
2015-11-02Disassemble RX NOP instructions as such.Nick Clifton2-0/+8
opcode * rx.h (enum RX_Opcode_ID): Add more NOP opcodes. opcodes * rx-decode.opc (rx_decode_opcode): Decode extra NOP instructions. * rx-decode.c: Regenerate. tests * gas/rx/max.d: Update expecetd disassembly. * gas/rx/nod.d: Likewise. * gas/rx/nop.sm: Add tests of more NOP instructions.
2015-11-02Fix disassembly of RX zero-offset register indirect instructions.Nick Clifton2-0/+5
opcode * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect. opcodes * rx-decode.opc (rx_disp): If the displacement is zero, set the type to RX_Operand_Zero_Indirect. * rx-decode.c: Regenerate. * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect. gas * config/rx-parse.y: Allow zero value for 5-bit displacements. tests * gas/rx/mov.sm: Add tests for zero offset indirect moves. * gas/rx/mov.d: Update expected output.
2015-10-28Pass noaliases_p to aarch64_decode_insnYao Qi2-1/+5
Nowadays aarch64_decode_insn is a public interface used by both opcodes and gdb. However, its behaviour relies on a global variable no_aliases, which isn't a good practise. On the other hand, In default, no_aliases is zero, but in GDB, we do want no alias when decoding instructions for prologue analysis (patches to be posted), so that we can handle both instructions "add" and "mov" (an alias of "add") as "add". The code in GDB can be simplified. This patch adds a new argument in aarch64_decode_insn, and pass no_aliases to it. In GDB side, always pass 1 to it. include/opcode: 2015-10-28 Yao Qi <yao.qi@linaro.org> * aarch64.h (aarch64_decode_insn): Update declaration. opcodes: 2015-10-28 Yao Qi <yao.qi@linaro.org> * aarch64-dis.c (aarch64_decode_insn): Add one argument noaliases_p. Update comments. Pass noaliases_p rather than no_aliases to aarch64_opcode_decode. (print_insn_aarch64_word): Pass no_aliases to aarch64_decode_insn. gdb: 2015-10-28 Yao Qi <yao.qi@linaro.org> * aarch64-tdep.c (aarch64_software_single_step): Pass 1 to aarch64_decode_insn.
2015-10-28Fix errors in the gas testsuite for the ARC target.Cupertino Miranda2-7/+18
bfd * reloc.c (BFD_RELOC_ARC_32_PCREL): New entry. (ARC_TLS_DTPOFF): Arrange it in order. * elf32-arc.c (arc_elf_howto_ini): Update formula. (get_middle_endian_relocation): New function. (PDATA): Define. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. elf * arc-reloc.def (ARC_32_PCREL): New definition. gas * config/tc-arc.c (tokenize_arguments): Avoid creating unused symbols when parsing relocation types. (md_apply_fix): Handle TLS relocations. Fix BFD_RELOC_ARC_32_PCREL relocation. (arc_check_reloc): Emit BFD_RELOC_ARC_32_PCREL relocation.
2015-10-27Add support to readelf for reading NetBSD ELF core notes.Stephen Fisher2-0/+5
binutils * binutils.c (process_netbsd_elf_note): New function. (process_note): Call the new function for NetBSD core notes. include * common.h (NT_NETBSD_MARCH): Define.
2015-10-22Add "-z call-nop=PADDING" option to ldH.J. Lu2-0/+11
The ld linker can transform indirect call to a locally defined function, foo, via its GOT slot, to either "NOP call foo" or "call foo NOP" where NOP is a 1-byte NOP padding. This patch adds a "-z call-nop=PADDING" option to x86 ld to control 1-byte NOP padding for x86 call instruction. PADDING is one of prefix-addr, prefix-nop, suffix-nop, prefix-NUMBER or suffix-NUMBER. bfd/ * elf32-i386.c (elf_i386_convert_load): Use call_nop_byte and check call_nop_as_suffix for 1-byte NOP padding to pad call. * elf64-x86-64.c (elf_x86_64_convert_load): Likewise. include/ * bfdlink.h (bfd_link_info): Add call_nop_as_suffix and call_nop_byte. ld/ * ld/ld.texinfo: Document "-z call-nop=PADDING" option. * emulparams/call_nop.sh: New file. * emulparams/elf_i386_be.sh: Source ${srcdir}/emulparams/call_nop.sh. * emulparams/elf_i386_chaos.sh: Likewise. * emulparams/elf_i386_ldso.sh: Likewise. * emulparams/elf_i386_vxworks.sh: Likewise. * emulparams/elf_iamcu.sh: Likewise. * emulparams/elf_k1om.sh: Likewise. * emulparams/elf_l1om.sh: Likewise. * emulparams/elf_x86_64.sh: Likewise. * emultempl/elf32.em (gld${EMULATION_NAME}_before_parse): Set link_info.call_nop_byte if $CALL_NOP_BYTE isn't empty. ld/testsuite/ * ld-i386/call3.s: New file. * ld-i386/call3a.d: Likewise. * ld-i386/call3b.d: Likewise. * ld-i386/call3c.d: Likewise. * ld-i386/call3d.d: Likewise. * ld-i386/call3e.d: Likewise. * ld-i386/call3f.d: Likewise. * ld-i386/call3g.d: Likewise. * ld-i386/call3h.d: Likewise. * ld-i386/load1-nacl.d: Likewise. * ld-x86-64/call1.s: Likewise. * ld-x86-64/call1a.d: Likewise. * ld-x86-64/call1b.d: Likewise. * ld-x86-64/call1c.d: Likewise. * ld-x86-64/call1d.d: Likewise. * ld-x86-64/call1e.d: Likewise. * ld-x86-64/call1f.d: Likewise. * ld-x86-64/call1g.d: Likewise. * ld-x86-64/call1h.d: Likewise. * ld-x86-64/call1i.d: Likewise. * ld-x86-64/load1a-nacl.d: Likewise. * ld-x86-64/load1b-nacl.d: Likewise. * ld-x86-64/load1c-nacl.d: Likewise. * ld-x86-64/load1d-nacl.d: Likewise.
2015-10-22Add R_X86_64_[REX_]GOTPCRELX support to gas and ldH.J. Lu2-4/+15
This patch adds support for the R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX relocations proposed in https://groups.google.com/forum/#!topic/x86-64-abi/n9AWHogmVY0 to gas and ld. It updates gas to generate R_X86_64_GOTPCRELX, R_X86_64_REX_GOTPCRELX if there is a REX prefix, relocation for memory operand, foo@GOTPCREL(%rip). With the locally defined symbol, foo, we convert mov foo@GOTPCREL(%rip), %reg to lea foo(%rip), %reg and convert call/jmp *foo@GOTPCREL(%rip) to nop call foo/jmp foo nop When PIC is false, convert test %reg, foo@GOTPCREL(%rip) to test $foo, %reg and convert binop foo@GOTPCREL(%rip), %reg to binop $foo, %reg where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions. bfd/ * elf64-x86-64.c: Include opcode/i386.h. (x86_64_elf_howto_table): Add R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX. (R_X86_64_standard): Replace R_X86_64_PLT32_BND with R_X86_64_REX_GOTPCRELX. (x86_64_reloc_map): Add BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX. (need_convert_mov_to_lea): Renamed to ... (need_convert_load): This. (elf_x86_64_check_relocs): Handle R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX. Replace need_convert_mov_to_lea with need_convert_load. (elf_x86_64_gc_sweep_hook): Handle R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX. (elf_x86_64_size_dynamic_sections): Likewise. (elf_x86_64_relocate_section): Likewise. (elf_x86_64_convert_mov_to_lea): Renamed to ... (elf_x86_64_convert_load): This. Replace need_convert_mov_to_lea with need_convert_load. Support R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX transformations. * reloc.c (BFD_RELOC_X86_64_GOTPCRELX): New. (BFD_RELOC_X86_64_REX_GOTPCRELX): Likewise. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX. (tc_gen_reloc): Likewise. (i386_validate_fix): Generate BFD_RELOC_X86_64_GOTPCRELX or BFD_RELOC_X86_64_REX_GOTPCRELX if fx_tcbit2 is set. * config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Also return true for BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX. gas/testsuite/ * gas/i386/i386.exp: Run x86-64-gotpcrel. * gas/i386/x86-64-gotpcrel.d: New file. * gas/i386/x86-64-gotpcrel.s: Likewise. * gas/i386/ilp32/x86-64-gotpcrel.d: Likewise. * gas/i386/x86-64-localpic.d: Replace R_X86_64_GOTPCREL with R_X86_64_REX_GOTPCRELX. * gas/i386/ilp32/x86-64-localpic.d: Likewise. include/elf/ * x86-64.h (R_X86_64_GOTPCRELX): New. (R_X86_64_REX_GOTPCRELX): Likewise. ld/testsuite/ * ld-ifunc/ifunc-5r-local-x86-64.d: Replace R_X86_64_GOTPCREL with R_X86_64_REX_GOTPCRELX. * ld-x86-64/plt-main1.rd: Likewise. * ld-x86-64/plt-main3.rd: Likewise. * ld-x86-64/plt-main4.rd: Likewise. * ld-x86-64/gotpcrel1.dd: New file. * ld-x86-64/gotpcrel1.out: Likewise. * ld-x86-64/gotpcrel1a.S: Likewise. * ld-x86-64/gotpcrel1b.c: Likewise. * ld-x86-64/gotpcrel1c.c: Likewise. * ld-x86-64/gotpcrel1d.S: Likewise. * ld-x86-64/load1.s: Likewise. * ld-x86-64/load1a.d: Likewise. * ld-x86-64/load1b.d: Likewise. * ld-x86-64/load1c.d: Likewise. * ld-x86-64/load1d.d: Likewise. * ld-x86-64/x86-64.exp: Run load1a, load1b, load1c and load1d tests. Run gotpcrel1 test.
2015-10-22Add R_386_GOT32X support to gas and ldH.J. Lu2-0/+6
This patch adds support for the R_386_GOT32X relocation proposed in https://groups.google.com/forum/#!topic/ia32-abi/GbJJskkid4I to gas and ld. It updates gas to generate R_386_GOT32X relocation for memory operand, foo@GOT[(%reg)]. We must encode "mov foo@GOT, %eax" with the 0x8b opcode, instead of the 0xb8 opcode, so that it can be transformed to "lea foo, %eax". With the locally defined symbol, foo, we convert mov foo@GOT[(%reg1)], %reg2 to lea foo[@GOTOFF(%reg1)], %reg2 and convert call/jmp *foo@GOT[(%reg)] to nop call foo/jmp foo nop When PIC is false, convert test %reg1, foo@GOT[(%reg2)] to test $foo, %reg1 and convert binop foo@GOT[(%reg1)], %reg2 to binop $foo, %reg2 where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions. bfd/ * elf32-i386.c: Include opcode/i386.h. (elf_howto_table): Add R_386_GOT32X. (R_386_ext2): Replace R_386_IRELATIVE with R_386_GOT32X. (elf_i386_reloc_type_lookup): Handle BFD_RELOC_386_GOT32X. (need_convert_mov_to_lea): Renamed to ... (need_convert_load): This. (elf_i386_check_relocs): Handle R_386_GOT32X. Replace need_convert_mov_to_lea with need_convert_load. (elf_i386_gc_sweep_hook): Handle R_386_GOT32X. (elf_i386_size_dynamic_sections): Likewise. (elf_i386_relocate_section): Likewise. (elf_i386_convert_mov_to_lea): Renamed to ... (elf_i386_convert_load): This. Replace need_convert_mov_to_lea with need_convert_load. Support R_386_GOT32X transformations. * reloc.c (BFD_RELOC_386_GOT32X): New. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_386_GOT32X. (tc_gen_reloc): Likewise. (match_template): Force 0x8b encoding for "mov foo@GOT, %eax". (output_disp): Check for "call/jmp *mem", "mov mem, %reg", "test %reg, mem" and "binop mem, %reg" where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions. Set fx_tcbit if the REX prefix is generated. Set fx_tcbit2 if BFD_RELOC_386_GOT32X should be generated. (i386_validate_fix): Generate BFD_RELOC_386_GOT32X if fx_tcbit2 is set. gas/testsuite/ * gas/i386/got.d: New file. * gas/i386/got.s: Likewise. * gas/i386/i386.exp: Run got. * gas/i386/localpic.d: Replace R_386_GOT32 with R_386_GOT32X. * gas/i386/mixed-mode-reloc32.d: Likewise. * gas/i386/reloc32.d: Likewise. include/elf/ * i386.h (R_386_GOT32X): New relocation. ld/testsuite/ * ld-i386/branch1.d: New file. * ld-i386/branch1.s: Likewise. * ld-i386/call1.d: Likewise. * ld-i386/call1.s: Likewise. * ld-i386/call2.d: Likewise. * ld-i386/call2.s: Likewise. * ld-i386/got1.dd: Likewise. * ld-i386/got1.out: Likewise. * ld-i386/got1a.S: Likewise. * ld-i386/got1b.c: Likewise. * ld-i386/got1c.c: Likewise. * ld-i386/got1d.S: Likewise. * ld-i386/jmp1.d: Likewise. * ld-i386/jmp1.s: Likewise. * ld-i386/jmp2.d: Likewise. * ld-i386/jmp2.s: Likewise. * ld-i386/load1.d: Likewise. * ld-i386/load1.s: Likewise. * ld-i386/load2.d: Likewise. * ld-i386/load2.s: Likewise. * ld-i386/load3.d: Likewise. * ld-i386/load3.s: Likewise. * ld-i386/load4.s: Likewise. * ld-i386/load4a.d: Likewise. * ld-i386/load4b.d: Likewise. * ld-i386/load5.s: Likewise. * ld-i386/load5a.d: Likewise. * ld-i386/load5b.d: Likewise. * ld-i386/load6.d: Likewise. * ld-i386/load6.s: Likewise. * ld-i386/i386.exp: Run branch1, call1, call2, jmp1, jmp2, load1, load2, load3, load4a, load4b, load5a, load5b and load6 tests. Run got1 test.
2015-10-07Avoid using 'template' C++ keywordYao Qi2-1/+6
'template' is used in include/opcode/aarch64.h as below, typedef struct { const char *template; uint32_t value; int has_xt; } aarch64_sys_ins_reg; and it triggers compilation errors when GDB is built in C++ mode. In file included from git/gdb/aarch64-tdep.c:62:0: git/gdb/../include/opcode/aarch64.h:651:15: error: expected unqualified-id before 'template' const char *template; This patch is to rename field template to name. gas/ * config/tc-aarch64.c (md_begin): Access field 'name' rather than 'template'. include/opcode/ * aarch64.h (aarch64_sys_ins_reg) <template>: Removed. <name>: New field. opcodes/ * aarch64-dis.c (aarch64_ext_sysins_op): Access field 'name' rather than 'template'. * aarch64-opc.c (aarch64_print_operand): Likewise.
2015-10-07Wrap include/opcode/aarch64.h in extern "C" for C++Yao Qi2-0/+12
This is sufficient to link an aarch64 GDB built in C++ mode. Pedro did something similar in Feb https://sourceware.org/ml/binutils/2015-02/msg00176.html include/opcode/ 2015-10-07 Yao Qi <yao.qi@linaro.org> * aarch64.h [__cplusplus]: Wrap in extern "C".
2015-10-07New ARC implementation.Nick Clifton9-268/+1088
bfd * archures.c: Remove support for older ARC. Added support for new ARC cpus (ARC600, ARC601, ARC700, ARCV2). * bfd-in2.h: Likewise. * config.bfd: Likewise. * cpu-arc.c: Likewise. * elf32-arc.c: Totally changed file with a refactored inplementation of the ARC port. * libbfd.h: Added ARC specific relocation types. * reloc.c: Likewise. gas * config/tc-arc.c: Revamped file for ARC support. * config/tc-arc.h: Likewise. * doc/as.texinfo: Add new ARC options. * doc/c-arc.texi: Likewise. ld * configure.tgt: Added target arc-*-elf* and arc*-*-linux-uclibc*. * emulparams/arcebelf_prof.sh: New file * emulparams/arcebelf.sh: Likewise. * emulparams/arceblinux_prof.sh: Likewise. * emulparams/arceblinux.sh: Likewise. * emulparams/arcelf_prof.sh: Likewise. * emulparams/arcelf.sh: Likewise. * emulparams/arclinux_prof.sh: Likewise. * emulparams/arclinux.sh: Likewise. * emulparams/arcv2elfx.sh: Likewise. * emulparams/arcv2elf.sh: Likewise. * emultempl/arclinux.em: Likewise. * scripttempl/arclinux.sc: Likewise. * scripttempl/elfarc.sc: Likewise. * scripttempl/elfarcv2.sc: Likewise * Makefile.am: Add new ARC emulations. * Makefile.in: Regenerate. * NEWS: Mention the new feature. opcodes * arc-dis.c: Revamped file for ARC support * arc-dis.h: Likewise. * arc-ext.c: Likewise. * arc-ext.h: Likewise. * arc-opc.c: Likewise. * arc-fxi.h: New file. * arc-regs.h: Likewise. * arc-tbl.h: Likewise. binutils * readelf.c (get_machine_name): Remove A5 reference. Add ARCompact and ARCv2. (get_machine_flags): Handle EM_ARCV2 and EM_ARCOMPACT. (guess_is_rela): Likewise. (dump_relocations): Likewise. (is_32bit_abs_reloc): Likewise. (is_16bit_abs_reloc): Likewise. (is_none_reloc): Likewise. * NEWS: Mention the new feature. include * dis-asm.h (arc_get_disassembler): Correct declaration. * arc-reloc.def: Macro file with definition of all relocation types. * arc.h: Changed macros for the newly supported ARC cpus. Altered enum defining the supported relocations. * common.h: Changed EM_ARC_A5 definition to EM_ARC_COMPACT. Added macro for EM_ARC_COMPACT2. * arc-func.h: New file. * arc.h: Likewise.
2015-10-02Make aarch64_zero_register_p declaration starts from column oneYao Qi2-2/+7
include/opcode: 2015-10-02 Yao Qi <yao.qi@linaro.org> * aarch64.h (aarch64_zero_register_p): Move the declaration to column one.
2015-10-02[aarch64] expose disas_aarch64_insn and rename it to aarch64_decode_insnYao Qi2-0/+7
We want to use disas_aarch64_insn inside GDB to decode instructions, so this patch exposes it and rename it to aarch64_decode_insn to follow the conventions of other interfaces. include/opcode: 2015-10-02 Yao Qi <yao.qi@linaro.org> * aarch64.h (aarch64_decode_insn): Declare it. opcodes: 2015-10-02 Yao Qi <yao.qi@linaro.org> * aarch64-dis.c (disas_aarch64_insn): Remove static. Change argument insn type to aarch64_insn. Rename to ... (aarch64_decode_insn): ... it. (print_insn_aarch64_word): Caller updated.
2015-09-30Resync files in the binutils repository that are maintained in the gcc ↵Nick Clifton2-0/+20
repository. . 2015-08-23 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org> PR libfortran/54572 * Makefile.def: Make libgfortran depend on libbacktrace. * Makefile.in: Regenerate. 2015-08-12 Tom de Vries <tom@codesourcery.com> PR other/67092 PR other/67098 * configure.ac: Remove --with_host_libstdcxx support. * configure: Regenerate. 2015-08-10 Thomas Schwinge <thomas@codesourcery.com> Jakub Jelinek <jakub@redhat.com> * configure.ac (noconfigdirs): Don't add "target-libgomp" for target nvptx*-*-*. * configure: Regenerate. include 2015-08-14 Pierre-Marie de Rodat <derodat@adacore.com> * dwarf2.def (DW_AT_GNU_bias): New attribute. 2015-08-14 Pierre-Marie de Rodat <derodat@adacore.com> * dwarf2.def (DW_AT_GNU_numerator, DW_AT_GNU_denominator): New attributes. libiberty 2015-08-15 Ian Lance Taylor <iant@google.com> * cp-demangle.c (d_abi_tags): Preserve di->last_name across any ABI tags.
2015-09-29Add support for extensions in the .machine pseudoop on S/390, e.g. ".machine ↵Dominik Vogt2-0/+9
zEC12+nohtm+vx" gas * doc/c-s390.texi: Add documentation. Add missing code markup. * config/tc-s390.c (current_flags): New static variable. (s390_parse_cpu): Parse cpu flags a la "+nohtm" etc. (s390_setup_opcodes): Use cpu flags to determine the set of opcodes. Fix indentation. (md_parse_option): Call s390_parse_cpu with the new signature. (s390_machine): Likewise. Keep track of current_flags. Simplify code a bit. undefine MAX_HISTORY at end of function. (s390_machinemode): undefine MAX_HISTORY at end of function. Update an error message. tests * gas/s390/s390.exp: Add new tests. * gas/s390/machine-parsing-1.s: New test file. * gas/s390/machine-parsing-1.l: Likewise. * gas/s390/machine-parsing-2.s: Likewise. * gas/s390/machine-parsing-2.l: Likewise. * gas/s390/machine-parsing-3.s: Likewise. * gas/s390/machine-parsing-3.l: Likewise. * gas/s390/machine-parsing-4.s: Likewise. * gas/s390/machine-parsing-4.l: Likewise. * gas/s390/machine-parsing-5.s: Likewise. * gas/s390/machine-parsing-5.l: Likewise. * gas/s390/machine-parsing-6.s: Likewise. * gas/s390/machine-parsing-6.l: Likewise. opcode * s390.h (S390_INSTR_FLAG_HTM): New flag. (S390_INSTR_FLAG_VX): New flag. (S390_INSTR_FLAG_FACILITY_MASK): New flag mask. opcodes * s390-mkopc.c (main): Parse htm and vx flag. * s390-opc.txt: Mark instructions from the hardware transactional memory and vector facilities with the "htm"/"vx" flag.
2015-09-28FT32: define macros for instruction recognition.jamesbowman2-0/+10
Other places (e.g. the gdb stack unwinder) can use these instead of hard-coded patterns. [include/Changelog] 2015-09-26 James Bowman <james.bowman@ftdichip.com> * opcode/ft32.h: Add instruction macros FT32_*()
2015-09-23Fix compile time warnings generated when compiling with clang.Nick Clifton2-1/+6
bfd * bout.c (b_out_slurp_reloc_table): Cast constant to unsigned in order to avoid problems with left shifting negative values. (abs32code): Likewise. * mach-o.c (FILE_ALIGN): Likewise. * coff-rs6000.c (xcoff_debug_sections): Delete unused static array. * elf32-visium.c (visium_reloc_map): Likewise. * elf32-arm.c (elf32_arm_final_link_relocate): Remove useless calls to abs function. * elf32-frv.c (_frvfdpic_relax_tls_entries): Likewise. * elf32-score.c (score_elf_final_link_relocate): Likewise. * elf32-score7.c (score_elf_final_link_relocate): Likewise. * elf32-i860.c (i860_howto_pc26_reloc): Use multiplication instead of shifting to create a negative mask. * elf32-msp430.c (elf_backend_special_sections): Define. * elfxx-mips.c (got_ofst_reloc_p): Delete unused function. (got_hi16_reloc_p): Delete unused function. * ppcboot.c (ppcboot_bfd_print_private_bfd_data): Fix test of partition name. gas * config/tc-ppc.c (insn_validate): Cast PPC_OPSHIFT_INV to an int. opcode * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left shifting. ld * emultempl/elf32.em (ehdr_start_empty): New static variable. (before_allocation): Use it to initialise ehdr_start_save. * emultempl/pe.em (write_build_id): Remove useless double parenthesis. * emultempl/pep.em (write_build_id): Likewise. opcodes * bfin-dis.c (fmtconst): Remove unnecessary call to the abs function. * tic30-dis.c (print_branch): Likewise. * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed value before left shifting. * fr30-ibld.c (fr30_cgen_extract_operand): Likewise. * hppa-dis.c (print_insn_hppa): Likewise. * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static array. * msp430-dis.c (msp430_singleoperand): Likewise. (msp430_doubleoperand): Likewise. (print_insn_msp430): Likewise. * nds32-asm.c (parse_operand): Likewise. * sh-opc.h (MASK): Likewise. * v850-dis.c (get_operand_value): Likewise.
2015-09-22Enhance the RX disassembler to detect and report bad instructions.Nick Clifton2-0/+6
opcode * rx.h (enum RX_Size): Add RX_Bad_Size entry. opcodes * rx-decode.opc (bwl): Use RX_Bad_Size. (sbwl): Likewise. (ubwl): Likewise. Rename to ubw. (uBWL): Rename to uBW. Replace all references to uBWL with uBW. * rx-decode.c: Regenerate. * rx-dis.c (size_names): Add entry for RX_Bad_Size. (opsize_names): Likewise. (print_insn_rx): Detect and report RX_Bad_Size.
2015-09-22Solaris PIE supportRainer Orth2-0/+6
include/elf: * common.h (DF_1_STUB, DF_1_PIE): Define. ld: * emulparams/solaris2.sh (GENERATE_PIE_SCRIPT): Set to yes. * emultempl/elf32.em: Include ldlex.h. (gld${EMULATION_NAME}_handle_option) [GENERATE_PIE_SCRIPT] <OPTION_PIE>: Set DF_1_PIE. binutils: * readelf.c (process_dynamic_section): Handle DF_1_STUB, DF_1_PIE.
2015-09-21Change ch_type in Elf64_External_Chdr to 4 bytesH.J. Lu2-1/+7
The ch_type field in Elf64_External_Chdr is 4 bytes, followed by a 4-byte padding. This change doesn't introduce any functional change since only the lower 32 bits of the ch_type field are used. * external.h (Elf64_External_Chdr): Change ch_type to 4 bytes and add ch_reserved.
2015-09-20Add --no-dynamic-linker option to ld, for static PIE useRich Felker2-0/+7
Inhibits output of .interp section in ELF executables. include/ * bfdlink.h (struct bfd_link_info): Add "nointerp" field. bfd/ * elflink.c (_bfd_elf_link_create_dynamic_sections): Don't create .interp when info->nointerp. (bfd_elf_size_dynamic_sections): Adjust assert. * elf32-arm.c (elf32_arm_size_dynamic_sections): Don't size .interp when info->nointerp. * elf32-bfin.c (elf32_bfinfdpic_size_dynamic_sections): Likewise. * elf32-cr16.c (_bfd_cr16_elf_size_dynamic_sections): Likewise. * elf32-cris.c (elf_cris_size_dynamic_sections): Likewise. * elf32-frv.c (elf32_frvfdpic_size_dynamic_sections): Likewise. * elf32-hppa.c (elf32_hppa_size_dynamic_sections): Likewise. * elf32-i370.c (i370_elf_size_dynamic_sections): Likewise. * elf32-i386.c (elf_i386_size_dynamic_sections): Likewise. * elf32-lm32.c (lm32_elf_size_dynamic_sections): Likewise. * elf32-m32r.c (m32r_elf_size_dynamic_sections): Likewise. * elf32-m68k.c (elf_m68k_size_dynamic_sections): Likewise. * elf32-metag.c (elf_metag_size_dynamic_sections): Likewise. * elf32-nds32.c (nds32_elf_size_dynamic_sections): Likewise. * elf32-nios2.c (nios2_elf32_size_dynamic_sections): Likewise. * elf32-or1k.c (or1k_elf_size_dynamic_sections): Likewise. * elf32-ppc.c (ppc_elf_size_dynamic_sections): Likewise. * elf32-s390.c (elf_s390_size_dynamic_sections): Likewise. * elf32-score.c (s3_bfd_score_elf_size_dynamic_sections): Likewise. * elf32-score7.c (s7_bfd_score_elf_size_dynamic_sections): Likewise. * elf32-sh.c (sh_elf_size_dynamic_sections): Likewise. * elf32-tic6x.c (elf32_tic6x_size_dynamic_sections): Likewise. * elf32-tilepro.c (tilepro_elf_size_dynamic_sections): Likewise. * elf32-vax.c (elf_vax_size_dynamic_sections): Likewise. * elf32-xtensa.c (elf_xtensa_size_dynamic_sections): Likewise. * elf64-alpha.c (elf64_alpha_size_dynamic_sections): Likewise. * elf64-hppa.c (elf64_hppa_size_dynamic_sections): Likewise. * elf64-ppc.c (ppc64_elf_size_dynamic_sections): Likewise. * elf64-s390.c (elf_s390_size_dynamic_sections): Likewise. * elf64-sh64.c (sh64_elf64_size_dynamic_sections): Likewise. * elf64-x86-64.c (elf_x86_64_size_dynamic_sections): Likewise. * elfnn-aarch64.c (elfNN_aarch64_size_dynamic_sections): Likewise. * elfnn-ia64.c (elfNN_ia64_size_dynamic_sections): Likewise. * elfxx-mips.c (_bfd_mips_elf_size_dynamic_sections): Likewise. * elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections): Likewise. * elfxx-tilegx.c (tilegx_elf_size_dynamic_sections): Likewise. ld/ * ld.texinfo (--no-dynamic-linker): Document. * ldlex.h (enum option_values): Add OPTION_NO_DYNAMIC_LINKER. * lexsup.c (ld_options, parse_args): Handle --no-dynamic-linker.
generated by cgit v1.1 at 2025-02-20 19:14:52 +0000