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2016-01-11Import changes made to files shared with the FSF GCC project.Nick Clifton2-2/+12
Import the following changes from the GCC mainline: 2015-11-13 Tsvetkova Alexandra <aleksandra.tsvetkova@intel.com> * configure.ac: Enable libmpx by default. * configure: Regenerated. 2015-11-19 Martin Liska <mliska@suse.cz> * .gitignore: Add .clang-format to ignored files. * Makefile.tpl: Add clang-format. * Makefile.in: Regenerate. 2015-12-01 Andreas Tobler <andreast@gcc.gnu.org> PR libffi/65726 * Makefile.def (lang_env_dependencies): Make libffi depend on cxx. * Makefile.in: Regenerate. 2015-12-02 Ian Lance Taylor <iant@google.com> PR go/66147 * Makefile.tpl (HOST_EXPORTS): Add XGCC_FLAGS_FOR_TARGET. * Makefile.in: Regenerate. 2015-12-17 Nathan Sidwell <nathan@acm.org> * config/isl.m4 (ISL_CHECK_VERSION): Add gmp libs. * configure: Regenerate. 2015-12-17 Sebastian Pop <s.pop@samsung.com> * Makefile.in: Replace ISL with isl. * Makefile.tpl: Same. * config/isl.m4: Same. * configure.ac: Same. * contrib/download_prerequisites: Same. * configure: Regenerate. 2016-01-01 Ben Elliston <bje@gnu.org> * config.guess: Import version 2016-01-01. * config.sub: Likewise. include 2016-01-07 Mike Frysinger <vapier@gentoo.org> * longlong.h: Change !__SHMEDIA__ to (!defined (__SHMEDIA__) || !__SHMEDIA__). Change __SHMEDIA__ to defined (__SHMEDIA__) && __SHMEDIA__.
2016-01-06sim: sim_{create_inferior,open,parse_args}: constify argv/env slightlyMike Frysinger2-2/+9
2016-01-03 Mike Frysinger <vapier@gentoo.org> * sim-options.c (sim_parse_args): Mark argv array const. * sim-options.h (sim_parse_args): Likewise.
2016-01-06MIPS/include: opcode/mips.h: Add a summary of MIPS16 operand codesMaciej W. Rozycki2-0/+10
include/ * opcode/mips.h: Add a summary of MIPS16 operand codes.
2016-01-05libiberty: {count,dup,write}argv: constify argv input slightlyMike Frysinger2-3/+8
Would be more useful if we could use "const char * const *", but there's a long standing bug where gcc warns about incompatible pointers when you try to pass in "char **". We can at least constify the array itself as gcc will not warn in that case.
2016-01-01Copyright update for binutilsAlan Modra295-295/+298
2016-01-01New 2016 binutils ChangeLog filesAlan Modra1-0/+17
Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01binutils ChangeLog rotationAlan Modra10-0/+0
2016-01-01GDB copyright headers update after running GDB's copyright.py script.Joel Brobecker22-22/+22
gdb/ChangeLog: Update year range in copyright notice of all files.
2015-12-30Fix assorted ChangeLog errorsAlan Modra5-244/+261
2015-12-24Add assembler support for ARMv8-M BaselineThomas Preud'homme4-21/+62
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ (tag_cpu_arch_combine): Adjust comment in v4t_plus_v6_m with regards to merging with ARMv8-M Baseline. binutils/ * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Baseline Tag_CPU_arch value. gas/ * config/tc-arm.c (arm_ext_v6t2_v8m): New feature for instructions shared between ARMv6T2 and ARMv8-M. (move_or_literal_pool): Check mov.w/mvn and movw availability against arm_ext_v6t2 and arm_ext_v6t2_v8m respectively instead of checking arm_arch_t2. (do_t_branch): Error out for wide conditional branch instructions if targetting ARMv8-M Baseline. (non_v6t2_wide_only_insn): Add the logic for new wide-only instructions in ARMv8-M Baseline. (wide_insn_ok): New function. (md_assemble): Use wide_insn_ok instead of non_v6t2_wide_only_insn and adapt error message for unsupported wide instruction to ARMv8-M Baseline. (insns): Reorganize instructions shared by ARMv8-M Baseline and ARMv6t2 architecture. (arm_cpus): Set feature bit ARM_EXT2_V6T2_V8M for marvell-pj4 and marvell-whitney cores. (arm_archs): Define armv8-m.base architecture. (cpu_arch_ver): Define ARM_ARCH_V8M_BASE architecture version. (aeabi_set_public_attributes): Add logic to set Tag_CPU_arch to 17 for ARMv8-M Mainline. Set Tag_DIV_use for ARMv8-M Baseline as well. gas/testsuite/ * gas/arm/archv8m-base.d: New file. * gas/arm/attr-march-armv8m.base.d: Likewise. * gas/arm/armv8m.base-idiv.d: Likewise. * gas/arm/any-armv8m.d: Adapt to deal with ARMv8-M Baseline. include/elf/ * arm.h (TAG_CPU_ARCH_V8M_BASE): Declare. include/opcode/ * arm.h (ARM_EXT2_V6T2_V8M): New extension bit. (ARM_AEXT2_V8A): New architecture extension bitfield. (ARM_AEXT2_V8_1A): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS. (ARM_AEXT_V8M_BASE): New architecture extension bitfield. (ARM_AEXT2_V8M): Add extension bit ARM_EXT2_V6T2_V8M. (ARM_ARCH_V6T2): Use ARM_EXT2_V6T2_V8M for the second extension bitfield. (ARM_ARCH_V6KT2): Likewise. (ARM_ARCH_V6ZT2): Likewise. (ARM_ARCH_V6KZT2): Likewise. (ARM_ARCH_V7): Likewise. (ARM_ARCH_V7A): Likewise. (ARM_ARCH_V7VE): Likewise. (ARM_ARCH_V7R): Likewise. (ARM_ARCH_V7M): Likewise. (ARM_ARCH_V7EM): Likewise. (ARM_ARCH_V8A): Likewise. (ARM_ARCH_V8M_BASE): New architecture bitfield. (ARM_ARCH_THUMB2): Include instructions shared by ARMv6t2 and ARMv8-M. (ARM_ARCH_V7A_SEC): Use ARM_EXT2_V6T2_V8M for the second extension bitfield and reindent. (ARM_ARCH_V7A_MP_SEC): Likewise. (ARM_ARCH_V7R_IDIV): Likewise. (ARM_ARCH_V8A_FP): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS. (ARM_ARCH_V8A_SIMD): Likewise. (ARM_ARCH_V8A_CRYPTOV1): Likewise. opcodes/ * arm-dis.c (arm_opcodes): Guard movw, movt cbz, cbnz, clrex, ldrex, ldrexb, ldrexh, strex, strexb, strexh shared by ARMv6T2 and ARMv8-M by ARM_EXT2_V6T2_V8M instead of ARM_EXT_V6T2.
2015-12-24Add assembler support for ARMv8-M MainlineThomas Preud'homme4-18/+54
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ (tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in comb array. binutils/ * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch value. (arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use value. gas/ * config/tc-arm.c (arm_ext_m): Include ARMv8-M. (arm_ext_v8m): New feature for ARMv8-M. (arm_ext_atomics): New feature for ARMv8 atomics. (do_tt): New encoding function for TT* instructions. (insns): Add new entries for ARMv8-M specific instructions and reorganize the ones shared by ARMv8-M Mainline and ARMv8-A. (arm_archs): Define armv8-m.main architecture. (cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and clarify the ordering rule. (aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile to 'A' if extension bit for atomic instructions is set, unless it is ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0 for ARMv8-M Mainline. gas/testsuite/ * gas/arm/archv8m.s: New file. * gas/arm/archv8m-main.d: Likewise. * gas/arm/attr-march-armv8m.main.d: Likewise. * gas/arm/any-armv8m.s: Likewise. * gas/arm/any-armv8m.d: Likewise. include/elf/ * arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare. (MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN. (TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15. include/opcode/ * arm.h (ARM_EXT2_ATOMICS): New extension bit. (ARM_EXT2_V8M): Likewise. (ARM_EXT_V8): Adjust comment with regards to atomics and remove mention of legacy use for that bit. (ARM_AEXT2_V8_1A): New architecture extension bitfield. (ARM_AEXT2_V8_2A): Likewise. (ARM_AEXT_V8M_MAIN): Likewise. (ARM_AEXT2_V8M): Likewise. (ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield. (ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A. (ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A. (ARM_ARCH_V8M_MAIN): New architecture feature bitfield. (ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield and reindent. (ARM_ARCH_V8A_SIMD): Likewise. (ARM_ARCH_V8A_CRYPTOV1): Likewise. (ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of feature bits. (ARM_ARCH_V8_1A_SIMD): Likewise. (ARM_ARCH_V8_1A_CRYPTOV1): Likewise. opcodes/ * arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl, stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of ARM_EXT_V8. (thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24Consolidate Thumb-1/Thumb-2 ISA detectionThomas Preud'homme2-3/+8
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (move_or_literal_pool): Check mov.w, mvm and movw availability against arm_ext_v6t2 instead of checking arm_arch_t2, fixing comments along the way. (handle_it_state): Check arm_ext_v6t2 instead of arm_arch_t2 to generate IT instruction. (t1_isa_t32_only_insn): New function. (md_assemble): Use above new function to check for invalid wide instruction for CPU Thumb ISA and to determine what Thumb extension bit is necessary for that instruction. (md_apply_fix): Use arm_ext_v6t2 instead of arm_arch_t2 to decide if branch is out of range. include/opcode/ * arm.h (ARM_ARCH_THUMB2): Add comment explaining its meaning and remove extension bit not including any Thumb-2 instruction.
2015-12-22Add support for ARM's NOREAD section flag.Mickael Guene3-4/+9
include/elf * arm.h: Add arm SHF_ARM_NOREAD section flag. bfd * bfd-in2.h: Regenerate. * section.c: Add SEC_ELF_NOREAD. * elf32-arm.c (elf32_arm_post_process_headers): Only set PF_X attribute if a segment only contains section with SHF_ARM_NOREAD flag. (elf32_arm_fake_sections): Add SEC_ELF_NOREAD conversion. (elf32_arm_section_flags): New function to convert SHF_ARM_NOREAD to bfd flag. (elf32_arm_lookup_section_flags): New function to allow INPUT_SECTION_FLAGS directive with SHF_ARM_NOREAD flag. (elf32_arm_special_sections): Add special sections array to catch section prefix by '.text.noread' pattern. ld/testsuite * ld-arm/arm-elf.exp: New tests. * ld-arm/thumb1-input-section-flag-match.d: New * ld-arm/thumb1-input-section-flag-match.s: New * ld-arm/thumb1-noread-not-present-mixing-two-section.d: New * ld-arm/thumb1-noread-not-present-mixing-two-section.s: New * ld-arm/thumb1-noread-present-one-section.d: New * ld-arm/thumb1-noread-present-one-section.s: New * ld-arm/thumb1-noread-present-two-section.d: New * ld-arm/thumb1-noread-present-two-section.s: New binutils * readelf.c (get_elf_section_flags): Add support for ARM specific section flags.
2015-12-17[Patch ARM] Fix build attributes for armv8-a in case of assembler files that ↵Ramana Radhakrishnan1-2/+3
contain no directives. There is currently a problem in the way in which we produce build attributes for simple assembler files that have armv8-a instructions. In these case we need to generate TAG_ISA_THUMB_Use to be Thumb-2 and set the architecture profile to be 'A' rather than not setting architecture profile to be 'A' and setting TAG_ISA_THUMB_Use to be Thumb-1. This is a pre-requisite for any v8-m patches that have been posted. arm-none-eabi gas testsuite run. no regressions. 2015-12-17 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * gas/config/tc-arm.c (aeabi_set_public_attributes): Adjust TAG_ARCH_profile for armv8-a. * gas/testsuite/gas/arm/armv8a-automatic-hlt.d: New test. * gas/testsuite/gas/arm/armv8a-automatic-hlt.s: New test. * gas/testsuite/gas/arm/armv8a-automatic-lda.d: New test. * gas/testsuite/gas/arm/armv8a-automatic-lda.s: New test.
2015-12-17Add forgotten ChangeLog updates for 72d98d16ed09584660d0cbb759d90f8dfeef2343:Christophe Lyon1-0/+4
2015-12-16 Mickael Guene <mickael.guene@st.com> bfd/ * bfd-in2.h: Regenerate. * reloc.c: Add new relocations. * libbfd.h (bfd_reloc_code_real_names): Add new relocations display names. * elf32-arm.c (elf32_arm_howto_table_1): Add HOWTO for new relocations. (elf32_arm_reloc_map): Add bfd/arm mapping for new relocations. (elf32_arm_final_link_relocate): Implement new relocations resolution. gas/ * doc/c-arm.texi: Add documentation about new directives * config/tc-arm.c (group_reloc_table): Add mapping between gas syntax and new relocations. (do_t_add_sub): Keep new relocations for add operand. (do_t_mov_cmp): Keep new relocations for mov operand. (insns): Use 'shifter operand with possible group relocation' operand parse code for movs operand. (md_apply_fix): Implement mov and add encoding when new relocations on them. (tc_gen_reloc): Add new relocations. (arm_fix_adjustable): Since offset has a limited range ([0:255]) we disable adjust_reloc_syms() for new relocations. gas/testsuite/ * gas/arm/adds-thumb1-reloc-local.d: New * gas/arm/adds-thumb1-reloc-local.s: New * gas/arm/movs-thumb1-reloc-local.d: New * gas/arm/movs-thumb1-reloc-local.s: New include/ * elf/arm.h: Add new arm relocations. ld/testsuite/ * ld-arm/arm-elf.exp (armelftests_common): Add new relocations tests. * ld-arm/thumb1-adds.d: New * ld-arm/thumb1-adds.s: New * ld-arm/thumb1-movs.d: New * ld-arm/thumb1-movs.s: New
2015-12-16[ARM] Add support for thumb1 pcrop relocations.Mickael Guene1-0/+5
To support thumb1 execute-only code we need to support four new relocations (R_ARM_THM_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G2_NC and R_ARM_THM_ALU_ABS_G3_NC). These relocations allow the static linker to finalize construction of symbol address. Typical sequence of code to get address of the symbol foo is then the following : movs r3, #:upper8_15:#foo lsls r3, #8 adds r3, #:upper0_7:#foo lsls r3, #8 adds r3, #:lower8_15:#foo lsls r3, #8 adds r3, #:lower0_7:#foo This will give following sequence of text and relocations after assembly : 4: 2300 movs r3, #0 4: R_ARM_THM_ALU_ABS_G3_NC foo 6: 021b lsls r3, r3, #8 8: 3300 adds r3, #0 8: R_ARM_THM_ALU_ABS_G2_NC foo a: 021b lsls r3, r3, #8 c: 3300 adds r3, #0 c: R_ARM_THM_ALU_ABS_G1_NC foo e: 021b lsls r3, r3, #8 10: 3300 adds r3, #0 10: R_ARM_THM_ALU_ABS_G0_NC foo
2015-12-15[ARM] Enable CRC by default for ARMv8.1 and later.Matthew Wahab2-3/+11
ARMv8.1 includes CRC as a required extension but the +crc feature isn't enabled by -march=armv8.1-a as it should be. This patch fixes that. opcode/include 2015-12-15 Matthew Wahab <matthew.wahab@arm.com> * arm.h (ARM_ARCH_V8_1A): Add the CRC_EXT_ARMV8 co-processor feature macro. (ARM_ARCH_V8_2A): Likewise. Change-Id: Id1fe0e6fa51dede19d61e1fd08e68628ea1b1e9e
2015-12-15Add support for RX V2 Instruction SetYoshinori Sato4-1/+28
binutils * readelf.c(get_machine_flags): Add v2 flag. gas * config/rx-defs.h(rx_cpu_type): Add RXV2 type. * config/tc-rx.c(cpu_type_list): New type lookup table. (md_parse_option): Use lookup table for choose cpu. (md_show_usage): Add rxv2 for mcpu option. * doc/c-rx.texi: Likewise. * config/rx-parse.y: Add v2 instructions and ACC register. (rx_check_v2): check v2 type. include/elf * rx.h(E_FLAG_RX_V2): New RXv2 type. include/opcode * rx.h: Add new instructions. opcoes * rx-deocde.opc(rx_decode_opcode): Add new instructions pattern. * rx-dis.c(register_name): Add new register. gas/testsuite * gas/rx/emaca.d: New. * gas/rx/emaca.sm: New. * gas/rx/emsba.d: New. * gas/rx/emsba.sm: New. * gas/rx/emula.d: New. * gas/rx/emula.sm: New. * gas/rx/fadd.d: Add new pattern. * gas/rx/fadd.sm: Add new pattern. * gas/rx/fmul.d: Add new pattern. * gas/rx/fmul.sm: Add new pattern. * gas/rx/fsqrt.d: New. * gas/rx/fsqrt.sm: New. * gas/rx/fsub.d: Add new pattern. * gas/rx/fsub.sm: Add new pattern. * gas/rx/ftou.d: New. * gas/rx/ftou.sm: New. * gas/rx/maclh.d: New. * gas/rx/maclh.sm: New. * gas/rx/maclo.d: Add new pattern. * gas/rx/maclo.sm: Add new pattern. * gas/rx/macros.inc: Add new register. * gas/rx/movco.d: New. * gas/rx/movco.sm: New. * gas/rx/movli.d: New. * gas/rx/movli.sm: New. * gas/rx/msbhi.d: New. * gas/rx/msbhi.sm: New. * gas/rx/msblh.d: New. * gas/rx/msblh.sm: New. * gas/rx/msblo.d: New. * gas/rx/msblo.sm: New. * gas/rx/mullh.d: New. * gas/rx/mullh.sm: New. * gas/rx/mvfacgu.d: New. * gas/rx/mvfacgu.sm: New. * gas/rx/mvfachi.d: Add new pattern. * gas/rx/mvfachi.sm: Add new pattern. * gas/rx/mvfaclo.d: Add new pattern. * gas/rx/mvfaclo.sm: Add new pattern. * gas/rx/mvfacmi.d: Add new pattern. * gas/rx/mvfacmi.sm: Add new pattern. * gas/rx/mvfc.d: Add new pattern. * gas/rx/mvtacgu.d: New. * gas/rx/mvtacgu.sm: New. * gas/rx/mvtc.d: Add new pattern. * gas/rx/popc.d: Add new pattern. * gas/rx/pushc.d: Add new pattern. * gas/rx/racl.d: New. * gas/rx/racl.sm: New. * gas/rx/racw.d: Add new pattern. * gas/rx/racw.sm: Add new pattern. * gas/rx/rdacl.d: New. * gas/rx/rdacl.sm: New. * gas/rx/rdacw.d: New. * gas/rx/rdacw.sm: New. * gas/rx/rx.exp: Add option. * gas/rx/stnz.d: Add new pattern. * gas/rx/stnz.sm: Add new pattern. * gas/rx/stz.d: Add new pattern. * gas/rx/stz.sm: Add new pattern. * gas/rx/utof.d: New. * gas/rx/utof.sm: New.
2015-12-14[AArch64][PATCH 11/14] Add support for the 2H vector type.Matthew Wahab2-0/+6
ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. The FP16 additions to the scalar pairwise group introduce a new vector type, 2H. This patch adds support for this vector type to binutils. The patch adds a new operand qualifier to the enum aarch64.h:aarch64_opnd_qualifier. This interferes with the calculation used by aarch64-dis.c:get_vreg_qualifier_from_value, called when decoding an instruction. Since the new vector type is only used in FP16 scalar pairwise instructions which do not require the function, this patch adjusts the function to ignore the new qualifier. gas/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (parse_neon_type_for_operand): Adjust to take into account new vector type 2H. (vectype_to_qualifier): Likewise. include/opcode/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (enum aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_V_2H. opcodes/ 2015-12-14 Matthew Wahab <matthew.wahab@arm.coM> * aarch64-dis.c (get_vreg_qualifier_from_value): Update comment and adjust calculation to ignore qualifier for type 2H. * aarch64-opc.c (aarch64_opnd_qualifier): Add "2H". Change-Id: Idf9a3694732962c80fde04f08c7304de9164f126
2015-12-11[AArch64][Patch 5/5] Add instruction PSB CSYNCMatthew Wahab2-0/+14
The Statistical Profile Extension adds the instruction PSB CSYNC as an alias for the HINT #17 instruction. This patch adds the instruction to binutils as a HINT alias that takes an operand. A new operand type, AARCH64_OPND_BARRIER_PSB, is added to represent the operand to PSB. A parser for the operand type is added to the assembler and a printer to the disassembler. The operand name "csync" is added to the list of HINT options with HINT number #17. Encoding and decoding of the operand is handled by the ins_hint/ext_hint functions added in the preceding patches. gas/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_hint_opt_hsh): New. (parse_barrier_psb): New. (parse_operands): Add case for AARCH64_OPND_BARRIER_PSB. (md_begin): Set up aarch64_hint_opt_hsh. gas/testsuite/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/system-2.d: Enable the statistical profiling extension. Update the expected output. * gas/aarch64/system-2.s: Add tests for PSB CSYNC. * gas/aarch64/system.d: Update the expected output. include/opcode/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. * aarch64-opc.c (aarch64_hint_options): Add "csync". (aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB. * aarch64-tbl.h (aarch64_feature_stat_profile): New. (STAT_PROFILE): New. (aarch64_opcode_table): Add "psb". (AARCH64_OPERANDS): Add "BARRIER_PSB". Change-Id: I5ffb672d26a8b15b48785478d359350a9b70ca09
2015-12-11[AArch64][Patch 4/5] Support HINT aliases taking operands.Matthew Wahab2-0/+7
The Statistical Profile Extension adds the instruction PSB CSYNC as an alias for the HINT #17 instruction. This patch adds support for aliases of HINT which take an operand, adding a table to store operand names and their matching hint number as well as encoding and decoding functions for such operands. Parsing and printing the operands are deferred to any support added for aliases with such operands. include/opcode/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_hint_options): Declare. (aarch64_opnd_info): Add field hint_option. opcodes/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm.c (aarch64_ins_hint): New. * aarch64-asm.h (aarch64_ins_hint): Declare. * aarch64-dis.c (aarch64_ext_hint): New. * aarch64-dis.h (aarch64_ext_hint): Declare. * aarch64-opc-2.c: Regenerate. * aarch64-opc.c (aarch64_hint_options): New. * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos. Change-Id: I2205038fc1c47d3025d1f0bc2fbf405b5575b287
2015-12-11[AArch64][Patch 1/5] Support the ARMv8.2 Statistical Profiling Extension.Matthew Wahab2-0/+5
The Statistical Profile extension included in the ARMv8.2 architecture adds a number of system registers and a new instruction. This patch set adds support for the extension to binutils, enabled when -march=armv8.2-a+profile is given. The patches in this series: - Add the new command line option and feature flags. - Add the new system registers. - Adjust the maximum number of aliases permitted for an instruction. - Add support for HINT aliases which take operands. - Add the new instruction, an alias of the HINT instruction. This patch adds the option "profile" to the permitted architecture extensions, disabling it by default. gas/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_features): Add "profile". * doc/c-aarch64.texi (AArch64 Extensions): Add "profile". include/opcode/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_PROFILE): New. Change-Id: If9bb4a9b69a264180f96f8ffaf10b15ced273699
2015-12-10[AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.Matthew Wahab2-0/+7
ARMv8.2 adds the new system instruction DC CVAP. This patch adds support for the instruction to binutils, enabled when -march=armv8.2-a is selected. gas/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (parse_sys_ins_reg): Add check of architectural support for system register. gas/testsuite/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/sysreg-2.d: Add tests for dc instruction. * gas/aarch64/sysreg-2.s: Add uses of dc instruction. include/opcode/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap". (aarch64_sys_ins_reg_supported_p): New. Change-Id: I3158b97d9bbee9644c2d0e2986db807412ef1053
2015-12-10[AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction.Matthew Wahab2-1/+8
ARMv8.2 adds the new system instruction DC CVAP. This patch series adds support for this instruction to binutils, enabled when -march=armv8.2-a is selected. The AArch64 binutils record of some system registers uses a boolean value to hold the single flag currently supported for them. To allow these registers to be limited to specific architectures, the first patch in this series replaces the boolean flag with a bitset and feature test. include/opcode/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags. (aarch64_sys_ins_reg_has_xt): Declare. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt with aarch64_sys_ins_reg_has_xt. (aarch64_ext_sysins_op): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): Likewise. (F_HASXT): New. (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg. (aarch64_sys_regs_dc): Likewise. (aarch64_sys_regs_at): Likewise. (aarch64_sys_regs_tlbi): Likewise. (aarch64_sys_ins_reg_has_xt): New. Change-Id: I363637a6c3f54d7ffff953b3a0734e8139cae819
2015-12-10[AArch64][PATCH 1/2] Add support for RAS instruction ESB.Matthew Wahab2-0/+7
The ARMv8.2 RAS extension adds a new barrier instruction ESB as an alias and the preferred form of HINT 16. This patch adds an architectural feature flag for the RAS extension and includes it in the features selected enabled by -march=armv8.2-a. It also adds the ESB instruction, making it available whenever the RAS feature is enabled. Because ESB is the preferred form and because the target architecture isn't available to the disassembler, HINT 16 will be disassembled as ESB even when the target has no support for the RAS extension. gas/testsuite/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/system-2.d: New. * gas/aarch64/system-2.s: New. * gas/aarch64/system.d: Adjust expected output for HINT 16. include/opcode/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_RAS): New. (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS. opcodes/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-tbl.h (aarch64_feature_ras): New. (RAS): New. (aarch64_opcode_table): Add "esb". Change-Id: Id4713917da15cca3b977284f43febd1c9b3d9faf
2015-12-10[AArch64] Fix ARMv8.1 and ARMv8.2 feature settings.Matthew Wahab2-2/+13
ARMv8.1 includes CRC as a required extension but this isn't reflected in the features enabled by -march=armv8.1-a. The FP16 feature modifier also clashes with AARCH64_FEATURE_V8_1 and the list of features for ARMv8.2 is missing ARMv8.1 features. This patch enables +crc for -march values of armv8.1-a and later. It also fixes the values for AARCH64_FEATURE_F16 and makes AARCH64_ARCH_V8_2 and superset of AARCH64_ARCH_V8_2. gas/ 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * doc/c-aarch64.texi (AArch64 Extensions): Update entry for crc. include/opcode 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_F16): Fix clash with AARCH64_FEATURE_V8_1. (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC. (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and AARCH64_FEATURE_V8_1. Change-Id: I8af5369f6df2430b28f6cec92870d2a4d14a7431
2015-12-07R_PPC64_ENTRYAlan Modra2-0/+5
Add a new relocation that marks large-model entry code, for edit back to medium-model. include/elf/ * ppc64.h (R_PPC64_ENTRY): Define. bfd/ * reloc.c (BFD_RELOC_PPC64_ENTRY): New. * elf64-ppc.c (reloc_howto_type ppc64_elf_howto_raw): Add entry for R_PPC64_ENTRY. (LD_R2_0R12, ADD_R2_R2_R12, LIS_R2, ADDIS_R2_R12): Define. (ppc64_elf_reloc_type_lookup): Handle R_PPC64_ENTRY. (ppc64_elf_relocate_section): Edit code at R_PPC64_ENTTY. Use new insn defines. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate.
2015-12-04Fix failures in the GAS testsuite for the ARC architecture.Claudiu Zissulescu2-1/+5
gas * config/tc-arc.c (arc_option): Sets all internal gas options when parsing .cpu directive. (declare_register_set): Declare all 64 registers. (md_section_align): Refactor. (md_pcrel_from_section): Remove assert. (pseudo_operand_match): Fix pseudo operand match. (find_reloc): Use flags filed, extend matching. * config/tc-arc.h (TC_VALIDATE_FIX): Don't fixup any PLT relocation. testsuite * gas/arc/bic.d: Update test. * gas/arc/add_s-err.s: New file. * gas/arc/cpu-warn1.s: Likewise. * gas/arc/pcl-relocs.d: Likewise. * gas/arc/pcl-relocs.s: Likewise. * gas/arc/pcrel-relocs.d: Likewise. * gas/arc/pcrel-relocs.s: Likewise. * gas/arc/pic-relocs.d: Likewise. * gas/arc/pic-relocs.s: Likewise. * gas/arc/plt-relocs.d: Likewise. * gas/arc/plt-relocs.s: Likewise. * gas/arc/pseudos.d: Likewise. * gas/arc/pseudos.s: Likewise. * gas/arc/sda-relocs.d: Likewise. * gas/arc/sda-relocs.s: Likewise. * gas/arc/sda-relocs2.d: Likewise. * gas/arc/sda-relocs2.s: Likewise. * gas/arc/tls-relocs.d: Likewise. * gas/arc/tls-relocs.s: Likewise. opcode * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32]. opcodes * arc-dis.c (special_flag_p): Match full mnemonic. * arc-opc.c (print_insn_arc): Check section size to read appropriate number of bytes. Fix printing. * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without arguments.
2015-12-03Darwin: add new mach-o header flags.Tristan Gingold2-1/+7
binutils/ * od-macho.c (bfd_mach_o_header_flags_name): Add name for flags until BFD_MACH_O_MH_APP_EXTENSION_SAFE. include/mach-o/ * loader.h (bfd_mach_o_header_flags): Add BFD_MACH_O_MH_APP_EXTENSION_SAFE.
2015-12-01Invoke aout N_* macros with pointer to struct internal_execAlan Modra11-53/+70
No functional changes here. BTW, some of these headers don't seem to be used anywhere: include/aout/dynix3.h, include/aout/encap.h, include/aout/hp.h, gas/config/aout_gnu.h bfd/ * aout-adobe.c: Invoke aout N_* macros with pointer to struct internal_exec. * aout-arm.c: Likewise. * aout-cris.c: Likewise. * aout-target.h: Likewise. * aout-tic30.c: Likewise. * aoutf1.h: Likewise. * aoutx.h: Likewise. * bout.c: Likewise. * freebsd.h: Likewise. * gen-aout.c: Likewise. * hp300hpux.c: Likewise. * i386aout.c: Likewise. * i386linux.c: Likewise. * i386lynx.c: Likewise. * i386mach3.c: Likewise. * i386os9k.c: Likewise. * libaout.h: Likewise. * m68klinux.c: Likewise. * m88kmach3.c: Likewise. * mipsbsd.c: Likewise. * netbsd.h: Likewise. * pc532-mach.c: Likewise. * pdp11.c: Likewise. * riscix.c: Likewise. * sparclinux.c: Likewise. * sparclynx.c: Likewise. gas/ * config/aout_gnu.h: Invoke aout N_* macros with pointer to struct internal_exec. include/ * bout.h: Invoke aout N_* macros with pointer to struct internal_exec. * os9k.h: Likewise. include/aout/ * adobe.h: Invoke aout N_* macros with pointer to struct internal_exec. * aout64.h: Likewise. * dynix3.h: Likewise. * encap.h: Likewise. * hp.h: Likewise. * hp300hpux.h: Likewise. * sun4.h: Likewise.
2015-11-28Port libvtv to SolarisRainer Orth2-0/+9
libstdc++-v3: * acinclude.m4 (GLIBCXX_ENABLE_VTABLE_VERIFY) <solaris2*>: Use -Wl,-R in VTV_CXXLINKFLAGS. * configure: Regenerate. * testsuite/18_support/bad_exception/23591_thread-1.c: Use -fvtable-verify=none on Solaris 12+. libgcc: * Makefile.in (VTV_CFLAGS): New variable. (vtv_start$(objext), vtv_end$(objext), vtv_end$(objext)) (vtv_start_preinit$(objext), vtv_end_preinit$(objext)): Use it. * config.host (*-*-solaris2*): Add t-crtstuff-pic to tmake_file. Add vtv_start.o, vtv_end.o, vtv_start_preinit.o, vtv_end_preinit.o to extra_parts if $enable_vtable_verify = yes. libvtv: * configure.tgt (*-*-solaris2.[1-9]*): Declare supported. * configure.ac: Call AC_USE_SYSTEM_EXTENSIONS. <*-*-solaris2*>: Check for init priority support. Check for getexecname, __fortify_fail, _obstack_begin. (VTV_NO_OBSTACK): New conditional. * configure: Regenerate. * Makefile.am [VTV_NO_OBSTACK] (obstack.c): Use new condition. Create empty config.h * Makefile.in: Regenerate. * vtv_rts.cc [HAVE_GETEXECNAME] (program_invocation_name): New variable. (read_section_offset_and_length) [HAVE_GETEXECNAME]: Set it. (dl_iterate_phdr_callback) [HAVE_GETEXECNAME]: Set it. (__fortify_fail): Wrap in HAVE___FORTIFY_FAIL [!HAVE___FORTIFY_FAIL]: Provide non-Cygwin implementation. (read_section_offset_and_length): Assert sh_size >= VTV_PAGE_SIZE. (iterate_modules): Fix typo. Use VTV_PAGE_SIZE. (dl_iterate_phdr_callback): Fix typo. Use VTV_PAGE_SIZE. (__VLTChangePermission): Fix typos. include: * vtv-change-permission.h (VTV_PAGE_SIZE) [__sun__ && __svr4__ && __sparc__]: Define. gcc: * config/sol2.h (SUPPORTS_INIT_PRIORITY): Move up. (STARTFILE_VTV_SPEC, ENDFILE_VTV_SPEC): Define. (STARTFILE_SPEC): Use %(startfile_vtv). (ENDFILE_SPEC): Use %(endfile_vtv). (SUBTARGET_EXTRA_SPECS): Handle STARTFILE_VTV_SPEC, ENDFILE_VTV_SPEC. * gcc.c (LINK_COMMAND_SPEC): Move VTABLE_VERIFICATION_SPEC after %{L*}. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230865 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-28SH FDPIC backend supportRich Felker2-0/+36
gcc/ChangeLog * config.gcc: Handle --enable-fdpic. * config/sh/constraints.md (Ccl): New constraint. * config/sh/linux.h (SUBTARGET_LINK_EMUL_SUFFIX): Handle -mfdpic. * config/sh/sh-c.c (sh_cpu_cpp_builtins): Add __FDPIC__ and __SH_FDPIC__. * config/sh/sh-mem.cc (expand_block_move): Support FDPIC for calls to library functions. * config/sh/sh-protos.h (function_symbol_result): New struct. (function_symbol): Return function_symbol_result. (sh_get_fdpic_reg_initial_val, sh_load_function_descriptor): New declarations. * config/sh/sh.c (TARGET_ASM_INTEGER, sh_assemble_integer): Implement target hook. (TARGET_CANNOT_FORCE_CONST_MEM, sh_cannot_force_const_mem_p): Likewise. (sh_option_override): Force -fPIC if FDPIC is in effect. (sh_asm_output_addr_const_extra): Add UNSPEC_GOTFUNCDESC and UNSPEC_GOTOFFFUNCDESC cases. (prepare_move_operands): Use FDPIC initial GOT register for TLS-related GOT access; inhibit cross-section address offset constants for FDPIC. (sh_assemble_integer): New function. (sh_cannot_copy_insn_p): Inhibit copying insns that are FDPIC PC-relative call sites. (expand_ashiftrt): Adapt invocation of function_symbol. (sh_expand_prologue): Inhibit PC-relative GOT address load for FDPIC. (nonpic_symbol_mentioned_p): Add cases for UNSPEC_GOTFUNCDESC and UNSPEC_GOTOFFFUNCDESC. (legitimize_pic_address): Resolve function symbols to function descriptors for FDPIC. Do not use GOT-relative addressing for local data that may be read-only on FDPIC. (sh_emit_storesi, sh_emit_storehi): New functions. (sh_trampoline_init): Generate FDPIC trampolines. (sh_function_ok_for_sibcall): Add TARGET_FDPIC check. (sh_expand_sym_label2reg): Don't assume sibcalls are local. (sh_output_mi_thunk): Generate FDPIC call. (function_symbol): Return function_symbol_result. For SFUNC_STATIC on FDPIC, generate call site labels to use PC-relative addressing rather than GOT-relative addressing. (sh_conditional_register_usage): Make PIC register fixed and call used when FDPIC is in effect. (sh_legitimate_constant_p): Impose FDPIC constant constraints. (sh_cannot_force_const_mem_p, sh_load_function_descriptor) (sh_get_fdpic_reg_initial_val): New functions. * config/sh/sh.h (SUBTARGET_ASM_SPEC, SUBTARGET_LINK_EMUL_SUFFIX): Handle -mfdpic. (FDPIC_SELF_SPECS, SUBTARGET_DRIVER_SELF_SPECS) (PIC_OFFSET_TABLE_REG_CALL_CLOBBERED) (SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P): New macros. (DRIVER_SELF_SPECS): Add SUBTARGET_DRIVER_SELF_SPECS and FDPIC_SELF_SPECS. (TRAMPOLINE_SIZE): Select trampoline size for FDPIC. (ASM_PREFERRED_EH_DATA_FORMAT): Add EH format constraints for FDPIC. (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): Handle FDPIC case. * config/sh/sh.md (UNSPEC_GOTFUNCDESC, UNSPEC_GOTOFFFUNCDESC): New constants. (calli_fdpic, call_valuei_fdpic, sibcalli_fdpic) (sibcalli_pcrel_fdpic, sibcall_pcrel_fdpic, sibcall_valuei_fdpic) (sibcall_valuei_pcrel_fdpic, sibcall_value_pcrel_fdpic) (sym2GOTFUNCDESC, symGOTFUNCDESC2reg, sym2GOTOFFFUNCDESC) (symGOTOFFFUNCDESC2reg): New patterns. (udivsi3_i1, udivsi3_i4, udivsi3_i4_single, udivsi3, *divsi_inv_call_combine, divsi3_i4, divsi3_i4_single, divsi3) (ashlsi3, ashlsi3_d_call, ashrsi3_n, lshrsi3, lshrsi3_d_call) (calli, call_valuei, call, call_value, sibcalli, sibcalli_pcrel) (sibcall_pcrel, sibcall, sibcall_valuei, sibcall_valuei_pcrel) (sibcall_value_pcrel, sibcall_value, GOTaddr2picreg, symGOT_load) (symGOTOFF2reg, block_move_real, block_lump_real) (block_move_real_i4, block_lump_real_i4): Add support for FDPIC calls. (mulsi3, ic_invalidate_line, initialize_trampoline, call_pop, call_value_pop): Adjust for new function_symbol signature. * config/sh/sh.opt (-mfdpic): New option. * doc/install.texi (Options specification): Document --enable-fdpic. * doc/invoke.texi (SH Options): Document -mfdpic. include/ChangeLog: * longlong.h (udiv_qrnnd): Add FDPIC compatible version for SH. libitm/ChangeLog: * config/sh/sjlj.S (_ITM_beginTransaction): Bypass PLT calling GTM_begin_transaction for compatibility with FDPIC. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@229438 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-28PR other/61321 - demangler crash on casts in template parametersPedro Alves1-0/+4
The fix for bug 59195: [C++ demangler handles conversion operator incorrectly] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=59195 unfortunately makes the demangler crash due to infinite recursion, in case of casts in template parameters. For example, with: template<int> struct A {}; template <typename Y> void function_temp(A<sizeof ((Y)(999))>) {} template void function_temp<int>(A<sizeof (int)>); The 'function_temp<int>' instantiation above mangles to: _Z13function_tempIiEv1AIXszcvT_Li999EEE The demangler parses this as: typed name template name 'function_temp' template argument list builtin type int function type builtin type void argument list template (*) name 'A' template argument list unary operator operator sizeof unary operator cast template parameter 0 (**) literal builtin type int name '999' And after the fix for 59195, due to: static void d_print_cast (struct d_print_info *dpi, int options, const struct demangle_component *dc) { ... /* For a cast operator, we need the template parameters from the enclosing template in scope for processing the type. */ if (dpi->current_template != NULL) { dpt.next = dpi->templates; dpi->templates = &dpt; dpt.template_decl = dpi->current_template; } when printing the template argument list of A (what should be "<sizeof (int)>"), the template parameter 0 (that is, "T_", the '**' above) now refers to the first parameter of the the template argument list of the 'A' template (the '*' above), exactly what we were already trying to print. This leads to infinite recursion, and stack exaustion. The template parameter 0 should actually refer to the first parameter of the 'function_temp' template. Where it reads "for the cast operator" in the comment in d_print_cast (above), it's really talking about a conversion operator, like: struct A { template <typename U> explicit operator U(); }; We don't want to inject the template parameters from the enclosing template in scope when processing a cast _expression_, only when handling a conversion operator. The problem is that DEMANGLE_COMPONENT_CAST is currently ambiguous, and means _both_ 'conversion operator' and 'cast expression'. Fix this by adding a new DEMANGLE_COMPONENT_CONVERSION component type, which does what DEMANGLE_COMPONENT_CAST does today, and making DEMANGLE_COMPONENT_CAST just simply print its component subtree. I think we could instead reuse DEMANGLE_COMPONENT_CAST and in d_print_comp_inner still do: @@ -5001,9 +5013,9 @@ d_print_comp_inner (struct d_print_info *dpi, int options, d_print_comp (dpi, options, dc->u.s_extended_operator.name); return; case DEMANGLE_COMPONENT_CAST: d_append_string (dpi, "operator "); - d_print_cast (dpi, options, dc); + d_print_conversion (dpi, options, dc); return; leaving the unary cast case below calling d_print_cast, but seems to me that spliting the component types makes it easier to reason about the code. g++'s testsuite actually generates three symbols that crash the demangler in the same way. I've added those as tests in the demangler testsuite as well. And then this fixes PR other/61233 too, which happens to be a demangler crash originally reported to GDB, at: https://sourceware.org/bugzilla/show_bug.cgi?id=16957 Bootstrapped and regtested on x86_64 Fedora 20. Also ran this through GDB's testsuite. GDB will require a small update to use DEMANGLE_COMPONENT_CONVERSION in one place it's using DEMANGLE_COMPONENT_CAST in its sources. libiberty/ 2015-11-27 Pedro Alves <palves@redhat.com> PR other/61321 PR other/61233 * demangle.h (enum demangle_component_type) <DEMANGLE_COMPONENT_CONVERSION>: New value. * cp-demangle.c (d_demangle_callback, d_make_comp): Handle DEMANGLE_COMPONENT_CONVERSION. (is_ctor_dtor_or_conversion): Handle DEMANGLE_COMPONENT_CONVERSION instead of DEMANGLE_COMPONENT_CAST. (d_operator_name): Return a DEMANGLE_COMPONENT_CONVERSION component if handling a conversion. (d_count_templates_scopes, d_print_comp_inner): Handle DEMANGLE_COMPONENT_CONVERSION. (d_print_comp_inner): Handle DEMANGLE_COMPONENT_CONVERSION instead of DEMANGLE_COMPONENT_CAST. (d_print_cast): Rename as ... (d_print_conversion): ... this. Adjust comments. (d_print_cast): Rewrite - simply print the left subcomponent. * cp-demint.c (cplus_demangle_fill_component): Handle DEMANGLE_COMPONENT_CONVERSION. * testsuite/demangle-expected: Add tests. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@231020 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-28Fix PR63758 by using the _NSGetEnviron() API on DarwinIain Sandoe2-0/+38
include/ Roland McGrath <roland@gnu.org> PR other/63758 * environ.h: New file. libiberty/ Roland McGrath <roland@gnu.org> Iain Sandoe <iain@codesourcery.com> PR other/63758 * pex-unix.c: Obtain the environment interface from settings in environ.h rather than in-line code. Update copyright date. * setenv.c: Likewise. * xmalloc.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228942 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-28Implement N4514, C++ Extensions for Transactional Memory.Jason Merrill1-0/+2
gcc/ * builtins.def (BUILT_IN_ABORT): Add transaction_pure attribute. gcc/c-family/ * c-common.c (c_common_reswords): Add C++ TM TS keywords. (c_common_attribute_table): Add transaction_safe_dynamic. transaction_safe now affects type identity. (handle_tm_attribute): Handle transaction_safe_dynamic. * c-common.h (enum rid): Add RID_ATOMIC_NOEXCEPT, RID_ATOMIC_CANCEL, RID_SYNCHRONIZED. (OBJC_IS_CXX_KEYWORD): Add RID_SYNCHRONIZED. (D_TRANSMEM): New. * c-cppbuiltin.c (c_cpp_builtins): Define __cpp_transactional_memory. * c-pretty-print.c (pp_c_attributes_display): Don't print transaction_safe in C++. gcc/c/ * c-parser.c (c_lex_one_token): Handle @synchronized. * c-decl.c (match_builtin_function_types): A declaration of a built-in can change whether the function is transaction_safe. gcc/cp/ * cp-tree.h (struct cp_declarator): Add tx_qualifier field. (BCS_NORMAL, BCS_TRANSACTION): New enumerators. * lex.c (init_reswords): Limit TM kewords to -fgnu-tm. * parser.c (cp_lexer_get_preprocessor_token): Fix @synchronized. (make_call_declarator): Take tx_qualifier. (cp_parser_tx_qualifier_opt): New. (cp_parser_lambda_declarator_opt): Use it. (cp_parser_direct_declarator): Likewise. (cp_parser_statement): Handle atomic_noexcept, atomic_cancel. (cp_parser_compound_statement): Change in_try parameter to bcs_flags. (cp_parser_std_attribute): Map optimize_for_synchronized to transaction_callable. (cp_parser_transaction): Take the token. Handle atomic_noexcept. * lambda.c (maybe_add_lambda_conv_op): Handle transaction-safety. * call.c (enum conversion_kind): Add ck_tsafe. (standard_conversion): Handle transaction-safety conversion. (convert_like_real, resolve_address_of_overloaded_function): Likewise. (check_methods): Diagnose transaction_safe_dynamic on non-virtual function. (look_for_tm_attr_overrides): Don't inherit transaction_safe_dynamic. * cvt.c (tx_safe_fn_type_p, tx_unsafe_fn_variant) (can_convert_tx_safety): New. * typeck.c (composite_pointer_type): Handle transaction-safety. * name-lookup.h (enum scope_kind): Add sk_transaction. * name-lookup.c (begin_scope): Handle it. * semantics.c (begin_compound_stmt): Pass it. * decl.c (check_previous_goto_1): Check it. (struct named_label_entry): Add in_transaction_scope. (poplevel_named_label_1): Set it. (check_goto): Check it. (duplicate_decls): A specialization can be transaction_safe independently of its template. (grokdeclarator): Handle tx-qualifier. * rtti.c (ptr_initializer): Handle transaction-safe. * search.c (check_final_overrider): Check transaction_safe_dynamic. Don't check transaction_safe. * mangle.c (write_function_type): Mangle transaction_safe here. (write_CV_qualifiers_for_type): Not here. (write_type): Preserve transaction_safe when stripping attributes. * error.c (dump_type_suffix): Print transaction_safe. libiberty/ * cp-demangle.c (d_cv_qualifiers): Dx means transaction_safe. (cplus_demangle_type): Let d_cv_qualifiers handle it. (d_dump, d_make_comp, has_return_type, d_encoding) (d_count_templates_scopes, d_print_comp_inner) (d_print_mod_list, d_print_mod, d_print_function_type) (is_ctor_or_dtor): Handle DEMANGLE_COMPONENT_TRANSACTION_SAFE. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228462 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-27[AArch64] Add ARMv8.2 instructions BFC and REV64.Matthew Wahab2-0/+5
ARMv8.2 adds two new instructions: BFC as an alias for BFM and REV64 as an alias for REV. This patch set adds support for these to binutils, enabled when the -march=armv8.2-a is given. It depends on the support for an instruction being its preferred form which was added in an earlier patch. This patch adds the alias BFC <Rd>, #<imm>, #<width> as the preferred form for BFM when the source is a zero register and the conditions for using the BFI form are met (in other words, BFC is the preferred form for BFI <Rd>, <Rs>, #<imm>, #<width> when the <Rs> is a zero register). gas/testsuite/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/alias-2.d: New. * gas/aarch64/alias-2.s: New. include/opcode/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_op): Add OP_BFC. opcodes/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. * aarch64-asm.c (convert_bfc_to_bfm): New. (convert_to_real): Add case for OP_BFC. * aarch64-dis-2.c: Regenerate. * aarch64-dis.c: (convert_bfm_to_bfc): New. (convert_to_alias): Add case for OP_BFC. * aarch64-opc-2.c: Regenerate. * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert to allow width operand in three-operand instructions. * aarch64-tbl.h (QL_BF1): New. (aarch64_feature_v8_2): New. (ARMV8_2): New. (aarch64_opcode_table): Add "bfc". Change-Id: I6efe318b2538ba11f0caece7c6d70957441c872b
2015-11-27[AArch64] Add feature flags and command line for ARMv8.2 FP16 support.Matthew Wahab2-0/+8
ARMv8.2 adds optional support for 16-bit operations to the FP and Adv.SIMD instructions. This patch adds a feature macro for this support with a new command line option "+fp16" to enable/disable it. Although the command line option is added as an architecture extension, it only affects instructions available with when +fp or +simd is enabled. If +fp16 is specified then it will also enable +fp. There are currently no FP16 instructions implemented in binutils, this patch is to enable subsequent work on supporting the extension. gas/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_features): Add "fp16". * doc/c-aarch64.texi (Architecture Extensions): Add "fp16". include/opcode/ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_F16): New. (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2 features. Change-Id: Id2021e0513946e16d0935c2a5b9605574cdff95a
2015-11-24Add an AArch64 simulator to GDB.Nick Clifton2-0/+52
sim * configure.tgt: Add aarch64 entry. * configure: Regenerate. * sim/aarch64/configure.ac: New configure template. * sim/aarch64/aclocal.m4: Generate. * sim/aarch64/config.in: Generate. * sim/aarch64/configure: Generate. * sim/aarch64/cpustate.c: New file - functions for accessing AArch64 registers. * sim/aarch64/cpustate.h: New header. * sim/aarch64/decode.h: New header. * sim/aarch64/interp.c: New file - interface between GDB and simulator. * sim/aarch64/Makefile.in: New makefile template. * sim/aarch64/memory.c: New file - functions for simulating aarch64 memory accesses. * sim/aarch64/memory.h: New header. * sim/aarch64/sim-main.h: New header. * sim/aarch64/simulator.c: New file - aarch64 simulator functions. * sim/aarch64/simulator.h: New header. include/gdb * sim-aarch64.h: New file. sim/test * configure: Regenerate. * sim/aarch64: New directory.
2015-11-20[AArch64] Add support for ARMv8.1 Virtulization Host Extensions.Matthew Wahab2-0/+7
The ARMv8.1 architecture includes the Virtualization Host Extensions which add a number of system registers. This patch adds support for these system registers, making them available when -march=armv8.1-a is selected. include/opcode/ 2015-11-20 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_V8_1): New. (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1. opcodes/ 2015-11-20 Matthew Wahab <matthew.wahab@arm.com> * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12, sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12, tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12, amair_el12, vbar_el12, contextidr_el2, contextidr_el12, cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02, cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2, cnthv_ctl_el2, cnthv_cval_el2. (aarch64_sys_reg_supported_p): Update for the new system registers. gas/testsuite/ 2015-11-20 Matthew Wahab <matthew.wahab@arm.com> * gas/aarch64/virthostext-directive.d: New. * gas/aarch64/virthostext.d: New. * gas/aarch64/virthostext.s: New. Change-Id: Iecb370591b1b6e9e00d81c8ccd9ae3b0f71794a2
2015-11-19[ARM] Add ARMv8.2 architecture feature and command line option.Matthew Wahab2-0/+8
ARMv8.2 is an architectural extension of ARMv8. This patch adds an architecture feature macro for ARMv8.2 to the binutils ARM target with GAS command line option -march=armv8.2-a. gas/ 2015-11-19 Matthew Wahab <matthew.wahab@arm.com> * config/tc-arm.c (arm_archs): Add "armv8.2-a". * doc/c-arm.texi (-march): Add "armv8.2-a". include/opcode/ 2015-11-19 Matthew Wahab <matthew.wahab@arm.com> * arm.h (ARM_EXT2_V8_2A): New. (ARM_ARCH_V8_2A): New. Change-Id: I9e0f50e3c6cea24e6b87b8b862fd4e1cdcc1052e
2015-11-19[AArch64] Add ARMv8.2 command line option and feature flag.Matthew Wahab2-1/+14
ARMv8.2 is an architectural extension of ARMv8. This patch adds an architecture feature macro for ARMv8.2 to the binutils AArch64 target with GAS command line option -march=armv8.2-a. gas/ 2015-11-19 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_archs): Add "armv8.2-a". * doc/c-aarch64.texi (-march): Likewise. include/opcode/ 2015-11-19 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (AARCH64_FEATURE_V8_2): New. (AARCH64_ARCH_V8_2): New. Change-Id: I129232ab00234a07d18ce4b619607344acb3cbaf
2015-11-17Mach-O: add new defines and struct for darwin 14.5Tristan Gingold5-2/+158
include/mach-o/ * arm64.h: New file. * unwind.h: Add arm64 encodings. * loader.h (bfd_mach_o_cpu_subtype): Add arm64 literals. (BFD_MACH_O_LC_ENCRYPTION_INFO_64, BFD_MACH_O_LC_LINKER_OPTIONS) (BFD_MACH_O_LC_LINKER_OPTIMIZATION_HINT) (BFD_MACH_O_LC_VERSION_MIN_WATCHOS): Define. * external.h (mach_o_encryption_info_64_command_external): (mach_o_linker_option_command_external) (mach_o_dyld_cache_header_external) (mach_o_dyld_cache_mapping_info_external) (mach_o_dyld_cache_image_info_external): New types.
2015-11-15sim: cr16: convert to common sim memory modulesMike Frysinger2-9/+6
The cr16 port has a lot of translation/offset logic baked into it, but it all looks like copy & paste from the d10v port rather than something the cr16 port wants.
2015-11-15sim: drop extern C linkage from most sim interface headersMike Frysinger8-59/+9
Since these headers merely have enum's, drop the extern C linkage markings. Helps to reduce the copy & paste spam.
2015-11-11Add assembler, disassembler and linker support for power9.Peter Bergner5-0/+25
include/opcode/ * ppc.h (PPC_OPCODE_POWER9): New define. (PPC_OPCODE_VSX3): Likewise. opcodes/ * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries. Add PPC_OPCODE_VSX3 to the vsx entry. (powerpc_init_dialect): Set default dialect to power9. * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1, extract_l1 insert_xtq6, extract_xtq6): New static functions. (insert_esync): Test for illegal L operand value. (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6, XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA, XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK, XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3, PPCVSX3): New defines. (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu, fcmpo, ftdiv, ftsqrt>: Use XBF_MASK. <mcrxr>: Use XBFRARB_MASK. <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq., bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc., cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first, cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx, lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll, lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw, modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last, rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx, stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx, subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh, vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh., vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd, vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d, vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx, vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq, vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd, vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait, xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp, xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp, xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz, xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp, xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp, xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo, xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo, xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo, xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp, xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp, xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp, xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw, xxinsertw, xxperm, xxpermr, xxspltib>: New instructions. <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9. <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands. include/elf/ * ppc.h (R_PPC_REL16DX_HA): New reloction. * ppc64.h (R_PPC64_REL16DX_HA): Likewise. bfd/ * elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_REL16DX_HA. (ppc_elf_reloc_type_lookup): Handle R_PPC_REL16DX_HA. (ppc_elf_addr16_ha_reloc): Likewise. (ppc_elf_check_relocs): Likewise. (ppc_elf_relocate_section): Likewise. (is_insn_dq_form): Handle lxv and stxv instructions. * elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_REL16DX_HA. (ppc64_elf_reloc_type_lookup): Handle R_PPC64_REL16DX_HA. (ppc64_elf_ha_reloc): Likewise. (ppc64_elf_check_relocs): Likewise. (ppc64_elf_relocate_section): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. * reloc.c (BFD_RELOC_PPC_REL16DX_HA): New. elfcpp/ * powerpc.h (R_POWERPC_REL16DX_HA): Define. gas/ * doc/as.texinfo (Target PowerPC): Document -mpower9 and -mpwr9. * doc/c-ppc.texi (PowerPC-Opts): Likewise. * config/tc-ppc.c (md_show_usage): Likewise. (md_assemble): Handle BFD_RELOC_PPC_REL16DX_HA. (md_apply_fix): Likewise. (ppc_handle_align): Handle power9's group ending nop. gas/testsuite/ * gas/ppc/altivec3.s: New test. * gas/ppc/altivec3.d: Likewise. * gas/ppc/vsx3.s: Likewise. * gas/ppc/vsx3.d: Likewise. * gas/ppc/power9.s: Likewise. * gas/ppc/power9.d: Likewise. * gas/ppc/ppc.exp: Run them. * gas/ppc/power8.s <lxvx, lxvd2x, stxvx, stxvd2x>: Add new tests. * gas/ppc/power8.d: Likewise. * gas/ppc/vsx.s: <lxvx, stxvx>: Rename invalid mnemonics ... <lxvd2x, stxvd2x>: ...to this. * gas/ppc/vsx.d: Likewise. gold/ * gold/powerpc.cc (Powerpc_relocate_functions::addr16_dq): New function. (Powerpc_relocate_functions::addr16dx_ha): Likewise. (Target_powerpc::Scan::local): Handle R_POWERPC_REL16DX_HA. (Target_powerpc::Scan::global): Likewise. (Target_powerpc::Relocate::relocate): Likewise. ld/testsuite/ * ld-powerpc/addpcis.d: New test. * ld-powerpc/addpcis.s: New test. * ld-powerpc/powerpc.exp: Run it.
2015-11-10sim: cr16/d10v: localize translation funcsMike Frysinger3-46/+9
These functions are only used in the interp module, so there's no point in exporting them and declaring them in the external sim interface.
2015-11-09Modify obstack.[hc] to avoid having to include other gnulib filesAlan Modra2-1/+10
Using the standard gnulib obstack source requires importing quite a lot of other files from gnulib, and requires build changes. include/ PR gdb/17133 * obstack.h (__attribute_pure__): Expand _GL_ATTRIBUTE_PURE. libiberty/ PR gdb/17133 * obstack.c (__alignof__): Expand alignof_type from alignof.h. (obstack_exit_failure): Don't use exitfail.h. (_): Include libintl.h when HAVE_LIBINTL_H and nls enabled. Provide default. Don't include gettext.h. (_Noreturn): Define. * obstacks.texi: Adjust node references to external libc info files.
2015-11-09Copy gnulib obstack filesAlan Modra2-461/+454
This copies obstack.[ch] from gnulib, and updates the docs. The next patch should be applied if someone repeats the import at a later date. include/ PR gdb/17133 * obstack.h: Import current gnulib file. libiberty/ PR gdb/17133 * obstack.c: Import current gnulib file. * obstacks.texi: Updated doc, from glibc's manual/memory.texi.
2015-11-02Disassemble RX NOP instructions as such.Nick Clifton2-0/+8
opcode * rx.h (enum RX_Opcode_ID): Add more NOP opcodes. opcodes * rx-decode.opc (rx_decode_opcode): Decode extra NOP instructions. * rx-decode.c: Regenerate. tests * gas/rx/max.d: Update expecetd disassembly. * gas/rx/nod.d: Likewise. * gas/rx/nop.sm: Add tests of more NOP instructions.
2015-11-02Fix disassembly of RX zero-offset register indirect instructions.Nick Clifton2-0/+5
opcode * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect. opcodes * rx-decode.opc (rx_disp): If the displacement is zero, set the type to RX_Operand_Zero_Indirect. * rx-decode.c: Regenerate. * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect. gas * config/rx-parse.y: Allow zero value for 5-bit displacements. tests * gas/rx/mov.sm: Add tests for zero offset indirect moves. * gas/rx/mov.d: Update expected output.
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