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CHERI/Morello defines some new auxv entries. Make sure gdb understands
their type, even though gdb doesn't know how to display the capabilities
themselves.
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While the concept of a core instruction relates to the idea of
instructions that are available irrespective of the presence of
architectural extensions, this concept breaks down with the
introduction of the Morello architecture.
Rather, what is observed in Morello is that when PSTATE.C64 == 1,
the A64C_INSN variant becomes the ONLY valid aarch64_opcode variant,
with the CORE_INSN variant becoming illegal. Therefore, some way of
ruling out the use of such CORE_INSNs is needed.
Similarly, some A64C_INSN instructions are only valid for
PSTATE.C64 == 1 and are not valid when compiling for Morello A64
mode.
At the assembly level, the CORE_INSN and A64C_INSN variants share the
same mnemonic, differing only by whether they are passed a general-
purpose register argument or its capability counterpart, e.g.
* CORE_INSN: adr x0, #0
* A64C_INSN: adr c0, #0
This makes the prospect of combining both insn variants in binutils
into a single insn entry in aarch64_opcode_table[], resolving the
appropriate operand code (e.g. AARCH64_OPND_Can versus
AARCH64_OPND_Rn) at compile time by analyzing the -march and -mabi
flags.
This approach falls short when dealing with instructions such as `bl'
where the core and morello instructions share the same mnemonic but
have distinct encodings.
A more flexible approach is therefore presented here. Special
restrictions to instructions are encoded in the FLAGS field, which
can then be used in checks carried out in `md_assemble'.
This fixes two issues:
1. Wrong fix suggestions in `output_operand_error_record':
- attempting to assemble `adr w0, #0' at present, for example,
results in a suggestion that `w0' be changed to `x0' as opposed
to `c0'.
2. Purecap only instructions being accepted when assembling without
the C64 extension:
- `adr c0, #0' is currently accepted when assembling for
Hybrid mode.
This patch defines the F_NONC64 and F_C64ONLY flags for labellig these
instructions in aarch64_opcode.flags, such that unavailable instructions
could be identified by cross-referencing this field along with whether
C64 is set in the `cpu_variant' aarch64_feature_set variable. When
the conditions set by the flag is not met by `cpu_variant', the
instruction can be attributed a AARCH64_OPDE_SYNTAX_ERROR, allowing
for correct error handling in md_assemble.
ChangeLog:
* include/opcode/aarch64.h (F_NONC64): New flag.
* include/opcode/aarch64.h (F_C64ONLY): Likewise.
opcodes/ChangeLog:
* aarch64-tbl.h (aarch64_opcode_table): Add F_NONC64 and F_C64ONLY
to relevant aarch64_opcodes
gas/ChangeLog:
* config/tc-aarch64.c (validate_opcode_for_feature): New.
(md_assemble): Use `validate_opcode_for_feature' in template
selection.
* gas/testsuite/gas/aarch64/morello-exclude.l: New testcase.
* gas/testsuite/gas/aarch64/morello-exclude.s: Likewise.
* gas/testsuite/gas/aarch64/morello-exclude.l: Likewise.
* gas/testsuite/gas/aarch64/morello_insn.s: Fix hybrid codegen.
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The calculation of OBJALLOC_ALIGN in include/objalloc.h ensures that
allocations are sufficiently aligned for doubles, but on CHERI
architectures it is possible that void * has a greater alignment
requirement than double.
Instead of deriving the alignment requirement from double alone, this
patch uses a union to compute the maximum alignment between double and
void *.
This fixes alignment faults seen when compiling the binutils for
pure-capability Morello. With this patch applied, the majority of
binutils tests pass when the binutils themselves are compiled for
purecap.
This patch is a backport of commit
a8af417a8a1559a3ebceb0c761cf26ebce5eab7f, initially upstreamed to
Morello GCC.
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Also add the ability to disassemble these relocations correctly.
Include checking that many different sizes work with different
instructions, include error checking that the `size` relocation is not
allowed in a64 mode. Ensure that the size relocation is not allowed on
instructions other than mov[kz].
See the arm ABI aaelf64-morello document for the definition of these
new relocations.
Regenerate bfd/bfd-in2.h and bfd/libbfd.h from bfd/reloc.c.
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The alt-base loads and stores allow WZR and XZR to be specified
as the register being loaded or stored. We were accepting the
XZR forms but not the WZR ones.
The easiest fix is to drop the separate Wt operand type. Most
other instructions handle the W/X distinction using the qualifiers
instead, and all instructions that used Wt already specified W
qualifiers.
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Many load instructions have two forms: LDR<x> that takes either:
- a register index or
- an unsigned scaled immediate offset
and LDUR<x> that takes:
- a signed unscaled immediate offset in the range [-256, 255]
The assembler usually maps out-of-range LDR<x> offsets to LDUR<x>
where possible. GAS does this using matching OP_* codes; see
try_to_encode_as_unscaled_ldst in gas/config/tc-aarch64.c.
Some alternative-base Morello instructions also come in these
LDR/LDUR pairs, so we can use the same approach for them.
However, the alternative-base forms of LDRS[BHW] only support a
register index. They do not have a register+unsigned scaled form.
There is therefore no OP_* pair linking alternative-base LDRS[BHW]
and LDURS[BHW] instructions.
This patch therefore treats immediate LDRS[BHW] as a straight alias
of LDURS[BHW]. Following existing practice, LDURS[BHW] is still the
preferred disassembly, so the patch uses F_P1 to force LDURS[BHW] to
be chosen ahead of LDRS[BHW].
Following the general preference for using immediate forms where
possible:
ldrsb x0, [c0]
is treated as:
ldursb x0, [c0, #0]
rather than:
ldrsb x0, [c0, xzr]
Co-Authored-By: Stam Markianos-Wright <stam.markianos-wright@arm.com>
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As it stands, the architecture feature bits for Morello include FP16FML
(i.e. ARMv8.2-FHM) but not FP16: this is an invalid combination.
Looking at the Morello Arm ARM [1], it seems that Morello wants the
feature FP16 (ARMv8.2-FP16) but not FP16FML.
[1] : https://developer.arm.com/documentation/ddi0606/latest
include/ChangeLog:
2021-09-10 Alex Coplan <alex.coplan@arm.com>
* opcode/aarch64.h (AARCH64_ARCH_MORELLO): Change F16_FML
feature bit to F16.
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Morello GDB used to rely on the presence of the __cap_relocs section to
identify a ELF file that followed the pure-cap ABI. This isn't reliable
anymore.
Instead, we check two types of information. One of them is the e_flags, which
contains a bit identifying the pure-cap ABI. The second one is the LSB of the
e_entry, which is set for a pure-cap ABI ELF.
gdb/ChangeLog:
2021-06-24 Luis Machado <luis.machado@arm.com>
* aarch64-tdep.c: Include elf/aarch64.h.
(aarch64_bfd_has_capabilities): Make more robust.
(aarch64_gdbarch_init): Set have_capability if we have a pure-cap
ABI marker.
include/ChangeLog:
2021-06-24 Luis Machado <luis.machado@arm.com>
* elf/aarch64.h (EF_AARCH64_CHERI_PURECAP): New constant.
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Enable core file dumping through the gcore command and enable reading of
kernel-generated core files for Morello.
This patch enables writing and reading Morello core file containing dumps
of the C register set and dumps of the capability tags from memory.
The C register dumps are stored in a NT_ARM_MORELLO note, while the capability
tag dumps are stored into multiple NT_MEMTAG notes.
The NT_MEMTAG notes have the following format:
NT_MEMTAG:
<header>
<tag data>
The header has the following format:
/* Header for NT_MEMTAG notes. */
struct __attribute__ ((packed)) tag_dump_header
{
uint16_t format;
uint64_t start_vma;
uint64_t end_vma;
union
{
struct tag_dump_fmt
{
uint16_t granule_byte_size;
uint16_t tag_bit_size;
uint16_t __unused;
} cheri;
} u;
// Other formats may be added here later.
};
There is a speed limitation while saving capability tags. That's because GDB
only has access to one capability per-ptrace call. In the future there may be
a ptrace request to read capability tags in bulk, which will make things much
faster.
Tested by writing a gcore-based core file and reading it back, and also
exercised by reading a kernel-generated core file.
bfd/ChangeLog:
2021-05-24 Luis Machado <luis.machado@arm.com>
* elf-bfd.h (elfcore_write_aarch_morello): New prototype.
* elf.c (elfcore_grok_aarch_morello): New function.
(elfcore_grok_note): Handle NT_ARM_MORELLO.
(elfcore_write_aarch_morello): New function.
(elfcore_write_register_note): Handle reg-aarch-morello.
(elfcore_make_memtag_note_section): New function.
(elfcore_grok_note): Handle NT_MEMTAG note types.
binutils/ChangeLog:
2021-05-24 Luis Machado <luis.machado@linaro.org>
* readelf.c (get_note_type): Handle NT_MEMTAG note types.
include/ChangeLog:
2021-05-24 Luis Machado <luis.machado@linaro.org>
* elf/common.h (NT_MEMTAG): New constant.
(ELF_CORE_TAG_CHERI): New constant.
gdb/ChangeLog:
2021-05-24 Luis Machado <luis.machado@arm.com>
* aarch64-linux-tdep.c (aarch64_linux_cregmap): Update to match
Morello's register layout in the core file.
(aarch64_linux_iterate_over_regset_sections): Update to handle
Morello's register set.
(aarch64_linux_init_abi): Likewise.
Register core file hooks.
(aarch64_linux_decode_memtag_note)
(aarch64_linux_create_memtag_notes_from_range)
(morello_get_tag_granules): New functions.
(MAX_TAGS_TO_TRANSFER): New constant.
* arch/aarch64-cap-linux.h (MORELLO_TAG_GRANULE_SIZE)
(MORELLO_TAG_BIT_SIZE): New constants.
(tag_dump_header): New struct.
* corelow.c (core_target <read_capability>: New method overrides.
(core_target::read_capability): New methods.
* gdbarch.sh (create_memtag_notes_from_range)
(decode_memtag_note): New hooks.
* gdbarch.c: Regenerate.
* gdbarch.h: Regenerate.
* linux-tdep.c (linux_make_memtag_corefile_notes): New function.
(linux_make_corefile_notes): Call linux_make_memtag_corefile_notes.
(linux_address_in_memtag_page): Removed.
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Disassembling of C64 instructions in GDB does not work correctly. It needs
to pass the proper information to opcodes.
This patch accomplishes that.
gdb/ChangeLog:
2021-03-17 Luis Machado <luis.machado@arm.com>
* aarch64-tdep.c (aarch64_find_mapping_symbol, aarch64_pc_is_c64): New
functions.
(aarch64_gdb_print_insn): Pass map type to disassembler.
include/ChangeLog:
2021-03-17 Luis Machado <luis.machado@arm.com>
* opcode/aarch64.h (enum map_type): Moved from opcodes/aarch64-dis.c.
Renamed fields.
(struct aarch64_private_data): New struct.
opcodes/ChangeLog:
2021-03-17 Luis Machado <luis.machado@arm.com>
* aarch64-dis.c (enum map_type): Moved to include/opcode/aarch64.h.
(MAYBE_C64): Adjust.
(get_sym_code_type): Adjust.
(print_insn_aarch64): Use private data when available.
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This patch adds capability register set support to both GDB and GDBserver,
allowing the use of ptrace.
gdb/ChangeLog
2020-10-20 Luis Machado <luis.machado@arm.com>
* aarch64-linux-nat.c: Include arch/aarch64-cap-linux.h.
(fetch_cregs_from_thread)
(store_cregs_to_thread): New functions.
(aarch64_linux_nat_target::fetch_registers): Modify to check for
capability registers.
* aarch64-linux-tdep.c: Include arch/aarch64-cap-linux.h.
* aarch64-tdep.c (aarch64_cannot_store_register): Check for capability
registers.
(aarch64_gdbarch_init): Also save the last capability register number.
* aarch64-tdep.h (struct gdbarch_tdep) <cap_reg_last>: New field.
* arch/aarch64-cap-linux.h (AARCH64_LINUX_CREGS_SIZE,
AARCH64_MORELLO_REGS_NUM, AARCH64_C_REGS_NUM): New constants.
* arch/aarch64.c: Remove FIXME comment.
* nat/aarch64-linux.h (user_morello_state): New struct.
gdbserver/ChangeLog
2020-10-20 Luis Machado <luis.machado@arm.com>
* linux-aarch64-low.c: arch/aarch64-cap-linux.h.
(aarch64_store_cregset): New function.
(aarch64_regsets): Add capability register set.
(aarch64_sve_regsets): Likewise.
include/ChangeLog
2020-10-20 Luis Machado <luis.machado@arm.com>
* elf/common.h (NT_ARM_MORELLO): Define.
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This patch adds some new definitions required for Morello.
* DWARF base types: DW_ATE_CHERI_signed_intcap and DW_ATE_CHERI_unsigned_intcap.
* DWARF address class: DW_ADDR_capability
* DWARF register numbering
It also adds support for handling DW_ATE_CHERI_signed_intcap and
DW_ATE_CHERI_unsigned_intcap on binutils and GDB.
binutils/ChangeLog
2020-10-20 Luis Machado <luis.machado@arm.com>
* dwarf.c (get_type_signedness): Handles capabilities.
(read_and_display_attr_value): Likewise.
gdb/ChangeLog:
2020-10-20 Luis Machado <luis.machado@arm.com>
* aarch64-tdep.h (AARCH64_DWARF_C0, AARCH64_DWARF_CSP)
(AARCH64_DWARF_PCC, AARCH64_DWARF_DDC)
(AARCH64_DWARF_RESERVED_1, AARCH64_DWARF_RESERVED_2)
(C_REGISTER_SIZE): New defines.
* dwarf2/read.c (read_base_type): Handle capabilities.
include/ChangeLog
2020-10-20 Luis Machado <luis.machado@arm.com>
* dwarf2.def (DW_ATE_CHERI_signed_intcap)
(DW_ATE_CHERI_unsigned_intcap): New defines.
* dwarf2.h (DW_ADDR_capability): New define.
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This change adds basic support for TLS descriptors. Relaxation of
TLSDESC_GD to other relocations is limited to TLS_LE, other cases end
up retaining TLSDESC_GD.
There is one key difference from A64 for TLSDESC_GD -> LE transition
and that is in the case of static non-pie binaries. Morello
TLSDESC_GD relocations are relaxed to LE for static non-pie binaries
since it ought to be safe to do so and it aligns with llvm behaviour.
bfd/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* elfnn-aarch64.c (IS_AARCH64_TLSDESC_RELOC): Add Morello
relocations.
(elfNN_aarch64_tlsdesc_small_plt_c64_entry): New Morello
tlsdesc PLT entry.
(elfNN_aarch64_howto_table): Add TLSDESC_ADR_PAGE20,
TLSDESC_LD128_LO12, TLSDESC_CALL, TLSDESC relocations for
Morello.
(aarch64_tls_transition_without_check): Add INFO and
MORELLO_RELOC arguments. Add morello TLSDESC relocations.
(aarch64_reloc_got_type, elfNN_aarch64_final_link_relocate,
elfNN_aarch64_tls_relax, elfNN_aarch64_check_relocs,
aarch64_can_relax_tls): Add morello TLSDESC relocations.
(aarch64_tls_transition): Add transitions for morello TLSDESC
relocations.
(elfNN_aarch64_tls_relax): Add relaxations for morello
TLSDESC.
(elfNN_aarch64_relocate_section): Emit dynamic relocation for
Morello static relocations.
(elfNN_aarch64_allocate_dynrelocs): Allocate dynamic
relocation space for Morello TLSDESC.
(elfNN_aarch64_finish_dynamic_sections): Emit Morello tlsdesc
PLT entry.
* elfxx-aarch64.c (_bfd_aarch64_elf_put_addend,
_bfd_aarch64_elf_resolve_relocation): Add Morello relocations.
* reloc.c: Add Morello relocations.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (s_tlsdesccall): Emit Morello
TLSDESC_CALL in C64 code.
(reloc_table): Add Morello relocation.
(md_apply_fix): Emit Morello TLSDESC_LD128_LO12 in C64 code.
(aarch64_force_relocation): Add Morello TLSDESC relocations.
* testsuite/gas/aarch64/morello-tlsdesc-c64.d: New file.
* testsuite/gas/aarch64/morello-tlsdesc.d: New file.
* testsuite/gas/aarch64/morello-tlsdesc.s: New file.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* elf/aarch64.h: New Morello TLSDESC relocations.
ld/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* testsuite/ld-aarch64/morello-tlsdesc.s: New file.
* testsuite/ld-aarch64/morello-tlsdesc.d: New test.
* testsuite/ld-aarch64/morello-tlsdesc-static.d: New test.
* testsuite/ld-aarch64/morello-tlsdesc-staticpie.d: New test.
* testsuite/ld-aarch64/aarch64-elf.exp: Add them.
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This implements the following static relocations:
- R_MORELLO_CALL26, R_MORELLO_JUMP26
- R_MORELLO_TSTBR14, R_MORELLO_CONDBR19
and the following dynamic relocations:
- R_MORELLO_JUMP_SLOT and R_MORELLO_IRELATIVE
Some notes on the implementation:
- The linker selects morello PLT stubs when it finds at least one
static relocation that needs a capability GOT slot.
- It is assumed that C64 is not compatible with BTI/PAC, so the latter
gets overridden. To allow this, the call to setup_plt_values is
delayed to take into account htab->c64_plt.
- If the caller is A64, the assembler emits R_AARCH64_JUMP_SLOT,
otherwise it emits R_MORELLO_JUMP_SLOT.
- The PLT stub is A64-compatible, in that it should do the right thing
when the execution state is A64.
- If the slots are 16-bytes (this happens when there is at least one
Morello relocation on the GOT), the references in .plt.got and in
.got are always capabilities; the dynamic linker will take care of
that. For PLT, the default trampoline is a capability. This is
true for A64 as well as C64.
- At present it is assumed that there is no interworking between A64
and C64 functions.
bfd/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* elfnn-aarch64.c (elfNN_c64_small_plt0_entry,
elfNN_c64_small_plt_entry): New variables.
(elfNN_aarch64_howto_table): Add relocations.
(setup_plt_values): Choose C64 PLT when appropriate.
(bfd_elfNN_aarch64_set_options): Defer setup_plt_values
call...
(elfNN_aarch64_link_setup_gnu_properties) ... from here as
well...
(elfNN_aarch64_size_dynamic_sections): ... to here.
(elfNN_aarch64_final_link_relocate,
elfNN_aarch64_check_relocs, elfNN_aarch64_reloc_type_class):
Support new relocations.
(map_symbol_type): New member AARCH64_MAP_C64.
(elfNN_aarch64_output_arch_local_syms): Use it.
(aarch64_update_c64_plt_entry): New function.
(elfNN_aarch64_create_small_pltn_entry): Use it.
(elfNN_aarch64_init_small_plt0_entry): Emit C64 PLT when
appropriate.
* elfxx-aarch64.c (_bfd_aarch64_elf_put_addend,
_bfd_aarch64_elf_resolve_relocation): Add new relocations.
* libbfd.h (bfd_reloc_code_real_names): Likewise.
* reloc.c: New relocations BFD_RELOC_MORELLO_TSTBR14,
BFD_RELOC_MORELLO_BRANCH19, BFD_RELOC_MORELLO_JUMP26,
BFD_RELOC_MORELLO_CALL26, BFD_RELOC_MORELLO_JUMP_SLOT and
BFD_RELOC_MORELLO_IRELATIVE.
* bfd-in2.h: Regenerate.
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (parse_operands): Choose C64 branch
relocations when appropriate.
(md_apply_fix, aarch64_force_relocation,
aarch64_fix_adjustable): Support C64 branch relocations.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* elf/aarch64.h: New relocations R_MORELLO_TSTBR14,
R_MORELLO_CONDBR19, R_MORELLO_JUMP26, R_MORELLO_CALL26,
R_MORELLO_JUMP_SLOT and R_MORELLO_IRELATIVE.
ld/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* testsuite/ld-aarch64/aarch64-elf.exp: Add new tests.
* testsuite/ld-aarch64/c64-ifunc-2-local.d: New file.
* testsuite/ld-aarch64/c64-ifunc-2.d: New file.
* testsuite/ld-aarch64/c64-ifunc-3a.d: New file.
* testsuite/ld-aarch64/c64-ifunc-3b.d: New file.
* testsuite/ld-aarch64/c64-ifunc-4.d: New file.
* testsuite/ld-aarch64/c64-ifunc-4a.d: New file.
* testsuite/ld-aarch64/ifunc-2-local.s: Support capabilities.
* testsuite/ld-aarch64/ifunc-2.s: Likewise.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-dis.c (get_sym_code_type): Fix C64 PLT disassembly.
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- Implement R_MORELLO_LD128_GOT_LO12_NC and emit the correct
relocation based on the target register size.
- Add R_MORELLO_GLOB_DAT and R_MORELLO_RELATIVE dynamic relocations for GOT
entries
- Add support for capabilities in GOT
GOT slots for capabilities need to be 16 byte to accommodate
capabilities. For this purpose, we delay initialising size and
alignment of the GOT sections until we have walked all relocs in
check_relocs. If we encounter capability relocations during the walk,
set the GOT entry size and alignment to account for capabilities or
leave it pointer sized otherwise.
bfd/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* elfnn-aarch64.c (GOT_ENTRY_SIZE): Adjust for C64
relocations. Adjust callers.
(GOT_RESERVED_HEADER_SLOTS, GOT_CAP): New macros.
(elfNN_aarch64_howto_table): Add R_MORELLO_LD128_GOT_LO12_NC
and R_MORELLO_GLOB_DAT.
(elf_aarch64_link_hash_table): New member c64_rel.
(bfd_elfNN_aarch64_set_options): Initialise it.
(cap_meta, c64_get_capsize): New functions.
(aarch64_reloc_got_type): Use GOT_CAP.
(elfNN_aarch64_final_link_relocate): Add
R_MORELLO_LD128_GOT_LO12_NC and R_MORELLO_GLOB_DAT.
(aarch64_elf_create_got_section): Move section initialisation
into a...
(aarch64_elf_init_got_section): ... New function.
(elfNN_aarch64_size_dynamic_sections): Call it.
(elfNN_aarch64_check_relocs): Add R_MORELLO_LD128_GOT_LO12_NC
and R_MORELLO_GLOB_DAT.
(elfNN_aarch64_finish_dynamic_symbol): Emit C64 relocations
when appropriate.
(elfNN_aarch64_got_elt_size): New function.
(elfNN_aarch64_got_header_size): Return GOT entry size based
on c64_rel.
(elf_backend_got_elt_size): New macro.
* elfxx-aarch64.c (_bfd_aarch64_elf_put_addend,
_bfd_aarch64_elf_resolve_relocation): Add
BFD_RELOC_MORELLO_LD128_GOT_LO12_NC.
* libbfd.h (bfd_reloc_code_real_names): Add
BFD_RELOC_MORELLO_GLOB_DAT and
BFD_RELOC_MORELLO_LD128_GOT_LO12_NC.
* reloc.c: Likewise.
* bfd-in2.h: Regenerate.
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (parse_operands): Emit C64 relocations
for got_lo12. Move old relocation checks from...
(md_apply_fix): ... here.
* testsuite/gas/aarch64/morello-ldst-reloc.d: Add tests.
* testsuite/gas/aarch64/morello-ldst-reloc.s: Likewise.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* elf/aarch64.h: New relocations R_MORELLO_LD128_GOT_LO12_NC
and R_MORELLO_GLOB_DAT.
ld/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* testsuite/ld-aarch64/emit-relocs-morello-1.d: New file.
* testsuite/ld-aarch64/emit-relocs-morello-1.s: New test file.
* testsuite/ld-aarch64/aarch64-elf.exp: Add it to test runner.
|
|
Introduce three new relocations disguised as two relocations to
support capabilities.
R_MORELLO_CAPINIT is emitted as a static relocation by the assembler
and as a dynamic relocation by the linker; it's a one on one free!
The R_MORELLO_CAPINIT static relocation is emitted by the assembler to
provide capability information to the static linker. The static
linker may do one of two things:
- For local symbols that can be resolved at link time, the static
linker sets up frag and emits a R_MORELLO_RELATIVE dynamic
relocation that the dynamic linker can resolve in a manner similar
to R_AARCH64_RELATIVE. The dynamic linker will have all of the
information it needs (i.e. permissions, size and relative address)
to set up the capability without needing to peek into the symbol
table.
- For dynamic symbols, the static linker emits a R_MORELLO_CAPINIT
with the reference of the dynamic symbol it refers to. The dynamic
linker is then responsible for resolving the symbol at runtime and
setting up the capability based on the properties of the symbol it
is able to deduce.
Linker and Linker script defined symbols
----------------------------------------
For symbols defined by the linker or in linker scripts, capability
size and permissions are based on the section the symbol belongs to.
For linker defined symbols (i.e. _DYNAMIC or _GLOBAL_OFFSET_TABLE_)
this is straightforward since the linker puts them in the correct
section and at the start.
For symbols defined in the linker script, if they are anywhere but the
end of the output script definition, their range becomes the point at
which they are defined, up to the end of the output section. For
symbols defined at the end of the output section, the symbols are
defined with a zero size unless their name is of the form __start_.*
or __.*_start, indicating a start of the section that follows it. In
this case, the symbols are given the range and permission of the
output section following it.
Ideally, the last case (i.e. the heuristic looking for the name)
should be strictly for compatibility and should eventually be fixed in
the linker script to put the symbol into the output section it intends
to track. It may be a useful enhancement to add a warning to that
effect.
bfd/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* elfnn-aarch64.c (elfNN_aarch64_howto_table,
elfNN_aarch64_final_link_relocate, elfNN_aarch64_check_relocs,
elfNN_aarch64_relocate_section): Add R_MORELLO_CAPINIT and
R_MORELLO_RELATIVE.
(elf_aarch64_link_hash_table): New member srelcaps.
(c64_valid_cap_range, exponent, cap_meta,
section_start_symbol, c64_fixup_frag): New functions.
* elfxx-aarch64.c (_bfd_aarch64_elf_put_addend,
_bfd_aarch64_elf_resolve_relocation): Add
BFD_RELOC_MORELLO_CAPINIT and BFD_RELOC_MORELLO_RELATIVE.
* libbfd.h (bfd_reloc_code_real_names): Likewise.
* reloc.c: Likewise.
* bfd-in2.h: Regenerate.
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (s_aarch64_capinit): New function.
(md_pseudo_table): Use it.
(md_apply_fix): Add BFD_RELOC_MORELLO_CAPINIT.
(aarch64_fix_adjustable): Return FALSE for capabilities.
* testsuite/gas/aarch64/morello-capinit.d: New test file.
* testsuite/gas/aarch64/morello-capinit.s: Likewise.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* elf/aarch64.h (R_MORELLO_CAPINIT, R_MORELLO_RELATIVE): New
relocations.
ld/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* testsuite/ld-aarch64/aarch64-elf.exp: Add test.
* testsuite/ld-aarch64/morello-capinit.d: New file.
* testsuite/ld-aarch64/morello-capinit.ld: New file.
* testsuite/ld-aarch64/morello-capinit.s: New file.
|
|
New relocations R_MORELLO_ADR_PREL_PG_HI20,
R_MORELLO_ADR_PREL_PG_HI20_NC and R_MORELLO_ADR_GOT_PAGE
bfd/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* reloc.c: Add MORELLO_ADR_HI20_PCREL,
MORELLO_ADR_HI20_NC_PCREL and MORELLO_ADR_GOT_PAGE.
* elfnn-aarch64.c (elfNN_aarch64_howto_table): Likewise.
(aarch64_reloc_got_type): Add MORELLO_ADR_GOT_PAGE.
(_bfd_aarch64_erratum_843419_branch_to_stub): Add C64 argument
to _bfd_aarch64_reencode_adr_imm.
(elfNN_aarch64_final_link_relocate,
elfNN_aarch64_check_relocs): Add MORELLO_ADR_GOT_PAGE,
MORELLO_ADR_HI20_PCREL and MORELLO_ADR_HI20_NC_PCREL.
* elfxx-aarch64.c (_bfd_aarch64_reencode_adr_imm): Add C64
argument.
(_bfd_aarch64_elf_put_addend): Adjust callers.
* elfxx-aarch64.h (_bfd_aarch64_reencode_adr_imm): Add C64
argument.
* libbfd.h (bfd_reloc_code_real_names): Add
MORELLO_ADR_GOT_PAGE, MORELLO_ADR_HI20_PCREL and
MORELLO_ADR_HI20_NC_PCREL.
* bfd-in2.h: Regenerate.
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (reloc_table_entry): Add c64_adrp_type
field.
(reloc_table): Adjust.
(parse_adrp): Adjust users.
(md_apply_fix): Add MORELLO_ADR_GOT_PAGE,
MORELLO_ADR_HI20_PCREL and MORELLO_ADR_HI20_NC_PCREL.
* testsuite/gas/aarch64/morello_insn-c64.d: Adjust test.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* elf/aarch64.h: Add R_MORELLO_ADR_PREL_PG_HI20,
R_MORELLO_ADR_PREL_PG_HI20_NC and R_MORELLO_ADR_GOT_PAGE.
|
|
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (process_omitted_operand,
parse_operands): Add Cat_SYS.
* testsuite/gas/aarch64/morello_ldst-c64.d: Add tests.
* testsuite/gas/aarch64/morello_ldst.d: Likewise.
* testsuite/gas/aarch64/morello_ldst.s: Likewise.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* opcode/aarch64.h (aarch64_opnd): New operand Cat_SYS.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-opc.c (operand_general_constraint_met_p): Expect
capability registers for cache operations in C64.
(aarch64_print_operand): Print register arguments for cache
instructions correctly.
* aarch64-tbl.h (aarch64_opcode_table): New instructions.
(AARCH64_OPERANDS): New operands.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
|
|
Implement MRS/MSR for capability registers.
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (parse_sys_reg): New opcode argument.
(parse_operands): Adjust callers.
* testsuite/gas/aarch64/morello_insn-c64.d: Add tests.
* testsuite/gas/aarch64/morello_insn.d: Likewise.
* testsuite/gas/aarch64/morello_insn.s: Likewise.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* include/opcode/aarch64.h
(aarch64_sys_reg_capreg_supported_p): New function.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-asm.c (aarch64_ins_sysreg): Adjust for morello
MRS/MSR.
* aarch64-dis.c (aarch64_ext_sysreg): Likewise.
* aarch64-opc.c (fields): New field a64c_op0.
(operand_general_constraint_met_p): Add SYSREG operand
validation.
(aarch64_print_operand): Print Morello MRS/MSR operands
correctly.
(SR_MORELLO): New macro.
(aarch64_sys_regs): Use it. Add Morello system registers.
(aarch64_sys_reg_capreg_supported_p): New function.
* aarch64-opc.h (aarch64_field_kind): New field FLD_a64c_op0.
* aarch64-tbl.h (QL2_SRC_CA, QL2_DST_CA): New macros.
(aarch64_opcode_table): New instructions.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
|
|
The opcodes for these instructions overlap with their A64 equivalents;
in fact they're the same with one bit reduced in the immediate. Use
mapping symbols to determine the correct disassembly.
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (parse_operands): Add A64C_ADDR_ADRDP.
Support 20-bit offset for capability variants.
* testsuite/gas/aarch64/morello_insn-c64.d: Add tests.
* testsuite/gas/aarch64/morello_insn.d: Likewise.
* testsuite/gas/aarch64/morello_insn.s: Likewise.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add A64C_ADDR_ADRDP.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-dis.c (aarch64_ext_regno): Reject A64 ADR when in
C64.
(aarch64_ext_imm): Select ADRDP in C64.
* aarch64-opc.c (fields): Add a64c_immhi field.
(validate_adr_reg_for_feature): New function.
(operand_general_constraint_met_p): Use it.
(aarch64_print_operand): Add A64C_ADDR_ADRDP.
* aarch64-opc.h (aarch64_field_kind): FLD_a64c_immhi.
* aarch64-tbl.h (aarch64_opcode_table): Add new instructions.
(AARCH64_OPERANDS): Add new operands.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
|
|
Give the ops saner names instead of _2, _3, etc.
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (parse_operand): Reuse ADDR_UIMM12 code
in CAPADDR_UIMM9.
(try_to_encode_as_unscaled_ldst, fix_insn): Add support for
altbase loads and stores.
* testsuite/gas/aarch64/morello_ldst-c64.d: Add tests.
* testsuite/gas/aarch64/morello_ldst.d: Likewise.
* testsuite/gas/aarch64/morello_ldst.s: Likewise.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* opcode/aarch64.h (aarch64_op): Add members for altbase LDUR
and STUR. Rename existing LDUR ops.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-tbl.h (aarch64_opcode_table): Change OP of LDUR/STUR
instructions.
* aarch64-opc-2.c: Regenerate.
|
|
LDRB, LDRH, LDRSB, LDRSH, STRB, STRH, LDURB, LDURH, STURB, STURH,
LDURSB, LDURSH, LDURSW.
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* testsuite/gas/aarch64/morello_ldst-c64.d: Add tests.
* testsuite/gas/aarch64/morello_ldst.d: Likewise.
* testsuite/gas/aarch64/morello_ldst.s: Likewise.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* opcode/aarch64.c (F_NOSHIFT): New flag.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-asm.c (aarch64_ins_addr_uimm): Shift only if
F_NOSHIFT is not set.
* aarch64-tbl.h (QL2_B_ADDR, QL2_X_ADDR, QL2_H_ADDR): New
macro.
(aarch64_opcode_table): New instructions.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
|
|
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (parse_operands): Add Rsz2, Fsz, St and
CAPADDR_SIMM9.
(try_to_encode_as_unscaled_ldst): Add unscaled altbase loads.
* testsuite/gas/aarch64/morello_ldst-c64.d: Add tests.
* testsuite/gas/aarch64/morello_ldst.d: Likewise.
* testsuite/gas/aarch64/morello_ldst.s: Likewise.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add sz2, Fsz, St and
CAPADDR_SIMM9.
(aarch64_op): Add OP_STR_POS_3, OP_LDR_POS_3, OP_STR_POS_4,
OP_LDR_POS_4, OP_LDUR_3, OP_STUR_3, OP_LDUR_4, OP_STUR_4.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-asm.c (aarch64_ins_fregsz): New function.
(aarch64_ins_addr_simm): Add ldst_altbase to assert.
* aarch64-asm.h (ins_fregsz): New function declaration.
* aarch64-dis.c (aarch64_ext_fregsz): New function.
(aarch64_ext_addr_simm): Disable writeback for ldst_altbase.
* aarch64-dis.h (ext_fregsz): New function declaration.
* aarch64-opc.c (fields): Add altbase_sf2 and altbase_sf3.
(operand_general_constraint_met_p): Add CAPADDR_SIMM9.
(aarch64_print_operand): Add CAPADDR_SIMM9, Rsz2, Fsz, St.
* aarch64-opc.h (aarch64_field_kind): Add FLD_altbase_sf2, FLD_altbase_sf3.
* aarch64-tbl.h (aarch64_opcode_table): New instructions.
(AARCH64_OPERANDS): New operands.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
|
|
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (parse_operands): Add Rsz,
CAPADDR_REGOFF, CAPADDR_UIMM9.
* testsuite/gas/aarch64/morello_ldst-c64.d: Add tests.
* testsuite/gas/aarch64/morello_ldst.d: Likewise.
* testsuite/gas/aarch64/morello_ldst.s: Likewise.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* opcode/aarch64.c (aarch64.opnd): add Rsz, CAPADDR_REGOFF,
CAPADDR_UIMM9.
(aarch64_insn_class): Add ldst_altbase.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-asm.c (aarch64_ins_regsz): New function.
(aarch64_ins_ft): Support altbase loads.
(aarch64_ins_addr_uimm12): Rename to aarch64_ins_addr_uimm.
* aarch64-asm.h: (ins_regsz): New function declaration.
(ins_addr_uimm12): Rename to ins_addr_uimm.
* aarch64-dis.c (aarch64_ext_regsz): New function.
(aarch64_ext_ft): Support altbase loads.
(aarch64_ext_addr_uimm12): Rename to aarch64_ext_addr_uimm.
* aarch64-dis.h: (ext_regsz): New function declaration.
(dis_addr_uimm12): Rename to dis_addr_uimm.
* aarch64-opc.c (fields): Add altbase_sf.
(operand_general_constraint_met_p): Check constraints for
ldst_altbase, CAPADDR_REGOFF, CAPADDR_UIMM9.
(aarch64_print_operand): Print Rsz, CAPADDR_REGOFF,
CAPADDR_UIMM9.
* aarch64-opc.h (aarch64_field_kind): Add FLD_altbase_sf.
* aarch64-tbl.h (QL2_A64C_R_CAPADDR, QL2_A64C_FP_CAPADDR): New
macro.
(aarch64_opcode_table): New instructions.
(AARCH64_OPERANDS): New operands.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
|
|
These are loads that use a capability base register in A64 and 64-bit
integer register in C64.
This patch implements LDAR, LDARB, STLR and STLRB.
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (parse_operands): Add Wt.
* testsuite/gas/aarch64/morello_ldst-c64.d: Add tests.
* testsuite/gas/aarch64/morello_ldst.d: Likewise.
* testsuite/gas/aarch64/morello_ldst.s: Likewise.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add Wt.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-opc.c (get_altbase_reg_name): New function.
(aarch64_print_operand): Use it. Add Wt.
* aarch64-tbl.h (QL2_A64C_W_CAPADDR): New macro.
(aarch64_opcode_table): Add instructions.
(AARCH64_OPERANDS): New operand.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
|
|
- LDR/STR immediate, indexed and register offset
- LDUR/STUR
- LDTR/STTR
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (parse_operands, fix_insn): Add
A64C_ADDR_SIMM9.
(try_to_encode_as_unscaled_ldst): Add capability loads.
* testsuite/gas/aarch64/morello_ldst-c64.d: Add tests.
* testsuite/gas/aarch64/morello_ldst.d: Likewise.
* testsuite/gas/aarch64/morello_ldst.s: Likewise.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add A64C_ADDR_SIMM9.
(aarch64_op): Add OP_STR_POS_2, OP_LDR_POS_2, OP_LDUR_2,
OP_STUR_2.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-asm.c (aarch64_ins_addr_simm): Support scaling.
* aarch64-dis.c (aarch64_ext_addr_simm): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p,
aarch64_print_operand): Add A64C_ADDR_SIMM9.
* aarch64-tbl.h (aarch64_opcode_table): New instructions.
(AARCH64_OPERANDS): New operands.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
|
|
The 17-bit signed offset needs to be 16-byte aligned, but the
PCC-relative address resolution rounds down the final address to the
16-byte boundary. Due to this, disassembly of the instruction will
show as if it is loading from the middle of an object.
bfd/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* elfnn-aarch64.c (elfNN_aarch64_howto_table): Add
LD_PREL_LO17.
(elfNN_aarch64_final_link_relocate,
elfNN_aarch64_check_relocs): Likewise.
* elfxx-aarch64.c (reencode_ld_lit_ofs_17): New function.
(_bfd_aarch64_elf_put_addend,
_bfd_aarch64_elf_resolve_relocation): Add LD_PREL_LO17.
* libbfd.h (bfd_reloc_code_real_names): Add
BFD_RELOC_MORELLO_LD_LO17_PCREL.
* reloc.c: Add BFD_RELOC_AARCH64_LD_LO17_PCREL.
* bfd-in2.h: Regenerate.
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (encode_ld_lit_ofs_17): New function.
(parse_operands, programmer_friendly_fixup, md_apply_fix): Add
ADDR_PCREL17.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* elf/aarch64.h: New relocation R_MORELLO_LD_PREL_LO17.
* opcode/aarch64.h (aarch64_opnd): Add ADDR_PCREL17.
(aarch64_op): Add OP_LDR_LIT_2.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-opc.c (fields): Add imm17.
(operand_general_constraint_met_p, aarch64_print_operand): Add
ADDR_PCREL17.
* aarch64-opc.h (aarch64_field_kind): Add FLD_imm17.
* aarch64-tbl.h (QL2_A64C_CA_PCREL): New macro.
(aarch64_opcode_table): New instruction.
(AARCH64_OPERANDS): New operand.
|
|
- LDAPR, LDAR, LDXP, LDAXP, LDXR, LDAXR, LDCT, LDNP, LDP.
- STXR, STLXR, STLR, STXP, STLXP, STCT, STNP, STP.
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (parse_operands, fix_insn): Add
A64C_ADDR_SIMM7.
* testsuite/gas/aarch64/morello_ldst-c64.d: Add tests.
* testsuite/gas/aarch64/morello_ldst.d: Likewise.
* testsuite/gas/aarch64/morello_ldst.s: Likewise.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add A64C_ADDR_SIMM7.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-opc.c (fields): Add a64c_index2.
(operand_general_constraint_met_p, aarch64_print_operand): Add
A64C_ADDR_SIMM7.
* aarch64-opc.h (aarch64_field_kind): Add FLD_a64c_index2.
* aarch64-tbl.h (QL2_A64C_CA_ADDR, QL2_A64C_X_ADDR,
QL3_A64C_W_CA_ADDR, QL4_A64C_W_CA_CA_ADDR): New macros.
(aarch64_opcode_table): New instructions.
(AARCH64_OPERANDS): New operands.
|
|
- BR, BLR
- LDPBR, LDPBLR
This branch instructions take an address as their target operand. The
important distinction between the address register usage between these
instructions and other load and store instructions is that these
instructions do not support 64-bit registers as addresses.
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (aarch64_addr_reg_parse): Add capability
registers.
(parse_address_main): Support capability address operands.
(parse_cap_address): New function.
(parse_operands): Add CAPADDR_SIMPLE and CAPADDR_SIMM7.
* testsuite/gas/aarch64/morello_ldst-c64.d: Add tests.
* testsuite/gas/aarch64/morello_ldst.d: Likewise.
* testsuite/gas/aarch64/morello_ldst.s: Likewise.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add CAPADDR_SIMPLE and
CAPADDR_SIMM7.
(aarch64_insn_class): Add br_capaddr.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-asm.c (aarch64_ins_addr_simple): Fix comment.
(aarch64_ins_addr_simm): Support capability address operands.
* aarch64-dis.c (aarch64_ext_addr_simple): Fix comment.
(aarch64_ext_addr_simm): Support capability address operands.
* aarch64-opc.c (fields): Add capaddr_simm7.
(operand_general_constraint_met_p): Add CAPADDR_SIMM7.
(aarch64_print_operand): Add CAPADDR_SIMM7 and CAPADDR_SIMPLE.
* aarch64-opc.h (aarch64_field_kind): Add FLD_capaddr_simm7.
* aarch64-tbl.h (QL1_A64C_CAPADDR, QL2_A64C_CA_CAPADDR): New
macros.
(aarch64_opcode_table): New instructions.
(AARCH64_OPERANDS): New operands.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
|
|
- SEAL, UNSEAL
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (parse_operands): Add FORM.
* testsuite/gas/aarch64/morello_insn-c64.d: Add tests.
* testsuite/gas/aarch64/morello_insn.d: Likewise.
* testsuite/gas/aarch64/morello_insn.s: Likewise.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/aarch64.h (aarch64_operand_class): Add FORM.
(aarch64_opnd): Likewise.
(aarch64_form): New struct.
(aarch64_forms): New array.
(get_form_from_value, get_form_from_str): New functions.
(aarch64_opnd_info): New member FORM.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-asm.c (aarch64_ins_form): New function.
* aarch64-asm.h (ins_form): New function declaration.
* aarch64-dis.c (aarch64_ext_form): New function.
* aarch64-dis.h (ext_form): New function declaraion.
* aarch64-opc.c (fields): New field form.
(aarch64_forms): Initialise array.
(get_form_from_value, get_form_from_str): New functions.
(aarch64_print_operand): Add FORM.
* aarch64-opc.h (aarch64_field_kind): Add FLD_form.
* aarch64-tbl.h (aarch64_opcode_table): New instructions.
(AARCH64_OPERANDS): New operands.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
|
|
SCBNDS, SCBNDSE, SCFLGS, SCOFF, SCTAG, SCVALUE.
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (parse_operands): Add IMM6_EXT.
* testsuite/gas/aarch64/morello_insn-c64.d: Add tests.
* testsuite/gas/aarch64/morello_insn.d: Likewise.
* testsuite/gas/aarch64/morello_insn.s: Likewise.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* include/aarch64.h (aarch64_opnd): Add IMM6_EXT.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-asm.c (aarch64_ins_aimm): Fix comment.
* aarch64-dis.c (aarch64_ext_a64c_imm6): New function.
* aarch64-dis.h (ext_a64c_imm6): New function.
* aarch64-opc.c (fields): New field a64c_shift.
(operand_general_constraint_met_p, aarch64_print_operand): Add
IMM6_EXT.
* aarch64-opc.h (aarch64_field_kind): Add new field.
* aarch64-tbl.h (aarch64_opcode_table): New instructions.
(AARCH64_OPERANDS): New operands.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
|
|
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (parse_perms): New function.
(parse_operands): Add PERM.
* testsuite/gas/aarch64/morello_insn-c64.d: Add tests.
* testsuite/gas/aarch64/morello_insn.d: Likewise.
* testsuite/gas/aarch64/morello_insn.s: Likewise.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* opcode/aarch64.h (aarch64_operand_class): Add PERM.
(aarch64_opnd): Add PERM.
(get_perm_bit): New function.
(aarch64_opnd_info): New member perm.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-asm.c (aarch64_ins_perm): New function.
* aarch64-asm.h (ins_perm): New function.
* aarch64-dis.c (aarch64_ext_perm): New function.
* aarch64-dis.h (ext_perm): New function.
* aarch64-opc.c (fields): New field perm.
(get_perm_str, get_perm_bit): New functions.
(aarch64_print_operand): Add PERM.
* aarch64-opc.h (aarch64_field_kind): Add perm.
* aarch64-tbl.h (QL_I2SAMEQ): New macro.
(aarch64_opcode_table): New instructions.
(AARCH64_OPERANDS): New operands.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
|
|
- BLR, BLRR, BLRS, BR, BRR, BRS, BX.
- RET, RETR, RETS.
Disassembly note: RET with capability is always disassembled with the
register name even if it is the default register, i.e. C30. This is
to make it visually simpler to differentiate between the A64 and
Morello RET instructions.
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (process_omitted_operand): Identify Can.
(parse_operands): Add CST_REG, Cam_SP
and A64C_IMMV4.
* testsuite/gas/aarch64/morello_insn.s: Add tests.
* testsuite/gas/aarch64/morello_insn.d: Likewise.
* testsuite/gas/aarch64/morello_insn-c64.d: Likewise.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add CST_REG, Cam_SP
and A64C_IMMV4.
(aarch64_insn_class): Add br_sealed.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-dis.c (aarch64_ext_a64c_immv): New function.
(aarch64_ext_regno): Set PRESENT flag for A64 RET.
* aarch64-dis.h (aarch64_ext_a64c_immv): New function.
* aarch64-opc.c (operand_general_constraint_met_p): Add
A64C_IMMV4. Remove ATTRIBUTE_UNUSED. Reject A64 RET without
operand when in C64.
(aarch64_match_operands_constraint): Remove ATTRIBUTE_UNUSED.
(aarch64_print_operand): Add A64C_IMMV4, Cam_SP and CST_REG.
* aarch64-tbl.h (QL1_A64C_CA, QL3_A64C_CA_CA_CA): New macros.
(aarch64_opcode_table): New instructions.
(AARCH64_OPERANDS): New operands.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
|
|
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (parse_operands): Add A64C_IMM8.
* testsuite/gas/aarch64/morello_insn.d: Add tests.
* testsuite/gas/aarch64/morello_insn-c64.d: Likewise.
* testsuite/gas/aarch64/morello_insn.s: Likewise.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add A64C_IMM8.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-opc.c (fields): Add a64c_imm8.
(aarch64_print_operand): Add A64C_IMM8.
* aarch64-opc.h (aarch64_field_kind): Add a64c_imm8.
* aarch64-tbl.h (QL3_A64C_CA_CA_X): New macro.
(aarch64_opcode_table): New instructions.
(AARCH64_OPERANDS): Add A64C_IMM8.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
|
|
Implement ADD (immediate), SUB (immediate) and ADD (extended
register).
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (parse_operands, fix_insn): Add
A64C_AIMM and A64C_Rm_EXT.
* testsuite/gas/aarch64/morello_insn.d: Add tests.
* testsuite/gas/aarch64/morello_insn-c64.d: Add tests.
* testsuite/gas/aarch64/morello_insn.s: Likewise.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* opcode/aarch64 (aarch64_opnd): Add A64C_AIMM and
A64C_Rm_EXT.
(aarch64_op): Add OP_A64C_ADD.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reg_extended):
Identify capability register class.
(do_ext_aimm): New function.
(arch64_ext_aimm): Call it.
(aarch64_ext_a64c_aimm): New function.
* aarch64-dis.h (ext_a64c_aimm): New function.
* aarch64-opc.c (fields): Add a64c_shift_ai field.
(operand_general_constraint_met_p, aarch64_print_operand): Add
A64C_AIMM and A64C_Rm_EXT.
* aarch64-opc.h (aarch64_field_kind): Add a64c_shift_ai.
* aarch64-tbl.h (QL3_A64C_CA_CA_NIL, QL3_A64C_CA_CA_R): New
macro.
(aarch64_opcode_table): New instructions.
(AARCH64_OPERANDS): Add new operands.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
|
|
MOV is an alias of CPY in all cases except when moving CZR into a
capability register (e.g. mov c0, czr), in which case it is treated
as an alias of mov x0, xzr.
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (parse_operands): Add capability
register operands.
* testsuite/gas/aarch64/morello_insn.d: Add tests.
* testsuite/gas/aarch64/morello_insn-c64.d: Likewise.
* testsuite/gas/aarch64/morello_insn.s: Likewise.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* opcode/aarch64.h (aarch64_opnd): New capability operands.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-asm.c (do_special_encoding): Recognise capability
registers.
* aarch64-opc.c (aarch64_opnd_qualifiers): Capability operand
qualifiers.
(aarch64_print_operand): Support capability operands.
* aarch64-opc.h (select_operand_for_sf_field_coding):
Recognise capability registers.
* aarch64-tbl.h (QL2_A64C_CA_CA): New macro.
(aarch64_opcode_table): Add mov and cpy.
(AARCH64_OPERANDS): Add capability register operands.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
|
|
The Morello processor takes the LSB of the PCC (i.e. the capability
equivalent of PC) as a hint to set PE state to C64 when set and A64
otherwise.
bfd/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Set LSB for C64 symbols.
(elfNN_aarch64_output_map_sym, elfNN_aarch64_output_stub_sym):
Initialise st_target_internal.
(aarch64_elfNN_swap_symbol_in, aarch64_elfNN_swap_symbol_out):
New functions.
(elfNN_aarch64_size_info): Add them as callbacks.
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c: Include cpu-aarch64.h.
(IS_C64): New macro.
(make_mapping_symbol, aarch64_frob_label): Set LSB of C64
symbol.
(aarch64_adjust_symtab): Mark all C64 functions.
(parse_operands): Set LSB when target of ADR is a function.
(aarch64_fix_adjustable): New function.
* config/tc-aarch64.h (AARCH64_SET_FLAG, AARCH64_RESET_FLAG,
AARCH64_FLAG_C64, AARCH64_IS_C64, AARCH64_SET_C64): New
macros.
(aarch64_fix_adjustable): New function.
(tc_fix_adjustable): Use it.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* elf/aarch64.h (aarch64_st_branch_type): New enum.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-dis.c: Include elf/aarch64.h.
(get_sym_code_type): Identify C64 functions.
|
|
Add a mapping symbol $c at the beginning of every C64 code section to
allow the disassembler to identify C64 code sections. This will allow
the disassembler to print the correct base address registers and also
choose the correct disassembly in cases where the opcodes for A64 and
C64 instructions are aliased.
To aid correct disassembly of instructions, pass CPU variant to
various helpers in libopcodes so that they can use that information to
choose between A64 and C64 disassembly.
bfd/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* cpu-aarch64.c (bfd_is_aarch64_special_symbol_name): Add
capability mapping symbol.
* elfnn-aarch64.c (elfNN_aarch64_output_map_sym,
is_aarch64_mapping_symbol): Likewise.
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.h (mstate): Add MAP_C64.
* config/tc-aarch64.c (make_mapping_symbol): Add capability
mapping symbol.
(MAP_CUR_INSN): New macro.
(mapping_state, s_aarch64_inst, md_assemble,
aarch64_handle_align, aarch64_init_frag): Use it.
(output_operand_error_record, do_encode,
try_to_encode_as_unscaled_ldst, fix_mov_imm_insn, fix_insn):
Pass CPU_VARIANT to AARCH64_OPCODE_ENCODE.
* doc/c-aarch64.texi: Document $c.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* opcode/aarch64.h (aarch64_opcode_encode): Add cpu variant
argument.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-asm.c (aarch64_opcode_encode): Add CPU variant
argument.
* aarch64-dis.c (map_type): Add MAP_C64.
(MAYBE_C64): New macro.
(determine_disassembling_preference, print_operands): Use it.
(aarch64_symbol_is_valid): Test for $c.
(get_sym_code_type): Recognise MAP_C64.
(select_aarch64_variant): Clear AARCH64_FEATURE_C64.
(determine_disassembling_preference, aarch64_opcode_decode):
Adjust calls to aarch64_match_operands_constraint.
* aarch64-opc.c (get_altbase_reg_name, get_base_reg_name): New
functions.
(aarch64_print_operand): Use them.
(aarch64_match_operands_constraint): Likewise.
* aarch64-opc.h (aarch64_match_operands_constraint): Add CPU
variant argument.
|
|
The Morello architecture implements support for 129 bit capabilities
to replace traditional pointers to reference memory. A 129 bit
capability has a 64-bit virtual address in its lowest bits and the
next 64 bits have various access control metadata such as bounds
within which the virtual address can be, permissions and other
metadata for protection. The top 129th bit is stored out of band and
it indicates if the capability is valid.
Capability registers extends the 64-bit register file and are
similarly numberd c0 to c30. The stack capability register is csp and
it aliases with sp. One may access the lower 64 bits of the
capability registers by using the 64-bit register names, i.e. x0-x30
and sp. The Arm Architecture Reference Manual Supplement Morello for
A-profile Architecture has more details on the register layout.
To ensure backward compatibiility, processors implementing the Morello
architecture can run in two states, the standard A64 and a new state
called C64. In A64 state, base addresses of memory access
instructions are treated as pointers and traditional aarch64
applications should run out of the box in this state. In C64 state,
base address registers are expected to be valid capabilities.
There are additional load and store instructions that allow using
capabilities as address registers in A64 mode (and 64-bit registers in
C64 mode). These are called alternate base loads and stores.
The following new -march flags are implemented:
- a64c: This is the base feature flag to implement instruction
extensions for Morello that are distinct from its base A64 support.
Address registers are assumed to be 64-bit except for alternate base
loads and stores; they are assumed to be capability registers.
- morello: This enables instructions that are allowed on the Morello
architecture in A64. This includes armv8.2-a, a64c and other
extensions that are considered part of the Morello architecture.
- c64: This enables instructions that are allowed on the Morello
architecture in C64 state. Address registers are assumed to be
capabilities except for alternate base loads and stores; they are
assumed to be 64-bit registers.
To assemble code that is intended to run in A64 state on Morello,
build with -march=morello and for C64 state, build with
-march=morello+c64.
This patch implements bare support for registers and the -march flags.
gas/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* config/tc-aarch64.c (AARCH64_REG_TYPES,
get_reg_expected_msg, aarch64_addr_reg_parse, parse_address,
reg_names): Add capability registers.
(parse_operands): Identify capability register based address.
(aarch64_archs): Add morello.
(aarch64_features): Add a64c and c64.
* doc/c-aarch64.texi: Document -march flags.
* testsuite/gas/aarch64/morello_insn.d: New file
* testsuite/gas/aarch64/morello_insn-c64.d: New file
* testsuite/gas/aarch64/morello_insn.s: New file.
include/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_A64C,
AARCH64_FEATURE_C64): New feature macros.
(AARCH64_ARCH_MORELLO): New architecture macro.
(aarch64_operand_class): Add AARCH64_OPND_CLASS_CAP_REG.
(aarch64_opnd): New capability operands.
(aarch64_opnd_qualifier): New capability qualifier.
(aarch64_insn_class): Add a64c instruction class.
opcodes/ChangeLog:
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-opc.c (fields): New capability register fields.
(aarch64_opnd_qualifiers): Capability operand qualifiers.
(int_reg): Add capability register bank.
(get_int_reg_name): Adjust for capability registers.
(get_cap_reg_name): New function.
(aarch64_print_operand): Support printing capability operands.
* aarch64-opc.h (aarch64_field_kind): Add capability operand
fields.
(OPD_F_MAYBE_CSP): New macro.
(operand_maybe_cap_stack_pointer): New function.
* aarch64-tbl.h (QL2_A64C_CA_CA, A64C, A64C_INSN): New macros.
(aarch64_feature_a64c): New feature set.
|
|
Generally, glibc dynamic linker should have two ways to deal with ifunc
- one is to handle the IRELATIVE relocations for the non-preemtive ifunc
symbols, the other is to handle the R_RISCV_32/64 and R_RISCV_JUMP_SLOT
relocations with the STT_IFUNC preemtive symbols. No matter which method
is used, both of them should get the resolved ifunc symbols at runtime.
Therefore, linker needs to generate the correct dynamic relocations for
ifunc to make sure the the dynamic linker works well. For now, there are
thirteen relocations are supported for ifunc in GNU ld,
* R_RISCV_CALL and R_RISCV_CALL_PLT:
The RISC-V compiler won't generate R_RISCV_JAL directly to jump to an
ifunc. Besides, we disable the relaxations for the relocation referenced
to ifunc, so just handling the R_RISCV_CALL and R_RISCV_CALL_PLT should be
enough. Linker should generate a .plt entry and a .got.plt entry for it,
and also needs to insert a dynamic IRELATIVE in the .got.plt enrty, or
insert a R_RISCV_JUMP_SLOT when generating shared library.
* R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO12_I/S:
LA/LLA pattern with local fPIC ifunc symbol, or any non-PIC ifunc symbol.
The PC-relative relocation. The current linker will deal with them in
the same way as R_RISCV_CALL_PLT.
* R_RISCV_GOT_HI20 and R_RISCV_PCREL_LO12_I/S:
LA pattern with global PIC ifunc symbol. Linker should insert a dynamic
IRELATIVE in the .got entry, or insert a R_RISCV_32/64 when generating
shared library.
* R_RISCV_32 and R_RISCV_64:
Store the ifunc symbol into the data section. Linker should insert a
dynamic IRELATIVE in the data section, or insert a R_RISCV_32/64 when
generating shared library.
* R_RISCV_HI20 and R_RISCV_LO12_I/S:
The LUI + ADDI/LW/SW patterns. The absolute access relocation. The
medlow model without the -fPIC compiler option should generate them.
The ld ifunc testsuites "Build pr23169a" and "Build pr23169d" need the
relocations, they are in the ld/testsuite/ld-ifunc/, and need compiler
support.
However, we also made some optimizations with reference to x86,
* If GOT and PLT relocations refer to the same ifunc symbol when generating
pie, then they can actually share a .got entry without creating two entries
to store the same value and relocation.
* If GOT, PLT and DATA relocations refer to the same ifunc symbol when
generating position dependency executable, then linker will fill the address
of .plt entry into the corresponding .got entry and data section, without
insert any dynamic relocations for the GOT and DATA relocations.
For the ifunc testcases, there are three types of them,
1. ifunc-reloc-*: Only check the single type of relocation refers to
ifunc symbol.
* ifunc-reloc-call: R_RISCV_CALL and R_RISCV_CALL_PLT.
* ifunc-reloc-data: R_RISCV_32 and R_RISCV_64.
* ifunc-reloc-got: R_RISCV_GOT_HI20 and R_RISCV_PCREL_LO_I/S.
* ifunc-reloc-pcrel: R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO_I/S.
2. ifunc-[nonplt|plt]-*: If we don't have PLT relocs, then don't need to
create the PLT and it's .plt entries.
* ifunc-nonplt: Combine R_RISCV_GOT_HI20 and R_RISCV_32/64.
* ifunc-plt: Combine all ifunc relocations.
3. ifunc-seperate-*: If we link the ifunc caller and resolver into the
same module (link the objects), then the results are the same as the
ifunc-reloc-* and ifunc-[noplt|plt]-* testcases. Consider the cases that
the ifunc callers and resolver are in the different modules, that is, we
compile the ifunc resolver to the shared library first, and then link it
with the ifunc callers. The output of ifunc callers should be the same as
the normal STT_FUNC cases, and the shared ifunc resolver should define the
symbols as STT_IFUNC.
The R_RISCV_PCREL_HI20 reloc is special. It should be linked and resolved
locally, so if the ifunc resolver is defined in other modules (other shared
libraries), then the R_RISCV_PCREL_HI20 is unresolvable, and linker should
issue an unresolvable reloc error.
bfd/
* elfnn-riscv.c: Include "objalloc.h" since we need objalloc_alloc.
(riscv_elf_link_hash_table): Add loc_hash_table and loc_hash_memory
for local STT_GNU_IFUNC symbols.
(riscv_elf_got_plt_val): Removed.
(riscv_elf_local_htab_hash, riscv_elf_local_htab_eq): New functions.
Use to compare local hash entries.
(riscv_elf_get_local_sym_hash): New function. Find a hash entry for
local symbol, and create a new one if needed.
(riscv_elf_link_hash_table_free): New function. Destroy an riscv
elf linker hash table.
(riscv_elf_link_hash_table_create): Create hash table for local ifunc.
(riscv_elf_check_relocs): Create a fake global symbol to track the
local ifunc symbol. Add support to check and handle the relocations
reference to ifunc symbols.
(allocate_dynrelocs): Let allocate_ifunc_dynrelocs and
allocate_local_ifunc_dynrelocs to handle the ifunc symbols if they
are defined and referenced in a non-shared object.
(allocate_ifunc_dynrelocs): New function. Allocate space in .plt,
.got and associated reloc sections for ifunc dynamic relocs.
(allocate_local_ifunc_dynrelocs): Likewise, but for local ifunc
dynamic relocs.
(riscv_elf_relocate_section): Add support to handle the relocation
referenced to ifunc symbols.
(riscv_elf_size_dynamic_sections): Updated.
(riscv_elf_adjust_dynamic_symbol): Updated.
(riscv_elf_finish_dynamic_symbol): Finish up the ifunc handling,
including fill the PLT and GOT entries for ifunc symbols.
(riscv_elf_finish_local_dynamic_symbol): New function. Called by
riscv_elf_finish_dynamic_symbol to handle the local ifunc symbols.
(_bfd_riscv_relax_section): Don't do the relaxation for ifunc.
* elfxx-riscv.c: Add R_RISCV_IRELATIVE.
* configure.ac: Link elf-ifunc.lo to use the generic ifunc support.
* configure: Regenerated.
include/
* elf/riscv.h: Add R_RISCV_IRELATIVE to 58.
ld/
* emulparams/elf32lriscv-defs.sh: Add IREL_IN_PLT.
* testsuite/ld-ifunc/ifunc.exp: Enable ifunc tests for RISC-V.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp (run_dump_test_ifunc):
New dump test for ifunc. There are two arguments, 'target` and
`output`. The `target` is rv32 or rv64, and the `output` is used
to choose which output you want to test (exe, pie or .so).
* testsuite/ld-riscv-elf/ifunc-reloc-call-01.s: New testcase.
* testsuite/ld-riscv-elf/ifunc-reloc-call-01.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-01-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-01-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-01-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-02.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-02.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-02-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-02-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-02-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-data.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-data.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-data-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-data-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-data-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-got.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-got.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-got-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-got-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-got-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-pcrel.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-pcrel.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-pcrel-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-pcrel-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-pcrel-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-nonplt.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-nonplt.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-nonplt-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-nonplt-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-nonplt-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-01.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-01.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-01-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-01-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-01-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-02.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-02.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-02-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-02-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-02-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-resolver.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-caller.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-exe.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-pic.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-pie.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-caller-pcrel.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-pcrel-pic.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-pcrel-pie.d: Likewise.
|
|
GCC 11 supports -march=x86-64-v[234] to enable x86 micro-architecture ISA
levels:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97250
Update GNU_PROPERTY_X86_ISA_1_XXX macros:
https://gitlab.com/x86-psABIs/x86-64-ABI/-/merge_requests/13
in x86 ELF binaries to indicate that micro-architecture ISA levels
required to execute the binary:
#define GNU_PROPERTY_X86_ISA_1_NEEDED (GNU_PROPERTY_X86_UINT32_OR_LO + 2)
#define GNU_PROPERTY_X86_ISA_1_USED (GNU_PROPERTY_X86_UINT32_OR_AND_LO + 2)
#define GNU_PROPERTY_X86_ISA_1_V2 (1U << 0)
#define GNU_PROPERTY_X86_ISA_1_V3 (1U << 1)
#define GNU_PROPERTY_X86_ISA_1_V4 (1U << 2)
The previous GNU_PROPERTY_X86_ISA_1_XXX macros are deprecated and renamed
to GNU_PROPERTY_X86_COMPAT_2_ISA_1_XXX.
In addition to EM_X86_64, GNU_PROPERTY_X86_ISA_1_V[234] marker can be used
by ld.so to detect the x86-64-v4 shared library placed in an x86-64-v2
directory by mistake on an x86-64-v2 machine to avoid crashes on x86-64-v4
instructions.
Add -z x86-64-v[234] linker command line option to mark x86-64-v[234]
ISA level as needed.
Also add
#define GNU_PROPERTY_X86_FEATURE_2_MASK (1U << 11)
for mask registers.
bfd/
PR gas/26703
* elf-linker-x86.h (elf_linker_x86_params): Add isa_level.
* elfxx-x86.c (_bfd_x86_elf_merge_gnu_properties): Merge
GNU_PROPERTY_X86_ISA_1_V[234].
(_bfd_x86_elf_link_setup_gnu_properties): Generate
GNU_PROPERTY_X86_ISA_1_V[234] for -z x86-64-v[234].
binutils/
PR gas/26703
* readelf.c (decode_x86_compat_2_isa): New function.
(decode_x86_isa): Updated for new X86_ISA_1_XXX bits.
(decode_x86_feature_1): Handle GNU_PROPERTY_X86_FEATURE_2_MASK.
(print_gnu_property_note): Handle X86_COMPAT_2_ISA_1_USED,
and X86_COMPAT_2_ISA_1_NEEDED.
* testsuite/binutils-all/i386/pr21231b.s: Updated to the current
GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_ISA_1_NEEDED
values.
* testsuite/binutils-all/x86-64/pr21231b.s: Likewise.
* testsuite/binutils-all/x86-64/pr23494a.s: Likewise.
* testsuite/binutils-all/x86-64/pr23494b.s: Likewise.
* testsuite/binutils-all/x86-64/pr23494c.s: Likewise.
* testsuite/binutils-all/i386/empty.d: Updated.
* testsuite/binutils-all/i386/ibt.d: Likewise.
* testsuite/binutils-all/i386/pr21231a.d: Likewise.
* testsuite/binutils-all/i386/pr21231b.d: Likewise.
* testsuite/binutils-all/i386/shstk.d: Likewise.
* testsuite/binutils-all/x86-64/empty-x32.d: Likewise.
* testsuite/binutils-all/x86-64/empty.d: Likewise.
* testsuite/binutils-all/x86-64/ibt-x32.d: Likewise.
* testsuite/binutils-all/x86-64/ibt.d: Likewise.
* testsuite/binutils-all/x86-64/pr21231a.d: Likewise.
* testsuite/binutils-all/x86-64/pr21231b.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494a-x32.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494a.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494c-x32.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494c.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494d-x32.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494d.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494e-x32.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494e.d: Likewise.
* testsuite/binutils-all/x86-64/shstk-x32.d: Likewise.
* testsuite/binutils-all/x86-64/shstk.d: Likewise.
gas/
PR gas/26703
* config/tc-i386.c (xstate): Add xstate_mask.
(md_assemble): Check i.types[j], instead of i.tm.operand_types[j],
for xstate. Set xstate_mask, instead of xstate_zmm, for RegMask.
(output_insn): Update for GNU_PROPERTY_X86_ISA_1_V[234]. Update
xstate for mask register and VSIB.
* testsuite/gas/i386/i386.exp: Run more GNU_PROPERTY tests.
* testsuite/gas/i386/property-1.s: Updated to the current
GNU_PROPERTY_X86_ISA_1_USED value.
* testsuite/gas/i386/property-2.s: Only keep cmove.
* testsuite/gas/i386/property-3.s: Changed to addsubpd.
* testsuite/gas/i386/property-1.d: Updated.
* testsuite/gas/i386/property-2.d: Likewise.
* testsuite/gas/i386/property-3.d: Likewise.
* testsuite/gas/i386/property-4.d: Likewise.
* testsuite/gas/i386/property-5.d: Likewise.
* testsuite/gas/i386/property-6.d: Likewise.
* testsuite/gas/i386/x86-64-property-1.d: Likewise.
* testsuite/gas/i386/x86-64-property-2.d: Likewise.
* testsuite/gas/i386/x86-64-property-3.d: Likewise.
* testsuite/gas/i386/x86-64-property-4.d: Likewise.
* testsuite/gas/i386/x86-64-property-5.d: Likewise.
* testsuite/gas/i386/x86-64-property-6.d: Likewise.
* testsuite/gas/i386/x86-64-property-7.d: Likewise.
* testsuite/gas/i386/x86-64-property-8.d: Likewise.
* testsuite/gas/i386/x86-64-property-9.d: Likewise.
* testsuite/gas/i386/property-11.d: New file.
* testsuite/gas/i386/property-11.s: Likewise.
* testsuite/gas/i386/property-12.d: Likewise.
* testsuite/gas/i386/property-12.s: Likewise.
* testsuite/gas/i386/property-13.d: Likewise.
* testsuite/gas/i386/property-13.s: Likewise.
* testsuite/gas/i386/x86-64-property-11.d: Likewise.
* testsuite/gas/i386/x86-64-property-12.d: Likewise.
* testsuite/gas/i386/x86-64-property-13.d: Likewise.
* testsuite/gas/i386/x86-64-property-14.d: Likewise.
* testsuite/gas/i386/x86-64-property-14.s: Likewise.
include/
PR gas/26703
* elf/common.h (GNU_PROPERTY_X86_ISA_1_USED): Renamed to ...
(GNU_PROPERTY_X86_COMPAT_2_ISA_1_USED): This.
(GNU_PROPERTY_X86_ISA_1_NEEDED): Renamed to ...
(GNU_PROPERTY_X86_COMPAT_2_ISA_1_NEEDED): This.
(GNU_PROPERTY_X86_ISA_1_XXX): Renamed to ...
(GNU_PROPERTY_X86_COMPAT_2_ISA_1_XXX): This.
(GNU_PROPERTY_X86_ISA_1_NEEDED): New.
(GNU_PROPERTY_X86_ISA_1_USED): Likewise.
(GNU_PROPERTY_X86_ISA_1_V2): Likewise.
(GNU_PROPERTY_X86_ISA_1_V3): Likewise.
(GNU_PROPERTY_X86_ISA_1_V4): Likewise.
(GNU_PROPERTY_X86_FEATURE_2_MASK): Likewise.
ld/
PR gas/26703
* NEWS: Mention -z x86-64-v[234].
* ld.texi: Document -z x86-64-v[234].
* emulparams/elf32_x86_64.sh: Use x86-64-level.sh.
* emulparams/elf_i386.sh: Likewise.
* emulparams/elf_x86_64.sh: Likewise.
* emulparams/x86-64-level.sh: New file.
* testsuite/ld-elf/x86-feature-1a.rd: Update.
* testsuite/ld-elf/x86-feature-1b.rd: Likewise.
* testsuite/ld-elf/x86-feature-1c.rd: Likewise.
* testsuite/ld-elf/x86-feature-1d.rd: Likewise.
* testsuite/ld-elf/x86-feature-1e.rd: Likewise.
* testsuite/ld-i386/pr23372c.d: Likewise.
* testsuite/ld-i386/pr23486c.d: Likewise.
* testsuite/ld-i386/pr23486d.d: Likewise.
* testsuite/ld-i386/pr24322a.d: Likewise.
* testsuite/ld-i386/pr24322b.d: Likewise.
* testsuite/ld-i386/property-1a.r: Likewise.
* testsuite/ld-i386/property-2a.r: Likewise.
* testsuite/ld-i386/property-3.r: Likewise.
* testsuite/ld-i386/property-3a.r: Likewise.
* testsuite/ld-i386/property-4.r: Likewise.
* testsuite/ld-i386/property-4a.r: Likewise.
* testsuite/ld-i386/property-5.r: Likewise.
* testsuite/ld-i386/property-5a.r: Likewise.
* testsuite/ld-i386/property-7a.r: Likewise.
* testsuite/ld-i386/property-x86-3.d: Likewise.
* testsuite/ld-i386/property-x86-4a.d: Likewise.
* testsuite/ld-i386/property-x86-5.d: Likewise.
* testsuite/ld-i386/property-x86-cet1.d: Likewise.
* testsuite/ld-i386/property-x86-cet2a.d: Likewise.
* testsuite/ld-i386/property-x86-cet5a.d: Likewise.
* testsuite/ld-i386/property-x86-cet5b.d: Likewise.
* testsuite/ld-i386/property-x86-ibt1a.d: Likewise.
* testsuite/ld-i386/property-x86-ibt1b.d: Likewise.
* testsuite/ld-i386/property-x86-ibt2.d: Likewise.
* testsuite/ld-i386/property-x86-ibt3a.d: Likewise.
* testsuite/ld-i386/property-x86-ibt3b.d: Likewise.
* testsuite/ld-i386/property-x86-ibt4.d: Likewise.
* testsuite/ld-i386/property-x86-ibt5.d: Likewise.
* testsuite/ld-i386/property-x86-shstk1a.d: Likewise.
* testsuite/ld-i386/property-x86-shstk1b.d: Likewise.
* testsuite/ld-i386/property-x86-shstk2.d: Likewise.
* testsuite/ld-i386/property-x86-shstk3a.d: Likewise.
* testsuite/ld-i386/property-x86-shstk3b.d: Likewise.
* testsuite/ld-i386/property-x86-shstk4.d: Likewise.
* testsuite/ld-i386/property-x86-shstk5.d: Likewise.
* testsuite/ld-x86-64/pr23372c-x32.d: Likewise.
* testsuite/ld-x86-64/pr23372c.d: Likewise.
* testsuite/ld-x86-64/pr23486c.d: Likewise.
* testsuite/ld-x86-64/pr23486d-x32.d: Likewise.
* testsuite/ld-x86-64/pr23486d.d: Likewise.
* testsuite/ld-x86-64/pr24322a-x32.d: Likewise.
* testsuite/ld-x86-64/pr24322a.d: Likewise.
* testsuite/ld-x86-64/pr24322b-x32.d: Likewise.
* testsuite/ld-x86-64/pr24322b.d: Likewise.
* testsuite/ld-x86-64/pr24458a-x32.d: Likewise.
* testsuite/ld-x86-64/pr24458a.d: Likewise.
* testsuite/ld-x86-64/pr24458b-x32.d: Likewise.
* testsuite/ld-x86-64/pr24458b.d: Likewise.
* testsuite/ld-x86-64/pr24458c-x32.d: Likewise.
* testsuite/ld-x86-64/pr24458c.d: Likewise.
* testsuite/ld-x86-64/property-1a.r: Likewise.
* testsuite/ld-x86-64/property-2a.r: Likewise.
* testsuite/ld-x86-64/property-3.r: Likewise.
* testsuite/ld-x86-64/property-3a.r: Likewise.
* testsuite/ld-x86-64/property-4.r: Likewise.
* testsuite/ld-x86-64/property-4a.r: Likewise.
* testsuite/ld-x86-64/property-5.r: Likewise.
* testsuite/ld-x86-64/property-5a.r: Likewise.
* testsuite/ld-x86-64/property-7a.r: Likewise.
* testsuite/ld-x86-64/property-x86-3-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-3.d: Likewise.
* testsuite/ld-x86-64/property-x86-4a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-4a.d: Likewise.
* testsuite/ld-x86-64/property-x86-5-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-5.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet1-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet1.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet2a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet2a.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet5a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet5a.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet5b-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet5b.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt1a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt1a.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt1b-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt1b.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt2-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt2.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt3a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt3a.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt3b-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt3b.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt4-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt4.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt5-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt5.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk1a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk1a.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk1b-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk1b.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk2-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk2.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk3a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk3a.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk3b-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk3b.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk4-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk4.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk5-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk5.d: Likewise.
* testsuite/ld-i386/i386.exp: Run property-x86-6,
property-x86-isa1, property-x86-isa2 and property-x86-isa3.
* testsuite/ld-i386/property-x86-1.S: Updated to the current
GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_ISA_1_NEEDED
values.
* testsuite/ld-i386/property-x86-2.S: Likewise.
* testsuite/ld-i386/property-x86-3.s: Likewise.
* testsuite/ld-x86-64/pr23372d.s: Likewise.
* testsuite/ld-x86-64/pr23372e.s: Likewise.
* testsuite/ld-x86-64/pr23372f.s: Likewise.
* testsuite/ld-x86-64/pr23486c.s: Likewise.
* testsuite/ld-x86-64/pr23486d.s: Likewise.
* testsuite/ld-x86-64/property-x86-1.S: Likewise.
* testsuite/ld-x86-64/property-x86-2.S: Likewise.
* testsuite/ld-x86-64/property-x86-3.s: Likewise.
* testsuite/ld-x86-64/property-x86-5a.s: Likewise.
* testsuite/ld-x86-64/property-x86-5b.s: Likewise.
* testsuite/ld-i386/property-x86-6.d: New file.
* testsuite/ld-i386/property-x86-isa1.d: Likewise.
* testsuite/ld-i386/property-x86-isa2.d: Likewise.
* testsuite/ld-i386/property-x86-isa3.d: Likewise.
* testsuite/ld-x86-64/property-x86-6-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-6.d: Likewise.
* testsuite/ld-x86-64/property-x86-6.s: Likewise.
* testsuite/ld-x86-64/property-x86-isa1-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-isa1.d: Likewise.
* testsuite/ld-x86-64/property-x86-isa1.s: Likewise.
* testsuite/ld-x86-64/property-x86-isa2-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-isa2.d: Likewise.
* testsuite/ld-x86-64/property-x86-isa3-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-isa3.d: Likewise.
* testsuite/ld-x86-64/simple.s: Likewise.
* ld/testsuite/ld-x86-64/x86-64.exp: Run property-x86-6,
property-x86-6-x32, property-x86-isa1, property-x86-isa1-x32,
property-x86-isa2, property-x86-isa2-x32, property-x86-isa3-x32
and property-x86-isa3.
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This adds a get_DW_UT_name function to dwarfnames using dwarf2.def
for use in binutils readelf to show the unit types in a DWARF5 header.
include/ChangeLog:
Sync with GCC
* dwarf2.def: Add DWARF5 Unit type header encoding macros
DW_UT_FIRST, DW_UT and DW_UT_END.
* dwarf2.h (enum dwarf_unit_type): Removed and define using
DW_UT_FIRST, DW_UT and DW_UT_END macros.
(get_DW_UT_name): New function declaration.
libiberty/ChangeLog:
Sync with GCC
* dwarfnames.c (get_DW_UT_name): Define using DW_UT_FIRST, DW_UT
and DW_UT_END.
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The symbol string table in the .symtab section is optional and cosmetic.
The contents of the .symtab section have no impact on run-time execution.
The symbol names in the symbol string table help distinguish addresses at
different locations. Add a linker option, -z unique-symbol, to avoid
duplicated local symbol names in the symbol string table.
This feature was well received by the livepatch maintainers. It not only
solves the duplicated local symbol name problem, but also would allow
livepatch to more precisely locate duplicate symbols in general for
patching.
bfd/
PR ld/26391
* elflink.c (elf_final_link_info): Add local_hash_table.
(local_hash_entry): New.
(local_hash_newfunc): Likewise.
(elf_link_output_symstrtab): Append ".COUNT" to duplicated local
symbols.
(bfd_elf_final_link): Initialize and free local_hash_table for
"-z unique-symbol".
include/
PR ld/26391
* bfdlink.h (bfd_link_info): Add unique_symbol.
ld/
PR ld/26391
* NEWS: Mention "-z unique-symbol".
* emultempl/elf.em (gld${EMULATION_NAME}_handle_option): Handle
"-z unique-symbol" and "-z nounique-symbol".
* ld.texi: Document "-z unique-symbol" and "-z nounique-symbol".
* lexsup.c (elf_static_list_options): Add "-z unique-symbol" and
"-z nounique-symbol".
* testsuite/ld-elf/elf.exp: Add PR ld/26391 tests.
* testsuite/ld-elf/pr26391.nd: New file.
* testsuite/ld-elf/pr26391.out: Likewise.
* testsuite/ld-elf/pr26391a.c: Likewise.
* testsuite/ld-elf/pr26391b.c: Likewise.
* testsuite/ld-elf/pr26391c.c: Likewise.
* testsuite/ld-elf/pr26391d.c: Likewise.
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include:
2020-09-10 Felix Willgerodt <felix.willgerodt@intel.com>
Sync with GCC
2020-08-17 Felix Willgerodt <felix.willgerodt@intel.com>
* floatformat.h (floatformat_bfloat16_big): New.
(floatformat_bfloat16_little): New.
libiberty:
2020-09-10 Felix Willgerodt <felix.willgerodt@intel.com>
Sync with GCC
2020-08-17 Felix Willgerodt <felix.willgerodt@intel.com>
* floatformat.c (floatformat_bfloat16_big): New.
(floatformat_bfloat16_little): New.
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The previous patch missed one modification.
Following is the error message:
gas/config/tc-csky.c:806:5: error: 'CSKY_ARCH_804' undeclared here
(not in a function); did you mean 'CSKY_ARCH_807'?
include/
* opcode/csky.h (CSKYV1_ISA_E1): Convert to bfd_uint64_t type.
(CSKYV2_ISA_E1): Likewise.
(CSKYV2_ISA_1E2): Likewise.
(CSKYV2_ISA_2E3): Likewise.
(CSKYV2_ISA_3E7): Likewise.
(CSKYV2_ISA_7E10): Likewise.
(CSKYV2_ISA_3E3R1): Likewise.
(CSKYV2_ISA_3E3R2): Likewise.
(CSKYV2_ISA_10E60): Likewise.
(CSKYV2_ISA_3E3R3): Likewise.
(CSKY_ISA_TRUST): Likewise.
(CSKY_ISA_CACHE): Likewise.
(CSKY_ISA_NVIC): Likewise.
(CSKY_ISA_CP): Likewise.
(CSKY_ISA_MP): Likewise.
(CSKY_ISA_MP_1E2): Likewise.
(CSKY_ISA_JAVA): Likewise.
(CSKY_ISA_MAC): Likewise.
(CSKY_ISA_MAC_DSP): Likewise.
(CSKY_ISA_DSP): Likewise.
(CSKY_ISA_DSP_1E2): Likewise.
(CSKY_ISA_DSP_ENHANCE): Likewise.
(CSKY_ISA_DSPE60): Likewise.
(CSKY_ISA_FLOAT_E1): Likewise.
(CSKY_ISA_FLOAT_1E2): Likewise.
(CSKY_ISA_FLOAT_1E3): Likewise.
(CSKY_ISA_FLOAT_3E4): Likewise.
(CSKY_ISA_FLOAT_7E60): Likewise.
(CSKY_ISA_VDSP): Likewise.
(CSKY_ISA_VDSP_2): Likewise.
(CSKY_ARCH_804): Define.
(CSKY_ARCH_805): Define.
(CSKY_ARCH_800): Define.
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Define NT_X86_CET which is the proposed note for x86 CET state to support
Intel CET in Linux kernel. Double check it after Intel CET patches have
been merged into Linux kernel.
binutils/
* readelf.c (get_note_type): Support NT_X86_CET.
include/
* elf/common.h (NT_X86_CET): New.
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Add arches CK804, CK805 and CK800. CK800 is an special arch which
support all instructions for CSKYV2. Refine the cpu tables to
simplify adding a new cpu.
Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com>
gas/
* config/tc-csky.c (struct csky_cpu_info): Add new members
isa_flag, features and ver.
(struct csky_cpu_feature): New.
(struct csky_cpu_version): New.
(CSKY_FEATURE_MAX): Define.
(CSKY_CPU_REVERISON_MAX): Define.
(FEATURE_DSP_EXT, FEATURE_DSP, FEATURE_MMU, FEATURE_VDSP,
FEATURE_FLOAT, FEATURE_TRUST, FEATURE_JAVA, FEATURE_SHIELD):
Define, each standard one collection of instructions.
(CSKY_FEATURES_DEF_NULL, CSKY_FEATURES_DEF_e,
CSKY_FEATURES_DEF_t, CSKY_FEATURES_DEF_f, CSKY_FEATURES_DEF_v,
CSKY_FEATURES_DEF_ef, CSKY_FEATURES_DEF_jt,
CSKY_FEATURES_DEF_efht, CSKY_FEATURES_DEF_efv,
CSKY_FEATURES_DEF_eft, CSKY_FEATURES_DEF_d,
CSKY_FEATURES_DEF_df, CSKY_FEATURES_DEF_ft,
CSKY_FEATURES_DEF_tv, CSKY_FEATURES_DEF_fv,
CSKY_FEATURES_DEF_dft, CSKY_FEATURES_DEF_dfv,
CSKY_FEATURES_DEF_ftv, CSKY_FEATURES_DEF_eftv): Define,
the features combination used by cpu.
(CSKY_CPU_REVERISON_r0p0, CSKY_CPU_REVERISON_r1p0,
CSKY_CPU_REVERISON_r2p0, CSKY_CPU_REVERISON_r3p0,
CSKY_CPU_REVERISON_RESERVED, CSKY_CPU_REVERISON_R3):
Define, version information used by cpu.
(csky_cpus): Refine, and add CK804, CK805 and CK800.
(parse_cpu): Refine.
(parse_arch): Refine.
(md_show_usage): Refine.
(md_begin): Refine.
include/
* opcode/csky.h (CSKY_ARCH_804): Define.
(CSKY_ARCH_805): Define.
(CSKY_ARCH_800): Define.
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incldue * opcode/csky.h (CSKY_ISA_FLOAT_7E60): Use a long long type for
this value.
opcodes * csky-dis.c (csky_output_operand): Coerce the immediate values to
long before printing.
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gas/
* config/tc-csky.c (CSKYV2_ISA_DSP): CSKY_ISA_DSPE60.
(CSKY_ISA_860): Likewise.
include/
* opcode/csky.h (CSKY_ISA_DSPE60): Define.
opcodes/
* csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
ISA flag.
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|
Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com>
gas/
* config/tc-csky.c (float_work_fpuv3_fmovi): New function,
helper function to encode fpuv3 fmovi instructions.
(float_work_fpuv3_fstore): New function.
(struct literal): Add new member 'offset'.
(csky_cpus): New cpu CK860f.
(enter_literal): Return literal pool pointer instead of offset.
(parse_rt): Adjust the change of enter_literal.
(parse_rtf): Likewise.
(v1_work_lrw): Likewise.
(v1_work_jbsr): Likewise.
(v2_work_lrw): Likewise.
(v2_work_jbsr): Likewise.
(v2_work_jsri): Likewise.
(vdsp_work_vlrw): Likewise.
(is_freglist_legal): Add handler for FPUV3.
(parse_type_freg): Likewise.
(is_imm_within_range): Set e.X_add_number if it is a signed and
negtive number.
(get_operand_value): Add handler for OPRND_TYPE_IMM9b,
OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI
and OPRND_TYPE_DFLOAT_FMOVI.
(float_to_half): Convert float number to harf float.
opcodes/
* csky-dis.c (csky_output_operand): Add handlers for
OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
to support FPUV3 instructions.
* csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
OPRND_TYPE_DFLOAT_FMOVI.
(OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
(csky_v2_opcodes): Add FPUV3 instructions.
include/
* opcode/csky.h (CSKY_ISA_FLOAT_7E60): Define.
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