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2021-09-10aarch64: Correct feature bits for MorelloAlex Coplan2-1/+6
2021-06-24Fix ABI checkLuis Machado2-0/+7
2021-05-24Core file support (C registers + capability tags)Luis Machado2-0/+10
2021-03-17Fix disassembly of C64 instructions in GDBLuis Machado2-0/+20
2020-10-20[Morello] Add capability register set supportLuis Machado2-0/+7
2020-10-20[Morello] Add new DWARF defines for capabilitiesLuis Machado3-0/+14
2020-10-20[Morello] TLS Descriptor supportSiddhesh Poyarekar2-0/+9
2020-10-20[Morello] Implement branch relocationsSiddhesh Poyarekar2-0/+20
2020-10-20[Morello] GOT RelocationsSiddhesh Poyarekar2-0/+8
2020-10-20[Morello] Capability data relocationsSiddhesh Poyarekar2-0/+10
2020-10-20[Morello] Add Morello relocations for ADRPSiddhesh Poyarekar2-0/+13
2020-10-20[Morello] Make DC, IC capability aware in C64.Siddhesh Poyarekar2-0/+5
2020-10-20[Morello] Add Morello system registersSiddhesh Poyarekar2-0/+7
2020-10-20[Morello] ADR, ADRP and ADRDPSiddhesh Poyarekar2-0/+5
2020-10-20[Morello] Implement LDUR/STUR fallback for LDR/STR in altbase modeSiddhesh Poyarekar2-12/+23
2020-10-20[Morello] altbase: Remaining LD/STSiddhesh Poyarekar2-1/+7
2020-10-20[Morello] altbase: LDUR/STURSiddhesh Poyarekar2-0/+20
2020-10-20[Morello] altbase: LDR/STRSiddhesh Poyarekar2-0/+12
2020-10-20[Morello] Loads and stores with alternate baseSiddhesh Poyarekar2-0/+6
2020-10-20[Morello] All remaining load and store instructionsSiddhesh Poyarekar2-0/+11
2020-10-20[Morello] LDR immediateSiddhesh Poyarekar3-0/+13
2020-10-20[Morello] Load and store instructions.Siddhesh Poyarekar2-0/+5
2020-10-20[Morello] Load and branch instructionsSiddhesh Poyarekar2-0/+10
2020-10-20[Morello] Capability sealing and unsealing instructionsSiddhesh Poyarekar2-0/+23
2020-10-20[Morello] Capability construction and modification instructionsSiddhesh Poyarekar2-0/+5
2020-10-20[Morello] CLRTAG, CLRPERMSiddhesh Poyarekar2-0/+13
2020-10-20[Morello] Branch and return instructionsSiddhesh Poyarekar2-0/+11
2020-10-20[Morello] Add BICFLGSSiddhesh Poyarekar2-0/+5
2020-10-20[Morello] ADD and SUB instructionsSiddhesh Poyarekar2-0/+9
2020-10-20[Morello] Add MOV and CPY instructions for capabilitiesSiddhesh Poyarekar2-0/+5
2020-10-20[Morello] Set LSB for c64 symbols in object codeSiddhesh Poyarekar2-0/+10
2020-10-20[Morello] Add mapping symbol to identify C64 code sectionsSiddhesh Poyarekar2-3/+9
2020-10-20[AArch64] Initial commit for Morello architectureSiddhesh Poyarekar2-0/+38
2020-10-16RISC-V: Support GNU indirect functions.Nelson Chu2-0/+5
2020-10-09x86: Support GNU_PROPERTY_X86_ISA_1_V[234] markerH.J. Lu2-28/+64
2020-09-24Sync libiberty and include with GCC for get_DW_UT_name.Mark Wielaard3-13/+31
2020-09-12elf: Add -z unique-symbol to avoid duplicated local symbol namesH.J. Lu2-0/+8
2020-09-11Sync include, libiberty with GCC.Felix Willgerodt2-0/+11
2020-09-12CSKY: Change ISA flag's type to bfd_uint64_t and fix build error.Cooper Qu2-31/+72
2020-09-11x86: Add NT_X86_CET noteH.J. Lu2-0/+6
2020-09-10CSKY: Add new arches while refine the cpu option process.Cooper Qu1-0/+6
2020-09-10Fix compile time warnings when building for the CSKY target on a 32-bit host.Nick Clifton2-1/+6
2020-09-09CSKY: Change mvtc and mulsw's ISA flag.Cooper Qu2-0/+5
2020-09-09CSKY: Add FPUV3 instructions, which supported by ck860f.Cooper Qu2-0/+6
2020-09-08MSP430: Support relocations for subtract expressions in .uleb128 directivesJozef Lawrynowicz2-0/+11
2020-09-08aarch64: Add support for Armv8-R system registersAlex Coplan2-2/+11
2020-09-08aarch64: Add base support for Armv8-RAlex Coplan2-1/+14
2020-09-02ubsan: v850-opc.c:412 left shift cannot be representedAlan Modra2-1/+6
2020-09-02CSKY: Add CPU CK803r3.Cooper Qu2-0/+5
2020-08-31PR26493 UBSAN: elfnn-riscv.c left shift of negative valueAlan Modra2-4/+10
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