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2016-11-01Add support for RISC-V architecture.Nick Clifton5-0/+1606
2016-10-17Update list of ELF machine numbers.Nick Clifton2-2/+41
2016-10-14FINAL/OVERRIDE: Define to empty on g++ < 4.7Pedro Alves2-5/+24
2016-10-14Move OVERRIDE/FINAL from gcc/coretypes.h to include/ansidecl.hPedro Alves2-6/+27
2016-10-14[ARC] Disassembler: fix LIMM detection for short instructions.Claudiu Zissulescu2-0/+5
2016-09-29Disallow 3-operand cmp[l][i] for ppc64Alan Modra2-0/+8
2016-09-26[ARC] ISA alignment.Claudiu Zissulescu2-1/+7
2016-09-26PowerPC .gnu.attributesAlan Modra2-5/+16
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford2-1/+5
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford2-0/+20
2016-09-21[AArch64][SVE 30/32] Add SVE instruction classesRichard Sandiford2-0/+19
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford2-0/+12
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford2-0/+10
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford2-0/+35
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford2-0/+15
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford2-0/+59
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford2-1/+11
2016-09-21[AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford2-0/+12
2016-09-21[AArch64][SVE 22/32] Add qualifiers for merging and zeroing predicationRichard Sandiford2-0/+8
2016-09-21[AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford2-0/+34
2016-09-21[AArch64][SVE 20/32] Add support for tied operandsRichard Sandiford2-0/+14
2016-09-21[AArch64][SVE 13/32] Add an F_STRICT flagRichard Sandiford2-1/+7
2016-09-07[arm] Automatically enable CRC instructions on supported ARMv8-A CPUs.Richard Earnshaw2-0/+6
2016-08-26Fixes to legacy ARC relocations.Cupertino Miranda3-19/+47
2016-08-042016-08-04 Thomas Preud'homme <thomas.preudhomme@arm.com>Thomas Preud'homme2-0/+12
2016-08-02Synchronize libiberty sources with FSF GCC mainline version.Nick Clifton2-0/+15
2016-08-01 Fix some PowerPC VLE BFD issues and add some PowerPC VLE instructions.Andrew Jenner2-0/+7
2016-07-27Begin implementing ARC NPS-400 Accelerator instructionsGraham Markall2-59/+143
2016-07-20Add support to the ARC disassembler for selecting instruction classes.Claudiu Zissulescu2-0/+5
2016-07-15Add support for creating ELF import librariesThomas Preud'homme2-0/+11
2016-07-15Pass SIGLIBRT directly to child processes.John Baldwin2-1/+7
2016-07-14[ARC] Fix/improve small data support.Claudiu Zissulescu2-1/+5
2016-07-11Fixes done to TLS.Cupertino Miranda1-1/+1
2016-07-05[ARM] Change noread to purecode.Andre Vieria2-1/+6
2016-07-01[AArch64] Fix +nofp16 handlingSzabolcs Nagy2-4/+14
2016-06-30[ARM][GAS] ARMv8.2 should enable ARMv8.1 NEON instructions.Matthew Wahab2-1/+6
2016-06-29sparc: make SPARC_OPCODE_ARCH_MAX part of its enumTrevor Saunders2-2/+6
2016-06-28[AArch64] Make register indices be full 64-bit valuesRichard Sandiford2-3/+7
2016-06-28MIPS16: Add R_MIPS16_PC16_S1 branch relocation supportMaciej W. Rozycki2-1/+6
2016-06-25xtensa: prototype xtensa_make_property_section in elf/xtensa.hTrevor Saunders2-0/+6
2016-06-24Add constants for FreeBSD-specific auxiliary vector entry types.John Baldwin2-0/+17
2016-06-23[ARC] Misc minor edits/fixesGraham Markall2-3/+7
2016-06-22addmore extern CTrevor Saunders4-0/+30
2016-06-22tilegx: move TILEGX_NUM_PIPELINE_ENCODINGS to tilegx_pipeline enumTrevor Saunders2-3/+6
2016-06-21Arc assembler: Convert nps400 from a machine type to an extension.Graham Markall3-2/+9
2016-06-17bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine nu...Jose E. Marchesi2-0/+13
2016-06-14Change the size field of MSP430_Opcode_Decoded to a plain integer.John Baldwin2-8/+6
2016-06-14[ARC] Add deep packet inspection instructions for npsGraham Markall1-0/+1
2016-06-11sparc-coff writing uninitialized memoryAlan Modra2-0/+12
2016-06-09sparc: add missing comment about hyperprivileged register operandsJose E. Marchesi2-0/+7
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