Age | Commit message (Expand) | Author | Files | Lines |
2022-11-08 | sim: drop unused CORE_ADDR_TYPE | Mike Frysinger | 1 | -7/+0 |
2022-11-02 | sim: common: change sim_{fetch,store}_register helpers to use void* buffers | Mike Frysinger | 1 | -3/+2 |
2022-10-31 | sim: reg: constify store helper | Mike Frysinger | 1 | -1/+2 |
2022-10-31 | sim: common: change sim_read & sim_write to use void* buffers | Mike Frysinger | 1 | -2/+2 |
2022-10-28 | include: Define macro to ignore -Wdeprecated-declarations on GCC | Tsukasa OI | 1 | -0/+3 |
2022-10-27 | PowerPC: Add support for RFC02653 - Dense Math Facility | Peter Bergner | 1 | -15/+18 |
2022-10-19 | aarch64-pe support for LD, GAS and BFD | Jedidiah Thompson | 1 | -0/+22 |
2022-10-14 | e200 LSP support | Alan Modra | 1 | -0/+5 |
2022-10-14 | RISC-V: Move certain arrays to riscv-opc.c | Tsukasa OI | 1 | -11/+2 |
2022-10-04 | RISC-V: Fix buffer overflow on print_insn_riscv | Tsukasa OI | 1 | -0/+2 |
2022-10-04 | RISC-V: Renamed INSN_CLASS for floating point in integer extensions. | Nelson Chu | 1 | -7/+7 |
2022-10-04 | RISC-V/gas: allow generating up to 176-bit instructions with .insn | Jan Beulich | 1 | -0/+3 |
2022-10-03 | Fix self-move warning check for GCC 13+ | Jan-Benedict Glaw | 2 | -0/+8 |
2022-09-30 | LoongArch: Update ELF e_flags handling according to specification. | liuzhensong | 1 | -23/+21 |
2022-09-23 | Support AT_USRSTACKBASE and AT_USRSTACKLIM. | John Baldwin | 1 | -0/+2 |
2022-09-23 | RISC-V: Add Zawrs ISA extension support | Christoph Müllner | 2 | -0/+9 |
2022-09-22 | RISC-V: Add T-Head MemPair vendor extension | Christoph Müllner | 2 | -0/+18 |
2022-09-22 | RISC-V: Add T-Head MemIdx vendor extension | Christoph Müllner | 2 | -0/+135 |
2022-09-22 | RISC-V: Add T-Head FMemIdx vendor extension | Christoph Müllner | 2 | -0/+27 |
2022-09-22 | RISC-V: Add T-Head MAC vendor extension | Christoph Müllner | 2 | -0/+21 |
2022-09-22 | RISC-V: Add T-Head CondMov vendor extension | Christoph Müllner | 2 | -0/+9 |
2022-09-22 | RISC-V: Add T-Head Bitmanip vendor extension | Christoph Müllner | 2 | -0/+42 |
2022-09-22 | RISC-V: Add support for arbitrary immediate encoding formats | Christoph Müllner | 1 | -0/+17 |
2022-09-22 | RISC-V: Add T-Head SYNC vendor extension | Christoph Müllner | 2 | -0/+18 |
2022-09-22 | RISC-V: Add T-Head CMO vendor extension | Christoph Müllner | 2 | -0/+66 |
2022-09-22 | include: Add macro to ignore -Wunused-but-set-variable | Tsukasa OI | 1 | -0/+14 |
2022-09-22 | include: Add macro to ignore -Wuser-defined-warnings | Tsukasa OI | 1 | -0/+9 |
2022-09-21 | gdbsupport: move include/gdb/fileio.h contents to fileio.h | Simon Marchi | 1 | -144/+0 |
2022-09-21 | RISC-V: Implement Ztso extension | Shihua | 1 | -0/+3 |
2022-09-12 | ppc: Document the -mfuture and -Mfuture options and make them usable | Peter Bergner | 1 | -0/+3 |
2022-09-06 | opcodes: Add non-enum disassembler options | Tsukasa OI | 1 | -1/+2 |
2022-08-30 | RISC-V: Add 'Zmmul' extension in assembler. | Tsukasa OI | 1 | -0/+1 |
2022-08-11 | ppc/svp64: introduce non-zero operand flag | Dmitry Selyutin | 1 | -0/+5 |
2022-08-11 | ppc/svp64: support LibreSOC architecture | Dmitry Selyutin | 1 | -0/+3 |
2022-08-10 | RISC-V: Remove R_RISCV_GNU_VTINHERIT/R_RISCV_GNU_VTENTRY | Fangrui Song | 1 | -2/+0 |
2022-08-10 | bfd: Add support for LoongArch64 EFI (efi-*-loongarch64). | Youling Tang | 2 | -0/+62 |
2022-08-02 | Add ELFCOMPRESS_ZSTD. | Cary Coutant | 1 | -0/+2 |
2022-07-29 | libopcodes/aarch64: add support for disassembler styling | Andrew Burgess | 1 | -1/+27 |
2022-07-25 | opcodes: add new sub-mnemonic disassembler style | Andrew Burgess | 1 | -0/+7 |
2022-07-25 | bfd: Delete R_LARCH_NONE from dyn info of LoongArch. | liuzhensong | 1 | -1/+4 |
2022-07-25 | bfd: Add supported for LoongArch new relocations. | liuzhensong | 1 | -0/+136 |
2022-07-19 | [AArch64] Support AArch64 MTE memory tag dumps in core files | Luis Machado | 1 | -0/+3 |
2022-07-12 | LTO plugin: sync header file with GCC | Martin Liska | 1 | -0/+33 |
2022-07-08 | Add markers for 2.39 branch | Nick Clifton | 1 | -0/+4 |
2022-07-07 | RISC-V: Added Zfhmin and Zhinxmin. | Tsukasa OI | 1 | -3/+4 |
2022-06-29 | opcodes/aarch64: split off creation of comment text in disassembler | Andrew Burgess | 1 | -1/+1 |
2022-06-28 | RISC-V: Add 'Sstc' extension and its CSRs | Tsukasa OI | 1 | -0/+10 |
2022-06-28 | RISC-V: Add 'Sscofpmf' extension with its CSRs | Tsukasa OI | 1 | -0/+62 |
2022-06-28 | RISC-V: Add 'Smstateen' extension and its CSRs | Tsukasa OI | 1 | -0/+42 |
2022-06-27 | drop XC16x bits | Jan Beulich | 1 | -40/+0 |