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2017-07-14binutils/objdump: Fix disassemble for huge elf sectionsRavi Bangoria2-1/+6
2017-07-07Recognize the recently-added FreeBSD core dump note for LWP info.John Baldwin2-0/+5
2017-07-02Import include/+libiberty/ r249883 from upstream GCC.Jan Kratochvil3-12/+34
2017-06-30Add support for a __gcc_isr pseudo isntruction to the AVR assembler.Georg-Johann Lay2-0/+10
2017-06-30MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki2-0/+8
2017-06-29S390: Support guarded-storage core note sectionsAndreas Arnez2-0/+9
2017-06-28[AArch64] Add dot product support for AArch64 to binutilsTamar Christina2-0/+7
2017-06-28[ARM] Assembler and disassembler support Dot Product ExtensionJiong Wang2-1/+9
2017-06-28MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki3-5/+33
2017-06-26RISC-V: Use pc-relative relocation for FDE initial locationKuan-Lin Chen2-0/+5
2017-06-26Add pgste marker changelogAndreas Krebbel1-0/+4
2017-06-24[ARM] Add support for ARMv8-R in assembler and readelfThomas Preud'homme3-1/+18
2017-06-24[ARM] Remove ARMv6S-M special casingThomas Preud'homme2-5/+15
2017-06-23S/390: Add support for pgste markerAndreas Krebbel1-0/+3
2017-06-22x86: Support Intel Shadow Stack with SHSTK propertyH.J. Lu3-0/+9
2017-06-22x86: Support Intel IBT with IBT property and IBT-enable PLTH.J. Lu3-0/+15
2017-06-21[ARM] Rework Tag_CPU_arch build attribute value selectionThomas Preud'homme2-0/+5
2017-06-16Rewrite __start and __stop symbol handlingAlan Modra2-3/+8
2017-06-14Don't use print_insn_XXX in GDBYao Qi2-8/+8
2017-06-06ld: Allow section groups to be resolved as part of a relocatable linkAndrew Burgess2-0/+8
2017-06-01PPC64_OPT_LOCALENTRYAlan Modra2-0/+5
2017-05-31Fix MinGW compilation warnings due to environ.hEli Zaretskii2-0/+6
2017-05-30[ARC] Add arc-cpu.def with processor definitionsAnton Kolesov2-0/+53
2017-05-30S/390: Improve error checking for optional operandsAndreas Krebbel1-3/+4
2017-05-30S/390: Remove optional operand flag.Andreas Krebbel1-10/+6
2017-05-24Move print_insn_XXX to an opcodes internal headerYao Qi2-78/+7
2017-05-24Refactor disassembler selectionYao Qi2-2/+10
2017-05-23[ARC] Update MAX_INSN_FLGS.claziss2-1/+5
2017-05-22x86: Add NOTRACK prefix supportH.J. Lu2-0/+5
2017-05-19binutils: support for the SPARC M8 processorJose E. Marchesi3-2/+58
2017-05-16Rename non_ir_ref to non_ir_ref_regularAlan Modra2-1/+6
2017-05-16non_ir_ref_dynamicAlan Modra2-5/+10
2017-05-15MIPS16e2: Add MIPS16e2 ASE supportMaciej W. Rozycki3-6/+46
2017-05-14Fix match and mask for 64-bit bb opcode.John David Anglin2-1/+5
2017-05-10[ARC] Object attributes.Claudiu Zissulescu4-64/+146
2017-04-20Handle symbol defined in IR and referenced in DSOH.J. Lu2-0/+9
2017-04-19Implement -z dynamic-undefined-weakAlan Modra2-2/+8
2017-04-11Reorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500Alan Modra2-43/+48
2017-04-11Bye bye PPC_OPCODE_HTM and -mhtmAlan Modra2-5/+1
2017-04-11Bye Bye PPC_OPCODE_VSX3Alan Modra2-3/+1
2017-04-11Bye bye PPC_OPCODE_ALTIVEC2Alan Modra2-3/+4
2017-04-06Add support for disassembling WebAssembly opcodes.Pip Cet2-0/+7
2017-04-05-Wwrite-strings: Constify struct disassemble_info's disassembler_options fieldPedro Alves2-4/+10
2017-04-04Support ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXXH.J. Lu2-0/+14
2017-04-04RISC-V: Resurrect GP-relative disassembly hintsPalmer Dabbelt2-0/+7
2017-03-31RISC-V: Add physical memory protection CSRsAndrew Waterman2-0/+83
2017-03-30Add support for the WebAssembly file format and the wasm32 ELF conversion to ...Pip Cet3-0/+233
2017-03-29PowerPC -Mraw disassemblyAlan Modra2-37/+48
2017-03-27Add minimal support for WebAssembly backend to the BFD library.Pip Cet2-0/+32
2017-03-27Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.Rinat Zelig2-6/+12
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