| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-11-12 | [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension | Sudakshina Das | 2 | -0/+7 |
| 2018-11-12 | [BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten... | Sudakshina Das | 2 | -0/+14 |
| 2018-11-12 | [BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex... | Sudakshina Das | 2 | -0/+7 |
| 2018-11-12 | [BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-A | Sudakshina Das | 2 | -0/+6 |
| 2018-11-07 | Add support for new load commands added by Apple to the MACH-O file format. | Roman Bolshakov | 3 | -28/+55 |
| 2018-11-06 | Add support for a couple of new Mach-O commands. | Nick Clifton | 2 | -1/+7 |
| 2018-11-06 | [BINUTILS, ARM] Add Armv8.5-A to select_arm_features and update macros. | Sudakshina Das | 2 | -4/+9 |
| 2018-10-26 | Support AT_HWCAP2 on FreeBSD. | John Baldwin | 2 | -0/+5 |
| 2018-10-23 | S12Z: New 32 bit Reloc. | John Darrington | 1 | -1/+2 |
| 2018-10-09 | [PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRS | Sudakshina Das | 2 | -1/+9 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers | Sudakshina Das | 2 | -1/+14 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction | Sudakshina Das | 2 | -1/+21 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructions | Sudakshina Das | 2 | -0/+6 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instruction | Sudakshina Das | 2 | -1/+8 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions | Sudakshina Das | 2 | -1/+13 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-A | Sudakshina Das | 2 | -1/+9 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-A | Sudakshina Das | 2 | -1/+14 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea... | Sudakshina Das | 2 | -0/+9 |
| 2018-10-08 | Separate header PT_LOAD for -z separate-code | Alan Modra | 2 | -0/+7 |
| 2018-10-05 | [Arm, 3/3] Add Execution and Data Prediction instructions for AArch32 | Sudakshina Das | 2 | -1/+8 |
| 2018-10-05 | [Arm, 2/3] Add instruction SB for AArch32 | Sudakshina Das | 2 | -1/+8 |
| 2018-10-05 | [Arm, 1/3] Add -march=armv8.5-a and related internal feature macros to AArch32 | Sudakshina Das | 2 | -0/+10 |
| 2018-10-05 | or1k: Add the l.adrp insn and supporting relocations | Stafford Horne | 2 | -0/+20 |
| 2018-10-05 | or1k: Add relocations for high-signed and low-stores | Richard Henderson | 2 | -0/+13 |
| 2018-10-03 | AArch64: Add SVE constraints verifier. | Tamar Christina | 2 | -2/+16 |
| 2018-10-03 | AArch64: Refactor verifiers to make more general. | Tamar Christina | 2 | -1/+8 |
| 2018-10-03 | AArch64: Refactor err_type. | Tamar Christina | 2 | -1/+16 |
| 2018-10-03 | AArch64: Wire through instr_sequence | Tamar Christina | 2 | -2/+27 |
| 2018-10-03 | AArch64: Mark sve instructions that require MOVPRFX constraints | Tamar Christina | 2 | -2/+22 |
| 2018-10-03 | Make print_insn_s12z public. | John Darrington | 2 | -0/+5 |
| 2018-10-02 | RISC-V: Add fence.tso instruction | Palmer Dabbelt | 2 | -0/+7 |
| 2018-10-02 | [ARC] Entries to Changelog for previous commits. | Cupertino Miranda | 1 | -0/+4 |
| 2018-10-01 | [ARC] Fixed issue with DTSOFF relocs. | Cupertino Miranda | 1 | -1/+1 |
| 2018-10-01 | [ARC] Fixes TLS failures related to tls-align. | Cupertino Miranda | 1 | -1/+1 |
| 2018-09-21 | ELF: Don't include zero size sections at start of PT_NOTE segment | H.J. Lu | 2 | -4/+12 |
| 2018-09-20 | Andes Technology has good news for you, we plan to update the nds32 port of b... | Nick Clifton | 4 | -43/+240 |
| 2018-09-20 | Handle missing Solaris auxv entries | Rainer Orth | 2 | -3/+17 |
| 2018-09-05 | Disable -Wformat-nonliteral in parts of printcmd.c | Simon Marchi | 2 | -0/+16 |
| 2018-08-31 | PowerPC64 higher REL16 relocations | Alan Modra | 2 | -5/+18 |
| 2018-08-30 | RISC-V: Allow instruction require more than one extension | Jim Wilson | 2 | -2/+14 |
| 2018-08-29 | [MIPS] Add Loongson 2K1000 proccessor support. | Chenghua Xu | 3 | -0/+6 |
| 2018-08-29 | [MIPS] Add Loongson 3A2000/3A3000 proccessor support. | Chenghua Xu | 3 | -0/+8 |
| 2018-08-29 | [MIPS] Add Loongson 3A1000 proccessor support. | Chenghua Xu | 3 | -9/+12 |
| 2018-08-29 | [MIPS/GAS] Add Loongson EXT2 Instructions support. | Chenghua Xu | 3 | -1/+10 |
| 2018-08-29 | [MIPS/GAS] Split Loongson EXT Instructions from loongson3a. | Chenghua Xu | 3 | -1/+10 |
| 2018-08-29 | [MIPS/GAS] Split Loongson CAM Instructions from loongson3a | Chenghua Xu | 3 | -1/+10 |
| 2018-08-24 | x86: Update GNU_PROPERTY_X86_XXX macros | H.J. Lu | 2 | -24/+147 |
| 2018-08-24 | x86: Add GNU_PROPERTY_X86_UINT32_VALID | H.J. Lu | 2 | -0/+7 |
| 2018-08-22 | Fix changelog entries | Alan Modra | 1 | -1/+1 |
| 2018-08-21 | S12Z: Rename reloc R_S12Z_UKNWN_3 to R_S12Z_EXT18 and implement according to ... | John Darrington | 2 | -1/+5 |
