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AgeCommit message (Expand)AuthorFilesLines
2022-07-29libopcodes/aarch64: add support for disassembler stylingAndrew Burgess1-1/+27
2022-07-07RISC-V: Added Zfhmin and Zhinxmin.Tsukasa OI1-3/+4
2022-06-29opcodes/aarch64: split off creation of comment text in disassemblerAndrew Burgess1-1/+1
2022-06-28RISC-V: Add 'Sstc' extension and its CSRsTsukasa OI1-0/+10
2022-06-28RISC-V: Add 'Sscofpmf' extension with its CSRsTsukasa OI1-0/+62
2022-06-28RISC-V: Add 'Smstateen' extension and its CSRsTsukasa OI1-0/+42
2022-06-22RISC-V: Use single h extension to control hypervisor CSRs and instructions.Nelson Chu2-25/+26
2022-05-30RISC-V: Add zhinx extension supports.jiawei1-2/+3
2022-05-27Remove use of bfd_uint64_t and similarAlan Modra2-32/+32
2022-05-25ppc: extend opindex to 16 bitsDmitry Selyutin1-1/+7
2022-05-20RISC-V: Remove RV128-only fmv instructionsTsukasa OI1-6/+0
2022-05-18AArch64: Enable FP16 by default for Armv9-A.Tamar Christina1-0/+1
2022-05-17RISC-V: Added half-precision floating-point v1.0 instructions.Nelson Chu2-0/+77
2022-04-22RISC-V: Add missing DECLARE_INSNs for Zicbo{m,p,z}Christoph Muellner1-0/+9
2022-03-20gas:LoongArch: Fix segment error in compilation due to too long symbol name.liuzhensong1-2/+2
2022-03-18RISC-V: Cache management instructionsTsukasa OI2-0/+11
2022-03-18RISC-V: Prefetch hint instructions and operand setTsukasa OI2-0/+8
2022-03-16Delete PowerPC macro insn supportAlan Modra1-26/+0
2022-03-16PowerPC64 extended instructions in powerpc_macrosAlan Modra1-3/+5
2022-02-23RISC-V: Updated CSRs to privileged spec v1.12 and debug spec v1.0.Nelson Chu1-34/+49
2022-02-23RISC-V: Add Privileged Architecture 1.12 CSRsTsukasa OI1-0/+138
2022-01-02Update year range in copyright notice of binutils filesAlan Modra70-70/+70
2021-12-24RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta1-0/+100
2021-12-24RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/testsVineet Gupta1-20/+0
2021-12-16arm: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford1-0/+7
2021-12-16arm: Add support for Armv8.7-A and Armv8.8-ARichard Sandiford1-0/+2
2021-12-16aarch64: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford1-40/+62
2021-12-16RISC-V: Support svinval extension with frozen version 1.0.Nelson Chu2-0/+17
2021-12-02aarch64: Add BC instructionRichard Sandiford1-1/+3
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford1-7/+25
2021-12-02aarch64: Add support for +mopsRichard Sandiford1-1/+6
2021-12-02aarch64: Add support for Armv8.8-ARichard Sandiford1-0/+3
2021-12-02aarch64: Tweak insn sequence codeRichard Sandiford1-7/+5
2021-11-30RISC-V: The vtype immediate with more than the defined 8 bits are preserved.Nelson Chu1-2/+0
2021-11-18RISC-V: Add instructions and operand set for z[fdq]inxjiawei1-0/+3
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus1-0/+1
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus1-0/+3
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus1-1/+11
2021-11-17aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus1-0/+1
2021-11-17aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus1-0/+14
2021-11-17aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus1-0/+4
2021-11-17aarch64: [SME] Add +sme option to -marchPrzemyslaw Wirkus1-0/+3
2021-11-17RISC-V: Support rvv extension with released version 1.0.Nelson Chu2-0/+1354
2021-11-16RISC-V: Scalar crypto instructions and operand set.jiawei2-0/+93
2021-11-01arm: add armv9-a architecture to -marchPrzemyslaw Wirkus1-11/+20
2021-10-24LoongArch opcodes supportliuzhensong1-0/+239
2021-10-07RISC-V: Add support for Zbs instructionsPhilipp Tomsich2-0/+25
2021-09-30aarch64: add armv9-a architecture to -marchPrzemyslaw Wirkus1-0/+5
2021-08-30RISC-V: PR27916, Support mapping symbols.Nelson Chu1-0/+7
2021-07-26PATCH [6/10] arm: Add -march=armv8.1-m.main+pacbti flagAndrea Corallo1-0/+7
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