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2019-09-17RISC-V: Gate opcode tables by enum rather than string.Jim Wilson1-3/+20
Generalize opcode arch dependencies so that we can support the overlapping B extension Zb* subsets. 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com> gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Handle insn_class enum rather than subset char string. (riscv_ip): Update call to riscv_multi_subset_supports. include/ * opcode/riscv.h (riscv_insn_class): New enum. * opcode/riscv.h (struct riscv_opcode): Change subset field to insn_class field. opcodes/ * riscv-opc.c (riscv_opcodes): Change subset field to insn_class field for all instructions. (riscv_insn_types): Likewise.
2019-08-30[ARC] [COMMITTED] Fix FASTMATH field.Claudiu Zissulescu1-1/+1
Move FASTMATH to the right enum. 2019-08-30 Claudiu Zissulescu <claziss@gmail.com> * opcode/arc.h (FASTMATH): Move it from insn_class_t to insn_subclass_t enum.
2019-08-08Update the handling of shift rotate and load/store multiple instructions in ↵Yoshinori Sato1-47/+47
the H8300 assembler. incldue * opcode/h8300.h (EXPAND_UNOP_EXTENDED_B): Add MODEL. (EXPAND_UNOP_EXTENDED_W): Likewise. (EXPAND_UNOP_EXTENDED_L): Likewise. (struct h8_opcode h8_opcodes): Likewise. (struct h8_opcode h8_opcodes): tas / ldm / stm supported H8S or later.
2019-07-24[ARC] Update ARC opcode tableClaudiu Zissulescu1-0/+2
Update ARC opcode table by cleaning up invalid instructions, and fixing wrong encodings. opcodes/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * arc-ext-tbl.h (bspeek): Remove it, added to main table. (bspop): Likewise. (modapp): Likewise. * arc-opc.c (RAD_CHK): Add. * arc-tbl.h: Regenerate. include/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * include/opcode/arc.h (FASTMATH): Add. (SWITCH): Likewise.
2019-07-16x86: fold SReg{2,3}Jan Beulich1-0/+1
They're the only exception to there generally being no mix of register kinds possible in an insn operand template, and there being two bits per operand for their representation is also quite wasteful, considering the low number of uses. Fold both bits and deal with the little bit of fallout. Also take the liberty and drop dead code trying to set REX_B: No segment register has RegRex set on it. Additionally I was quite surprised that PUSH/POP with the permitted segment registers is not covered by the test cases. Add the missing pieces.
2019-07-01[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AESMatthew Malcomson1-1/+1
I had mistakenly given all variants of the new SVE2 instructions pmull{t,b} a dependency on the feature +sve2-aes. Only the variant specifying .Q -> .D sizes should have that restriction. This patch fixes that mistake and updates the testsuite to have extra tests (matching the given set of tests per line in aarch64-tbl.h that the rest of the SVE2 tests follow). We also add a line in the documentation of the command line to clarify how to enable `pmull{t,b}` of this larger size. This is needed because all other instructions gated under the `sve2-aes` architecture extension are marked in the instruction documentation by an `HaveSVE2AES` check while pmull{t,b} is gated under the `HaveSVE2PMULL128` check. Regtested targeting aarch64-linux. gas/ChangeLog: 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> * testsuite/gas/aarch64/illegal-sve2-aes.d: Update tests. * testsuite/gas/aarch64/illegal-sve2.l: Update tests. * doc/c-aarch64.texi: Add special note of pmull{t,b} instructions under the sve2-aes architecture extension. * testsuite/gas/aarch64/illegal-sve2.s: Add small size pmull{t,b} instructions. * testsuite/gas/aarch64/sve2.d: Add small size pmull{t,b} disassembly. * testsuite/gas/aarch64/sve2.s: Add small size pmull{t,b} instructions. include/ChangeLog: 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): sve_size_013 renamed to sve_size_13. opcodes/ChangeLog: 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new sve_size_13 icode to account for variant behaviour of pmull{t,b}. * aarch64-dis-2.c: Regenerate. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new sve_size_13 icode to account for variant behaviour of pmull{t,b}. * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier. (OP_SVE_VVV_Q_D): Add new qualifier. (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier. (struct aarch64_opcode): Split pmull{t,b} into those requiring AES and those not.
2019-05-24PowerPC add initial -mfuture instruction supportPeter Bergner1-0/+18
This patch adds initial 64-bit insn assembler/disassembler support. The only instruction added is "pnop" along with the automatic aligning of prefix instruction so they do not cross 64-byte boundaries. include/ * dis-asm.h (WIDE_OUTPUT): Define. * opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare. (PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX), (PPC_PREFIX_P, PPC_PREFIX_SEG): Define. opcodes/ * ppc-dis.c (ppc_opts): Add "future" entry. (PREFIX_OPCD_SEGS): Define. (prefix_opcd_indices): New array. (disassemble_init_powerpc): Initialize prefix_opcd_indices. (lookup_prefix): New function. (print_insn_powerpc): Handle 64-bit prefix instructions. * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK), (PMRR, POWERXX): Define. (prefix_opcodes): New instruction table. (prefix_num_opcodes): New constant. binutils/ * objdump.c (disassemble_bytes): Set WIDE_OUTPUT in flags. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Handle prefix_opcodes. (struct insn_label_list): New. (insn_labels, free_insn_labels): New variables. (ppc_record_label, ppc_clear_labels, ppc_start_line_hook): New funcs. (ppc_frob_label, ppc_new_dot_label): Move functions earlier in file and call ppc_record_label. (md_assemble): Handle 64-bit prefix instructions. Align labels that are on the same line as a prefix instruction. * config/tc-ppc.h (tc_frob_label, ppc_frob_label): Move to later in the file. (md_start_line_hook): Define. (ppc_start_line_hook): Declare. * testsuite/gas/ppc/prefix-align.d, * testsuite/gas/ppc/prefix-align.s: New test. * testsuite/gas/ppc/ppc.exp: Run new test.
2019-05-16[PATCH 1/57][Arm][GAS]: Add support for +mve and +mve.fpAndre Vieira1-0/+2
bfd/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * elf32-arm.c (elf32_arm_merge_eabi_attributes): Add case for Tag_MVE_arch. binutils/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * readelf.c (arm_attr_tag_MVE_arch): New array for Tag_MVE_arch values. (arm_attr_public_tag arm_attr_public_tags): Add case for Tag_MVE_arch. elfcpp/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * arm.h (Tag_MVE_arch): Define new enum value. gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (mve_ext, mve_fp_ext): New features. (armv8_1m_main_ext_table): Add new extensions. (aeabi_set_public_attributes): Translate new features to new build attributes. (arm_convert_symbolic_attribute): Add Tag_MVE_arch. * doc/c-arm.texi: Document new extensions and new build attribute. include/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * elf/arm.h (Tag_MVE_arch): Define new enum value. * opcode/arm.h (FPU_MVE, FPU_MVE_FP): New MACROs for new features.
2019-05-09[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson1-0/+1
New operand describes a shift-left immediate encoded in bits 22:20-19:18-16 where UInt(bits) - esize == shift. This operand is useful for instructions like sshllb. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22 operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_SHLIMM_UNPRED_22. (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22 operand.
2019-05-09[binutils][aarch64] New sve_size_tsz_bhs iclass.Matthew Malcomson1-0/+1
Add sve_size_tsz_bhs iclass needed for sqxtnb and similar instructions. This iclass encodes one of three variants by the most significant bit set in a 3-bit value where only one bit may be set. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_tsz_bhs iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_tsz_bhs iclass decode.
2019-05-09[binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson1-0/+1
This includes defining a new single bit field SVE_i2h at position 20. SVE_Zm4_11_INDEX handles indexed Zn registers where the index is encoded in bits 20:11 and the register is chosed from range z0-z15 in bits 19-16. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_Zm4_11_INDEX. (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX. (fields): Handle SVE_i2h field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
2019-05-09[binutils][aarch64] New sve_shift_tsz_bhsd iclass.Matthew Malcomson1-0/+1
This new iclass encodes the variant by which is the most significant bit used of bits 23-22:20-19, where those bits are usually part of a given constant operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_shift_tsz_bhsd iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_shift_tsz_bhsd iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_shift_tsz_bhsd iclass decode.
2019-05-09[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson1-0/+2
Include a new iclass to extract the variant from the most significant 3 bits of this operand. Instructions such as rshrnb include a constant shift amount as an operand, where the most significant three bits of this operand determine what size elements the instruction is operating on. The new SVE_SHRIMM_UNPRED_22 operand denotes this constant encoded in bits 22:20-19:18-16 while the new sve_shift_tsz_hsd iclass denotes that the SVE qualifier is encoded in bits 22:20-19. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22 operand. (enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-asm.c (aarch64_ins_sve_shrimm): (aarch64_encode_variant_using_iclass): Handle sve_shift_tsz_hsd iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_shift_tsz_hsd iclass decode. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_SHRIMM_UNPRED_22. (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22 operand.
2019-05-09[binutils][aarch64] New sve_size_013 iclass.Matthew Malcomson1-0/+1
Add sve_size_013 instruction class This new iclass handles instructions such as pmullb whose size specifier can only be encoded as 0, 1, or 3. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_013 iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_013 iclass decode.
2019-05-09[binutils][aarch64] New sve_size_bh iclass.Matthew Malcomson1-0/+1
Add new iclass sve_size_bh to handle instructions that have two variants encoded with the SVE_sz field. This iclass behaves the same as the sve_size_sd iclass, but it has a nicer name for those instructions that choose between variants using the "B" and "H" size qualifiers. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_bh iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_bh iclass decode.
2019-05-09[binutils][aarch64] New sve_size_sd2 iclass.Matthew Malcomson1-0/+1
Define new sve_size_sd2 iclass to distinguish between the two variants of ldnt1sb and ldnt1sh. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_sd2 iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_sd2 iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_sd2 iclass decode. * aarch64-opc.c (fields): Handle SVE_sz2 field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
2019-05-09[binutils][aarch64] New SVE_ADDR_ZX operand.Matthew Malcomson1-0/+1
Add AARCH64_OPND_SVE_ADDR_ZX operand that allows a vector of addresses in a Zn register, offset by an Xm register. This is used with scatter/gather SVE2 instructions. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (REG_ZR): Macro specifying zero register. (parse_address_main): Account for new addressing mode [Zn.S, Xm]. (parse_operands): Handle new SVE_ADDR_ZX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_ADDR_ZX. (aarch64_print_operand): Add printing for SVE_ADDR_ZX. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
2019-05-09[binutils][aarch64] New SVE_Zm3_11_INDEX operand.Matthew Malcomson1-0/+1
Introduce new operand SVE_Zm3_11_INDEX that indicates a register between z0-z7 stored in bits 18-16 and an index stored in bits 20-19:11. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_Zm3_11_INDEX. (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX. (fields): Handle SVE_i3l and SVE_i3h2 fields. * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2 fields. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
2019-05-09[binutils][aarch64] New iclass sve_size_hsd2.Matthew Malcomson1-0/+1
Add "sve_size_hsd2" iclass decode that uses the new FLD_SVE_size field value to determine the variant of an instruction. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle sve_size_hsd2 iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_size_hsd2 iclass decode. * aarch64-opc.c (fields): Handle SVE_size field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
2019-05-09[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.Matthew Malcomson1-0/+1
New operand AARCH64_OPND_SVE_IMM_ROT3 handles a single bit rotate operand encoded at bit position 10. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_IMM_ROT3. (aarch64_print_operand): Add printing for SVE_IMM_ROT3. (fields): Handle SVE_rot3 field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
2019-05-09[binutils][aarch64] SVE2 feature extension flags.Matthew Malcomson1-0/+7
Include all feature flag macros. The "sve2" extension that enables the core sve2 instructions. This also enables the sve extension, since sve is a requirement of sve2. Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions. These are all given extra feature flags, "bitperm", "sve2-sm4", "sve2-aes", and "sve2-sha3" respectively. The sm4, aes, and sha3 extensions are explicitly marked as sve2 extensions to distinguish them from the corresponding NEON extensions. Rather than continue extending the current feature flag numbers, I used some bits that have been skipped. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c: Add command line architecture feature flags "sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm". * doc/c-aarch64.texi: Document new architecture feature flags. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_SVE2 AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM, AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New feature macros. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-tbl.h (aarch64_feature_sve2, aarch64_feature_sve2aes, aarch64_feature_sve2sha3, aarch64_feature_sve2sm4, aarch64_feature_sve2bitperm): New feature sets. (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros for feature set addresses. (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN, SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2019-05-06Add load-link, store-conditional paired EVA instructionsFaraz Shahbazker1-0/+5
Add paired load-link and store-conditional instructions to the EVA ASE for MIPS32R6[1]. These instructions are optional within the EVA ASE. Their presence is indicated by the XNP bit in the Config5 register. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 230-231, pp. 357-360. gas/ * config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6. (macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases. (mips_after_parse_args): Translate EVA to EVA_R6. * testsuite/gas/mips/ase-errors-1.s: Add new instructions. * testsuite/gas/mips/eva.s: Likewise. * testsuite/gas/mips/ase-errors-1.l: Check errors for new instructions. * testsuite/gas/mips/mipsr6@eva.d: Check new test cases. include/ * opcode/mips.h (ASE_EVA_R6): New macro. (M_LLWPE_AB, M_SCWPE_AB): New enum values. opcodes/ * mips-dis.c (mips_calculate_combination_ases): Add ISA argument and set ASE_EVA_R6 appropriately. (set_default_mips_dis_options): Pass ISA to above. (parse_mips_dis_option): Likewise. * mips-opc.c (EVAR6): New macro. (mips_builtin_opcodes): Add llwpe, scwpe. Derived from patch authored by Andrew Bennett <andrew.bennett@imgtec.com>
2019-05-01[BINUTILS, AArch64] Enable Transactional Memory ExtensionSudakshina Das1-1/+3
This patch enables the new Transactional Memory Extension added recently as part of Arm's new architecture technologies. We introduce a new optional extension "tme" to enable this. The following instructions are part of the extension: * tstart <Xt> * ttest <Xt> * tcommit * tcancel #<imm> The ISA for the above can be found here: https://developer.arm.com/docs/ddi0602/latest/base-instructions-alphabetic-order *** gas/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add case for AARCH64_OPND_TME_UIMM16. (aarch64_features): Add "tme". * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/tme-invalid.d: New test. * testsuite/gas/aarch64/tme-invalid.l: New test. * testsuite/gas/aarch64/tme-invalid.s: New test. * testsuite/gas/aarch64/tme.d: New test. * testsuite/gas/aarch64/tme.s: New test. *** include/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_TME): New. (enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16. *** opcodes/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Add case for AARCH64_OPND_TME_UIMM16. (aarch64_print_operand): Likewise. * aarch64-tbl.h (QL_IMM_NIL): New. (TME): New. (_TME_INSN): New. (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
2019-04-26[MIPS] Add load-link, store-conditional paired instructionsAndrew Bennett1-0/+4
Add several baseline MIPS32R6[1] and MIPS64R6[2] instructions that were omitted from the initial spec. These instructions are optional in implementations but not associated with any ASE or pseudo-ASE. Their presence is indicated by the XNP bit in the Config5 register. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 228-229, pp. 354-357. [2] "MIPS Architecture for Programmers Volume II-A: The MIPS64 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 289-290 and pp. 458-460. gas/ * config/tc-mips.c (macro) <M_LLWP_AB, M_LLDP_AB, M_SCWP_AB, M_SCDP_AB>: New cases and expansions for paired instructions. * testsuite/gas/mips/llpscp-32.s: New test source. * testsuite/gas/mips/llpscp-64.s: Likewise. * testsuite/gas/mips/llpscp-32.d: New test. * testsuite/gas/mips/llpscp-64.d: Likewise. * testsuite/gas/mips/mips.exp: Run the new tests. * testsuite/gas/mips/r6.s: Add new instructions to test source. * testsuite/gas/mips/r6-64.s: Likewise. * testsuite/gas/mips/r6-64-n32.d: Check new instructions. * testsuite/gas/mips/r6-64-n64.d: Likewise. * testsuite/gas/mips/r6-n32.d: Likewise. * testsuite/gas/mips/r6-n64.d: Likwwise. * testsuite/gas/mips/r6.d: Likewise. include/ * opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values. (M_SCWP_AB, M_SCDP_AB): Likewise. opcodes/ * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2019-04-25MIPS/include: opcode/mips.h: Update stale comment for CODE20 operandMaciej W. Rozycki1-2/+2
Complement commit 1586d91e32ea ("/ 0 should send SIGFPE not SIGTRAP..."), <https://sourceware.org/ml/binutils/2004-07/msg00260.html>, and update a stale comment referring the 20-bit code field of the BREAK and SDBBP instructions, by making it explicit that where permitted by choosing the MIPS32 or a later ISA the whole field can now be set with a single operand for the SDBBP instruction only. include/ * opcode/mips.h: Update comment for MIPS32 CODE20 operand.
2019-04-15[binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLIAndre Vieira1-0/+6
The patch is straightforward, it does the following: - support the new Tag_CPU_arch build attribute value, ie.: + declare the new value + update all the asserts forcing logic to be reviewed for new architectures + create a corresponding bfd_mach_arm_8_1M_MAIN enumerator in bfd and add mapping from Tag_CPU_arch to it + teach readelf about new Tag_CPU_arch value - declare armv8.1-m.main as a supported architecture value - define Armv8.1-M Mainline in terms of feature bits available - tell objdump mapping from bfd_mach_arm_8_1M_MAIN enumerator to feature bits available - update architecture-specific logic in gas and bfd guarded by the asserts mentioned above. - tests for all the above ChangeLog entries are as follows: *** bfd/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * archures.c (bfd_mach_arm_8_1M_MAIN): Define. * bfd-in2.h: Regenerate. * cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline. * elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline and update assert. (using_thumb2): Likewise. (using_thumb2_bl): Update assert. (arch_has_arm_nop): Likewise. (bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline. (tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging. *** binutils/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * readelf.c (arm_attr_tag_CPU_arch): Add entry for Armv8.1-M Mainline. *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline Tag_CPU_arch build attribute value. Reindent. (get_aeabi_cpu_arch_from_fset): Update assert. (aeabi_set_public_attributes): Update assert for Tag_DIV_use logic. * testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test. *** include/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro. (MAX_TAG_CPU_ARCH): Set value to above macro. * opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro. (ARM_AEXT_V8_1M_MAIN): Likewise. (ARM_AEXT2_V8_1M_MAIN): Likewise. (ARM_ARCH_V8_1M_MAIN): Likewise. *** ld/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * testsuite/ld-arm/attr-merge-13.attr: New test. * testsuite/ld-arm/attr-merge-13a.s: New test. * testsuite/ld-arm/attr-merge-13b.s: New test. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2019-04-11[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructionsSudakshina Das1-0/+1
This patch updates the Store allocation tags instructions in Armv8.5-A Memory Tagging Extension. This is part of the changes that have been introduced recently in the 00bet10 release All of these instructions have an updated register operand (Xt -> <Xt|SP>) - STG <Xt|SP>, [<Xn|SP>, #<simm>] - STG <Xt|SP>, [<Xn|SP>, #<simm>]! - STG <Xt|SP>, [<Xn|SP>], #<simm> - STZG <Xt|SP>, [<Xn|SP>, #<simm>] - STZG <Xt|SP>, [<Xn|SP>, #<simm>]! - STZG <Xt|SP>, [<Xn|SP>], #<simm> - ST2G <Xt|SP>, [<Xn|SP>, #<simm>] - ST2G <Xt|SP>, [<Xn|SP>, #<simm>]! - ST2G <Xt|SP>, [<Xn|SP>], #<simm> - STZ2G <Xt|SP>, [<Xn|SP>, #<simm>] - STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]! - STZ2G <Xt|SP>, [<Xn|SP>], #<simm> In order to accept <Rt|SP> a new operand type Rt_SP is introduced which has the same field as FLD_Rt but follows other semantics of Rn_SP. *** gas/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (process_omitted_operand): Add case for AARCH64_OPND_Rt_SP. (parse_operands): Likewise. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** include/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP. *** opcodes/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_print_operand): Add case for AARCH64_OPND_Rt_SP. (verify_constraints): Likewise. * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier. (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions to accept Rt|SP as first operand. (AARCH64_OPERANDS): Add new Rt_SP. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2019-04-01[GAS, Arm] CLI with architecture sensitive extensionsAndre Vieira1-7/+24
This patch adds a new framework to add architecture sensitive extensions, like GCC does. This patch also implements all architecture extensions currently available in GCC. This framework works as follows. To enable architecture sensitive extensions for a particular architecture, that architecture must contain an ARM_ARCH_OPT2 entry in the 'arm_archs' table. All fields here are the same as previous, with the addition of a new extra field at the end to <name> it's extension table. This <name>, corresponds to a <name>_ext_table of type 'struct arm_ext_table'. This struct can be filled with three types of entries: ARM_ADD (string <ext>, arm_feature_set <enable_bits>), which means +<ext> will enable <enable_bits> ARM_REMOVE (string <ext>, arm_feature_set <disable_bits>), which means +no<ext> will disable <disable_bits> ARM_EXT (string <ext>, arm_feature_set <enable_bits>, arm_feature_set <disable_bits>), which means +<ext> will enable <enable_bits> and +no<ext> will disable <disable_bits> (this is to be used instead of adding an ARM_ADD and ARM_REMOVE for the same <ext>) This patch does not disable the use of the old extensions, even if some of them are duplicated in the new tables. This is a "in-between-step" as we may want to deprecate the old table of extensions in later patches. For now, GAS will first look for the +<ext> or +no<ext> in the new table and if no entry is found it will continue searching in the old table, following old behaviour. If only an ARM_ADD or an ARM_REMOVE is defined for <ext> and +no<ext> or +<ext> resp. is used then it also continues to search the old table for it. A couple of caveats: - This patch does not enable the use of these architecture extensions with the '.arch_extension' directive. This is future work that I will tend to later. - This patch does not enable the use of these architecture extensions with the -mcpu option. This is future work that I will tend to later. - This patch does not change the current behaviour when combining an architecture extension and using -mfpu on the command-line. The current behaviour of GAS is to stage the union of feature bits enabled by both -march and -mfpu. GCC behaves differently here, so this is something we may want to revisit on a later date.
2019-03-28PR24390, Don't decode mtfsb field as a cr fieldAlan Modra1-1/+4
"mtfsb0 4*cr7+lt" doesn't make all that much sense, but unfortunately glibc uses just that instead of "mtfsb0 28" to clear the fpscr xe bit. So for backwards compatibility accept cr field expressions when assembling mtfsb operands, but disassemble to a plain number. PR 24390 include/ * opcode/ppc.h (PPC_OPERAND_CR_REG): Comment. opcodes/ * ppc-opc.c (BTF): Define. (powerpc_opcodes): Use for mtfsb*. * ppc-dis.c (print_insn_powerpc): Print fields with both PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number. gas/ * testsuite/gas/ppc/476.d: Update mtfsb*. * testsuite/gas/ppc/a2.d: Likewise.
2019-01-31S/390: Implement instruction set extensionsAndreas Krebbel1-0/+1
opcodes/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * s390-mkopc.c (main): Accept arch13 as cpu string. * s390-opc.c: Add new instruction formats and instruction opcode masks. * s390-opc.txt: Add new arch13 instructions. include/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH13. gas/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * config/tc-s390.c (s390_parse_cpu): New entry for arch13. * doc/c-s390.texi: Document arch13 march option. * testsuite/gas/s390/s390.exp: Run the arch13 related tests. * testsuite/gas/s390/zarch-arch13.d: New test. * testsuite/gas/s390/zarch-arch13.s: New test. * testsuite/gas/s390/zarch-z13.d: Expect the renamed mnemonics also for z13.
2019-01-25AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging ↵Sudi Das1-2/+0
Extension. This patch is part of a series of patches to introduce a few changes to the Armv8.5-A Memory Tagging Extension. This patch removes the LDGV and STGV instructions. These instructions needed special infrastructure to support [base]! style for addressing mode. That is also removed now. Committed on behalf of Sudakshina Das. *** gas/ChangeLog *** * config/tc-aarch64.c (parse_address_main): Remove support for [base]! address expression. (parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2. (warn_unpredictable_ldst): Remove support for ldstgv_indexed. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv and stgv. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** include/ChangeLog *** * opcode/aarch64.h (enum aarch64_opnd): Remove AARCH64_OPND_ADDR_SIMPLE_2. (enum aarch64_insn_class): Remove ldstgv_indexed. *** opcodes/ChangeLog *** * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove. * aarch64-asm.h (ins_addr_simple_2): Likeiwse. * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise. * aarch64-dis.h (ext_addr_simple_2): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): Remove case for ldstgv_indexed. (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2. * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv. (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2019-01-05RX: include - Add RXv3 support.Yoshinori Sato1-0/+32
* elf/rx.h (EF_RX_CPU_MASK): Update new bits. (E_FLAG_RX_V3): New RXv3 type. * opcode/rx.h (RX_Size): Add double size. (RX_Operand_Type): Add double FPU registers. (RX_Opcode_ID): Add new instuctions.
2019-01-01Update year range in copyright notice of binutils filesAlan Modra69-69/+69
2018-12-28PR24028, PPC_INT_FMTAlan Modra1-8/+0
PPC_INT_FMT is redundant now that bfd.h pulls in inttypes.h if available. Apparently MacOS Mojave defines int64_t as long long even though long is also 64 bits, which confuses the logic selecting PPC_INT_FMT (and BFD_PRI64 too). Hopefully inttypes.h is available on Mojave. PR 24028 include/ * opcode/ppc.h (PPC_INT_FMT): Delete. opcodes/ * ppc-dis.c (print_insn_powerpc): Replace PPC_INT_FMT uses with PRId64/PRIx64.
2018-12-06PowerPC @l, @h and @ha warnings, plus VLE e_liAlan Modra1-0/+5
This patch started off just adding the warnings in tc-ppc.c about incorrect usage of @l, @h and @ha in instructions that don't have 16-bit D-form fields. That unfortunately showed up three warnings in ld/testsuite/ld-powerpc/vle-multiseg.s on instructions like e_li r3, IV_table@l+0x00 which was being assembled to 8: 70 60 00 00 e_li r3,0 a: R_PPC_ADDR16_LO IV_table The ADDR16_LO reloc is of course completely bogus on e_li, which has a split 20-bit signed integer field in bits 0x1f7fff, the low 11 bit in 0x7ff, the next 5 bits in 0x1f0000, and the high 4 bits in 0x7800. Applying an ADDR16_LO reloc to the instruction potentially changes the e_li instruction to e_add2i., e_add2is, e_cmp16i, e_mull2i, e_cmpl16i, e_cmph16i, e_cmphl16i, e_or2i, e_and2i., e_or2is, e_lis, e_and2is, or some invalid encodings. Now there is a relocation that suits e_li, R_PPC_VLE_ADDR20, which was added 2017-09-05 but I can't see code in gas to generate the relocation. In any case, VLE_ADDR20 probably doesn't have the correct semantics for @l since ideally you'd want an @l to pair with @h or @ha to generate a 32-bit constant. Thus @l should only produce a 16-bit value, I think. So we need some more relocations to handle e_li it seems, or as I do in this patch, modify the behaviour of existing relocations when applied to e_li instructions. include/ * opcode/ppc.h (E_OPCODE_MASK, E_LI_MASK, E_LI_INSN): Define. bfd/ * elf32-ppc.c (ppc_elf_howto_raw <R_PPC_VLE_ADDR20>): Correct mask and shift value. (ppc_elf_vle_split16): Use E_OPCODE_MASK. Handle e_li specially. gas/ * config/tc-ppc.c (md_assemble): Adjust relocs for VLE before TLS tweaks. Handle e_li. Warn on unexpected operand field for lo16/hi16/ha16 relocs.
2018-12-06opcodes/riscv: Hide '.L0 ' fake symbolsAndrew Burgess1-0/+6
The RISC-V assembler generates fake labels with the name '.L0 ' as part of the debug information (see gas/config/tc-riscv.h:FAKE_LABEL_NAME). The problem is that currently, when disassembling an object file, the output looks like this (this is an example from the GDB testsuite, but is pretty representative of anything with debug information): 000000000000001e <main>: 1e: 7179 addi sp,sp,-48 20: f406 sd ra,40(sp) 22: f022 sd s0,32(sp) 24: 1800 addi s0,sp,48 0000000000000026 <.L0 >: 26: 87aa mv a5,a0 28: feb43023 sd a1,-32(s0) 2c: fcc43c23 sd a2,-40(s0) 30: fef42623 sw a5,-20(s0) 0000000000000034 <.L0 >: 34: fec42783 lw a5,-20(s0) 38: 0007871b sext.w a4,a5 3c: 678d lui a5,0x3 3e: 03978793 addi a5,a5,57 # 3039 <.LASF30+0x2a9d> 42: 02f71463 bne a4,a5,6a <.L0 > 0000000000000046 <.L0 >: 46: 000007b7 lui a5,0x0 4a: 0007b783 ld a5,0(a5) # 0 <need_malloc> 4e: 6f9c ld a5,24(a5) 0000000000000050 <.L0 >: 50: 86be mv a3,a5 52: 466d li a2,27 54: 4585 li a1,1 56: 000007b7 lui a5,0x0 5a: 00078513 mv a0,a5 5e: 00000097 auipc ra,0x0 62: 000080e7 jalr ra # 5e <.L0 +0xe> 0000000000000066 <.L0 >: 66: 4785 li a5,1 68: a869 j 102 <.L0 > 000000000000006a <.L0 >: 6a: 000007b7 lui a5,0x0 6e: 00078513 mv a0,a5 72: 00000097 auipc ra,0x0 76: 000080e7 jalr ra # 72 <.L0 +0x8> The frequent repeated '.L0 ' labels are pointless, as they are non-unique there's no way to match a use of '.L0 ' to its appearence in the output, so we'd be better off just not printing it at all. That's what this patch does by defining a 'symbol_is_valid' method for RISC-V. With this commit, the same disassembly now looks like this: 000000000000001e <main>: 1e: 7179 addi sp,sp,-48 20: f406 sd ra,40(sp) 22: f022 sd s0,32(sp) 24: 1800 addi s0,sp,48 26: 87aa mv a5,a0 28: feb43023 sd a1,-32(s0) 2c: fcc43c23 sd a2,-40(s0) 30: fef42623 sw a5,-20(s0) 34: fec42783 lw a5,-20(s0) 38: 0007871b sext.w a4,a5 3c: 678d lui a5,0x3 3e: 03978793 addi a5,a5,57 # 3039 <.LASF30+0x2a9d> 42: 02f71463 bne a4,a5,6a <.L4> 46: 000007b7 lui a5,0x0 4a: 0007b783 ld a5,0(a5) # 0 <need_malloc> 4e: 6f9c ld a5,24(a5) 50: 86be mv a3,a5 52: 466d li a2,27 54: 4585 li a1,1 56: 000007b7 lui a5,0x0 5a: 00078513 mv a0,a5 5e: 00000097 auipc ra,0x0 62: 000080e7 jalr ra # 5e <main+0x40> 66: 4785 li a5,1 68: a869 j 102 <.L5> 000000000000006a <.L4>: 6a: 000007b7 lui a5,0x0 6e: 00078513 mv a0,a5 72: 00000097 auipc ra,0x0 76: 000080e7 jalr ra # 72 <.L4+0x8> In order to share the fake label between the assembler and the libopcodes library, I've added some new defines RISCV_FAKE_LABEL_NAME and RISCV_FAKE_LABEL_CHAR in include/opcode/riscv.h. I could have just moved FAKE_LABEL_NAME to the include file, however, I thnk this would be confusing, someone working on the assembler would likely not expect to find FAKE_LABEL_NAME defined outside of the assembler source tree. By introducing the RISCV_FAKE_LABEL_* defines I can leave the assembler standard FAKE_LABEL_ defines in the assembler source, but still share the RISCV_FAKE_LABEL_* with libopcodes. gas/ChangeLog: * config/tc-riscv.h (FAKE_LABEL_NAME): Define as RISCV_FAKE_LABEL_NAME. (FAKE_LABEL_CHAR): Define as RISCV_FAKE_LABEL_CHAR. include/ChangeLog: * dis-asm.h (riscv_symbol_is_valid): Declare. * opcode/riscv.h (RISCV_FAKE_LABEL_NAME): Define. (RISCV_FAKE_LABEL_CHAR): Define. opcodes/ChangeLog: * disassembler.c (disassemble_init_for_target): Add RISC-V initialisation. * riscv-dis.c (riscv_symbol_is_valid): New function.
2018-12-03RISC-V: Accept version, supervisor ext and more than one NSE for -march.Jim Wilson1-1/+1
This patch moves all -march parsing logic into bfd, because we will use this code in ELF attributes. bfd/ * elfxx-riscv.h (RISCV_DONT_CARE_VERSION): New macro. (struct riscv_subset_t): New structure. (riscv_subset_t): New typedef. (riscv_subset_list_t): New structure. (riscv_release_subset_list): New prototype. (riscv_add_subset): Likewise. (riscv_lookup_subset): Likewise. (riscv_lookup_subset_version): Likewise. (riscv_release_subset_list): Likewise. * elfxx-riscv.c: Include safe-ctype.h. (riscv_parsing_subset_version): New function. (riscv_supported_std_ext): Likewise. (riscv_parse_std_ext): Likewise. (riscv_parse_sv_or_non_std_ext): Likewise. (riscv_parse_subset): Likewise. (riscv_add_subset): Likewise. (riscv_lookup_subset): Likewise. (riscv_lookup_subset_version): Likewise. (riscv_release_subset_list): Likewise. gas/ * config/tc-riscv.c: Include elfxx-riscv.h. (struct riscv_subset): Removed. (riscv_subsets): Change type to riscv_subset_list_t. (riscv_subset_supports): Removed argument: xlen_required and move logic into libbfd. (riscv_multi_subset_supports): Removed argument: xlen_required. (riscv_clear_subsets): Removed. (riscv_add_subset): Ditto. (riscv_set_arch): Extract parsing logic into libbfd. (riscv_ip): Update argument for riscv_multi_subset_supports and riscv_subset_supports. Update riscv_subsets due to struct definition changed. (riscv_after_parse_args): Update riscv_subsets due to struct definition changed, update and argument for riscv_subset_supports. * testsuite/gas/riscv/empty.s: New. * testsuite/gas/riscv/march-fail-rv32ef.d: Likewise. * testsuite/gas/riscv/march-fail-rv32ef.l: Likewise. * testsuite/gas/riscv/march-fail-rv32i.d: Likewise. * testsuite/gas/riscv/march-fail-rv32i.l: Likewise. * testsuite/gas/riscv/march-fail-rv32iam.d: Likewise. * testsuite/gas/riscv/march-fail-rv32iam.l: Likewise. * testsuite/gas/riscv/march-fail-rv32ic.d: Likewise. * testsuite/gas/riscv/march-fail-rv32ic.l: Likewise. * testsuite/gas/riscv/march-fail-rv32icx2p.d: Likewise. * testsuite/gas/riscv/march-fail-rv32icx2p.l: Likewise. * testsuite/gas/riscv/march-fail-rv32imc.d: Likewise. * testsuite/gas/riscv/march-fail-rv32imc.l: Likewise. * testsuite/gas/riscv/march-fail-rv64I.d: Likewise. * testsuite/gas/riscv/march-fail-rv64I.l: Likewise. * testsuite/gas/riscv/march-fail-rv64e.d: Likewise. * testsuite/gas/riscv/march-fail-rv64e.l: Likewise. * testsuite/gas/riscv/march-ok-g2.d: Likewise. * testsuite/gas/riscv/march-ok-g2p0.d: Likewise. * testsuite/gas/riscv/march-ok-i2p0.d: Likewise. * testsuite/gas/riscv/march-ok-nse-with-version.: Likewise.d * testsuite/gas/riscv/march-ok-s-with-version.d: Likewise. * testsuite/gas/riscv/march-ok-s.d: Likewise. * testsuite/gas/riscv/march-ok-sx.d: Likewise. * testsuite/gas/riscv/march-ok-two-nse.d: Likewise. * testsuite/gas/riscv/march-ok-g2_p1.d: Likewise. * testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise. include/ * opcode/riscv.h (riscv_opcode): Change type of xlen_requirement to unsigned. opcodes/ * riscv-opc.c: Change the type of xlen, because type of xlen_requirement changed.
2018-11-27RISC-V: Add .insn CA support.Jim Wilson1-0/+4
gas/ * config/tc-riscv.c (validate_riscv_insn) <'F'>: Add support for CF6 and CF2 operands. (riscv_ip) <'F'>: Likewise. * doc/c-riscv.texi (RISC-V-Formats): Add func6 abbreviation. Use rs2 instead of rs1 in CR description. Add CA docs. * gas/testsuite/riscv/insn.s: Add use of .insn ca. * gas/testsuite/riscv/insn.d: Update to match. include/ * opcode/riscv.h (OP_MASK_CFUNCT6, OP_SH_CFUNCT6): New. (OP_MASK_CFUNCT2, OP_SH_CFUNCT2): New. opcodes/ * riscv-opc.c (ciw): Fix whitespace to align columns. (ca): New.
2018-11-13[ARM] Improve indentation of ARM architecture declarationsThomas Preud'homme1-254/+281
This commit cleans up indentation of ARM architecture declaration, namely entries of arm_archs and definition of macros ARM_EXT_*, ARM_AEXT_*, ARM_AEXT2_*, FPU_EXT_*, FPU_ARCH_* and ARM_ARCH_*. It also gets rid of unused ARM_ARCH_V6M-ONLY and merge AEM_AEXT_V6M_ONLY in ARM_AEXT_V6M now sole user. gas/ 2018-11-13 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (arm_archs): Reindent. include/ 2018-11-13 Thomas Preud'homme <thomas.preudhomme@arm.com> * opcode/arm.h (ARM_AEXT_V6M_ONLY): Merge into its use in ARM_AEXT_V6M. (ARM_ARCH_V6M_ONLY): Remove. (ARM_EXT_V1, ARM_EXT_V2, ARM_EXT_V2S, ARM_EXT_V3, ARM_EXT_V3M, ARM_EXT_V4, ARM_EXT_V4T, ARM_EXT_V5, ARM_EXT_V5T, ARM_EXT_V5ExP, ARM_EXT_V5E, ARM_EXT_V5J, ARM_EXT_V6, ARM_EXT_V6K, ARM_EXT_V8, ARM_EXT_V6T2, ARM_EXT_DIV, ARM_EXT_V5E_NOTM, ARM_EXT_V6_NOTM, ARM_EXT_V7, ARM_EXT_V7A, ARM_EXT_V7R, ARM_EXT_V7M, ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR, ARM_EXT_V6_DSP, ARM_EXT_MP, ARM_EXT_SEC, ARM_EXT_OS, ARM_EXT_ADIV, ARM_EXT_VIRT, ARM_EXT2_PAN, ARM_EXT2_V8_2A, ARM_EXT2_V8M, ARM_EXT2_ATOMICS, ARM_EXT2_V6T2_V8M, ARM_EXT2_FP16_INST, ARM_EXT2_V8M_MAIN, ARM_EXT2_RAS, ARM_EXT2_V8_3A, ARM_EXT2_V8A, ARM_EXT2_V8_4A, ARM_EXT2_FP16_FML, ARM_EXT2_V8_5A, ARM_EXT2_SB, ARM_EXT2_PREDRES, ARM_CEXT_XSCALE, ARM_CEXT_MAVERICK, ARM_CEXT_IWMMXT, ARM_CEXT_IWMMXT2, FPU_ENDIAN_PURE, FPU_ENDIAN_BIG, FPU_FPA_EXT_V1, FPU_FPA_EXT_V2, FPU_MAVERICK, FPU_VFP_EXT_V1xD, FPU_VFP_EXT_V1, FPU_VFP_EXT_V2, FPU_VFP_EXT_V3xD, FPU_VFP_EXT_V3, FPU_NEON_EXT_V1, FPU_VFP_EXT_D32, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA, FPU_VFP_EXT_FMA, FPU_VFP_EXT_ARMV8, FPU_NEON_EXT_ARMV8, FPU_CRYPTO_EXT_ARMV8, CRC_EXT_ARMV8, FPU_VFP_EXT_ARMV8xD, FPU_NEON_EXT_RDMA, FPU_NEON_EXT_DOTPROD, ARM_AEXT_V1, ARM_AEXT_V2, ARM_AEXT_V2S, ARM_AEXT_V3, ARM_AEXT_V3M, ARM_AEXT_V4xM, ARM_AEXT_V4, ARM_AEXT_V4TxM, ARM_AEXT_V4T, ARM_AEXT_V5xM, ARM_AEXT_V5, ARM_AEXT_V5TxM, ARM_AEXT_V5T, ARM_AEXT_V5TExP, ARM_AEXT_V5TE, ARM_AEXT_V5TEJ, ARM_AEXT_V6, ARM_AEXT_V6K, ARM_AEXT_V6Z, ARM_AEXT_V6KZ, ARM_AEXT_V6T2, ARM_AEXT_V6KT2, ARM_AEXT_V6ZT2, ARM_AEXT_V6KZT2, ARM_AEXT_V7_ARM, ARM_AEXT_V7A, ARM_AEXT_V7VE, ARM_AEXT_V7R, ARM_AEXT_NOTM, ARM_AEXT_V6M_ONLY, ARM_AEXT_V6M, ARM_AEXT_V6SM, ARM_AEXT_V7M, ARM_AEXT_V7, ARM_AEXT_V7EM, ARM_AEXT_V8A, ARM_AEXT2_V8A, ARM_AEXT2_V8_1A, ARM_AEXT2_V8_2A, ARM_AEXT2_V8_3A, ARM_AEXT2_V8_4A, ARM_AEXT2_V8_5A, ARM_AEXT_V8M_BASE, ARM_AEXT_V8M_MAIN, ARM_AEXT_V8M_MAIN_DSP, ARM_AEXT2_V8M, ARM_AEXT2_V8M_BASE, ARM_AEXT2_V8M_MAIN, ARM_AEXT2_V8M_MAIN_DSP, ARM_AEXT_V8R, ARM_AEXT2_V8R, FPU_VFP_V1xD, FPU_VFP_V1, FPU_VFP_V2, FPU_VFP_V3D16, FPU_VFP_V3, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4, FPU_VFP_V4_SP_D16, FPU_VFP_V5D16, FPU_VFP_ARMV8, FPU_NEON_ARMV8, FPU_CRYPTO_ARMV8, FPU_VFP_HARD, FPU_FPA, FPU_ARCH_VFP, FPU_ARCH_FPE, FPU_ARCH_FPA, FPU_ARCH_VFP_V1xD, FPU_ARCH_VFP_V1, FPU_ARCH_VFP_V2, FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_NEON_V1, FPU_ARCH_VFP_V3_PLUS_NEON_V1, FPU_ARCH_NEON_FP16, FPU_ARCH_VFP_HARD, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16, FPU_ARCH_VFP_V4_SP_D16, FPU_ARCH_VFP_V5D16, FPU_ARCH_VFP_V5_SP_D16, FPU_ARCH_NEON_VFP_V4, FPU_ARCH_VFP_ARMV8, FPU_ARCH_NEON_VFP_ARMV8, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD, ARCH_CRC_ARMV8, FPU_ARCH_NEON_VFP_ARMV8_1, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1, FPU_ARCH_DOTPROD_NEON_VFP_ARMV8, ARM_ARCH_V1, ARM_ARCH_V2, ARM_ARCH_V2S, ARM_ARCH_V3, ARM_ARCH_V3M, ARM_ARCH_V4xM, ARM_ARCH_V4, ARM_ARCH_V4TxM, ARM_ARCH_V4T, ARM_ARCH_V5xM, ARM_ARCH_V5, ARM_ARCH_V5TxM, ARM_ARCH_V5T, ARM_ARCH_V5TExP, ARM_ARCH_V5TE, ARM_ARCH_V5TEJ, ARM_ARCH_V6, ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6KZ, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, ARM_ARCH_V6KZT2, ARM_ARCH_V6M, ARM_ARCH_V6SM, ARM_ARCH_V7, ARM_ARCH_V7A, ARM_ARCH_V7VE, ARM_ARCH_V7R, ARM_ARCH_V7M, ARM_ARCH_V7EM, ARM_ARCH_V8A, ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A, ARM_ARCH_V8_3A, ARM_ARCH_V8_4A, ARM_ARCH_V8_5A, ARM_ARCH_V8M_BASE, ARM_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN_DSP, ARM_ARCH_V8R): Reindent.
2018-11-12[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das1-0/+2
This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Bulk Allocation Tag instructions from MTE. These are the following instructions added in this patch: - LDGV <Xt>, [<Xn|SP>]! - STGV <Xt>, [<Xn|SP>]! This needed a new kind of operand for the new addressing [<Xn|SP>]! since this has no offset and only takes a pre-indexed version. Hence AARCH64_OPND_ADDR_SIMPLE_2 and ldtdgv_indexed are introduced. (AARCH64_OPND_ADDR_SIMPLE fulfilled the no offset criteria but does not allow writeback). We also needed new encoding and decoding functions to be able to do the same. where <Xt> : Is the 64-bit destination GPR. <Xn|SP> : Is the 64-bit first source GPR or Stack pointer. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2. (aarch64_insn_class): Add ldstgv_indexed. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-asm.c (aarch64_ins_addr_simple_2): New. * aarch64-asm.h (ins_addr_simple_2): Declare the above. * aarch64-dis.c (aarch64_ext_addr_simple_2): New. * aarch64-dis.h (ext_addr_simple_2): Declare the above. * aarch64-opc.c (operand_general_constraint_met_p): Add case for AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed. (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2. * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv. (AARCH64_OPERANDS): Define ADDR_SIMPLE_2. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add switch case for AARCH64_OPND_ADDR_SIMPLE_2 and allow [base]! for it. (warn_unpredictable_ldst): Exempt ldstgv_indexed for ldgv. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldgv and stgv. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
2018-11-12[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging ↵Sudakshina Das1-0/+8
Extension This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Tag setting instructions from MTE which consists of the following instructions: - STG [<Xn|SP>, #<simm>] - STG [<Xn|SP>, #<simm>]! - STG [<Xn|SP>], #<simm> - STZG [<Xn|SP>, #<simm>] - STZG [<Xn|SP>, #<simm>]! - STZG [<Xn|SP>], #<simm> - ST2G [<Xn|SP>, #<simm>] - ST2G [<Xn|SP>, #<simm>]! - ST2G [<Xn|SP>], #<simm> - STZ2G [<Xn|SP>, #<simm>] - STZ2G [<Xn|SP>, #<simm>]! - STZ2G [<Xn|SP>], #<simm> - STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>] - STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]! - STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm> where <Xn|SP> : Is the 64-bit GPR or Stack pointer. <simm> : Is the optional signed immediate offset, a multiple of 16 in the range -4096 to 4080, defaulting to 0. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. (aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data for AARCH64_OPND_QLF_imm_tag. (operand_general_constraint_met_p): Add case for AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. (aarch64_print_operand): Likewise. * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New. (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp for both offset and pre/post indexed versions. (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add switch case for AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. (fix_insn): Likewise. (warn_unpredictable_ldst): Exempt STGP. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g, stzg, stz2g and stgp. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
2018-11-12[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging ↵Sudakshina Das1-0/+2
Extension This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Tag generation instructions from MTE. These are the following instructions added in this patch: - IRG <Xd|SP>, <Xn|SP>{, Xm} - ADDG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2> - SUBG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2> - GMI <Xd>, <Xn|SP>, <Xm> where <Xd|SP> : Is the 64-bit destination GPR or Stack pointer. <Xn|SP> : Is the 64-bit source GPR or Stack pointer. <uimm6> : Is the unsigned immediate, a multiple of 16 in the range 0 to 1008. <uimm4> : Is the unsigned immediate, in the range 0 to 15. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3. (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New. * aarch64-opc.c (fields): Add entry for imm4_3. (operand_general_constraint_met_p): Add cases for AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10. (aarch64_print_operand): Likewise. * aarch64-tbl.h (QL_ADDG): New. (aarch64_opcode_table): Add addg, subg, irg and gmi. (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10. * aarch64-asm.c (aarch64_ins_imm): Add case for operand_need_shift_by_four. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add switch case for AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10. * testsuite/gas/aarch64/armv8_5-a-memtag.s: New. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.d: Likewise.
2018-11-12[BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-ASudakshina Das1-0/+2
This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions. Memory Tagging Extension is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch adds the new command line option and the new feature macros. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_MEMTAG): New. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-tbl.h (aarch64_feature_memtag): New. (MEMTAG, MEMTAG_INSN): New. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (aarch64_features): Add "memtag" as a new option. * doc/c-aarch64.texi: Document the same.
2018-11-06[BINUTILS, ARM] Add Armv8.5-A to select_arm_features and update macros.Sudakshina Das1-4/+3
This patch addresses the following 1) Adding ARMv8.5-A in select_arm_features. 2) Updating the feature macro so that the new ARM_EXT2_* features for Armv8.5-A are moved to ARM_AEXT2_V8_5A. *** opcodes/ChangeLog *** 2018-11-06 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (select_arm_features): Update bfd_mach_arm_8 with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML. *** include/ChangeLog *** 2018-11-06 Sudakshina Das <sudi.das@arm.com> * opcode/arm.h (ARM_ARCH_V8_5A): Move ARM_EXT2_PREDRES and ARM_EXT2_SB to ... (ARM_AEXT2_V8_5A): Here.
2018-10-09[PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRSSudakshina Das1-1/+4
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) The encodings can be found in the System Register XML. This patch adds support for the mitigation for Spectre Variant 4 by adding the PSTATE bit SSBS which are accessible using MSR and MRS instructions. Although this is a mandatory addition to the ARMv8.5-A, it is permitted to be added to any version of the ARMv8 architecture. This is enabled using the command line option of +ssbs for older versions. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_SSBS): New. (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SSBS by default. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (operand_general_constraint_met_p): Add SSBS in the check for one-bit immediate. (aarch64_sys_regs): New entry for SSBS. (aarch64_sys_reg_supported_p): New check for above. (aarch64_pstatefields): New entry for SSBS. (aarch64_pstatefield_supported_p): New check for above. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (aarch64_features): Add new "ssbs". * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/ssbs-illegal1.d: New test. * testsuite/gas/aarch64/ssbs-illegal1.l: New test. * testsuite/gas/aarch64/ssbs-illegal2.d: New test. * testsuite/gas/aarch64/ssbs-illegal2.l: New test. * testsuite/gas/aarch64/ssbs.s: New test. * testsuite/gas/aarch64/ssbs1.d: Test with +ssbs * testsuite/gas/aarch64/ssbs2.d: Test with armv8.5-a.
2018-10-09[PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registersSudakshina Das1-1/+8
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) The encodings can be found in the System Register XML. This patch adds the new system registers SCXTNUM_ELx and ID_PFR2_EL1. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New. (AARCH64_FEATURE_ID_PFR2): New. (AARCH64_ARCH_V8_5): Add both by default. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_sys_regs): New entries for scxtnum_el[0,1,2,3,12] and id_pfr2_el1. (aarch64_sys_reg_supported_p): New checks for above. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/sysreg-4.s: Test registers scxtnum_el[0,1,2,3,12] and id_pfr2_el1. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
2018-10-09[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instructionSudakshina Das1-1/+12
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/bti-branch-target-identification) The Branch Target Identification instructions (BTI) are allocated to existing HINT space, using HINT numbers 32, 34, 36, 38, such that bits[7:6] of the instruction identify the compatibility of the BTI instruction to different branches. BTI {<targets>} where <targets> one of the following, specifying which type of indirection is allowed: j : Can be a target of any BR Xn isntruction. c : Can be a target of any BLR Xn and BR {X16|X17}. jc: Can be a target of any free branch. A BTI instruction without any <targets> is the strictest of all and can not be a target of nay free branch. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_BTI): New. (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default. (aarch64_opnd): Add AARCH64_OPND_BTI_TARGET. (HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to define HINT #imm values. (HINT_OPD_JC, HINT_OPD_NULL): Likewise. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New. (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag with the hint immediate. * aarch64-opc.c (aarch64_hint_options): New entries for c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI. (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET while checking for HINT_OPD_F_NOPRINT flag. * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to extract value. * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New. (aarch64_opcode_table): Add entry for BTI. (AARCH64_OPERANDS): Add new description for BTI targets. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_bti_operand): New. (process_omitted_operand): Add case for AARCH64_OPND_BTI_TARGET. (parse_operands): Likewise. * testsuite/gas/aarch64/system.d: Update for BTI. * testsuite/gas/aarch64/bti.s: New. * testsuite/gas/aarch64/bti.d: New. * testsuite/gas/aarch64/illegal-bti.d: New. * testsuite/gas/aarch64/illegal-bti.l: New.
2018-10-09[PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructionsSudakshina Das1-0/+2
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) The encodings can be found in the System Register XML. This patch adds the following: MSR Xn, RNDR MSR Xn, RNDRRS These are optional instructions in ARMv8.5-A and hence the new +rng is added. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_RNG): New. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_sys_regs): New entries for rndr and rndrrs. (aarch64_sys_reg_supported_p): New check for above. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (aarch64_features): New "rng" option. * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/sysreg-4.s: Test both instructions. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
2018-10-09[PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instructionSudakshina Das1-1/+4
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/dc-data-cache-operation-an-alias-of-sys) This patch adds the DC CVADP instruction. Since this has a separate identification mechanism a new feature bit is added. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_CVADP): New. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp. (aarch64_sys_ins_reg_supported_p): New check for above. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/sysreg-4.s: Test instruction. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
2018-10-09[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructionsSudakshina Das1-1/+6
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order) This patch adds the prediction restriction instructions (that is, cfp, dvp, cpp). These instructions are retrospectively made optional for all versions of the architecture from ARMv8.0 to ARMv8.4 and is mandatory from ARMv8.5. Hence adding a new +predres which can be used by the older architectures. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New. (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default. (aarch64_opnd): Add AARCH64_OPND_SYSREG_SR. (aarch64_sys_regs_sr): Declare new table. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-dis.c (aarch64_ext_sysins_op): Add case for AARCH64_OPND_SYSREG_SR. * aarch64-opc.c (aarch64_print_operand): Likewise. (aarch64_sys_regs_sr): Define table. (aarch64_sys_ins_reg_supported_p): Check for RCTX with AARCH64_FEATURE_PREDRES. * aarch64-tbl.h (aarch64_feature_predres): New. (PREDRES, PREDRES_INSN): New. (aarch64_opcode_table): Add entries for cfp, dvp and cpp. (AARCH64_OPERANDS): Add new description for SYSREG_SR. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New. (parse_operands): Add entry for AARCH64_OPND_SYSREG_SR. (md_begin): Allocate and initialize aarch64_sys_regs_sr_hsh with aarch64_sys_regs_sr. (aarch64_features): Add new "predres" option for older architectures. * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/sysreg-4.s: New. * testsuite/gas/aarch64/sysreg-4.d: New. * testsuite/gas/aarch64/illegal-sysreg-4.d: New. * testsuite/gas/aarch64/illegal-sysreg-4.l: New. * testsuite/gas/aarch64/predres.s: New. * testsuite/gas/aarch64/predres.d: New.
generated by cgit v1.1 at 2024-12-11 22:25:27 +0000