Age | Commit message (Collapse) | Author | Files | Lines |
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* d30v.h: Fix declaration of reg_name_cnt.
* d10v.h: Fix declaration of d10v_reg_name_cnt.
* arc.h: Add prototypes from opcodes/arc-opc.c.
For opcodes:
* tic54x-dis.c: Add unused attributes where needed.
* z8k-dis.c (output_instr): Add unused attribute.
* h8300-dis.c: Add missing prototypes.
(bfd_h8_disassemble): Make static.
* cris-dis.c: Add missing prototype.
* h8500-dis.c: Likewise.
* m68hc11-dis.c: Likewise.
* pj-dis.c: Likewise.
* tic54x-dis.c: Likewise.
* v850-dis.c: Likewise.
* vax-dis.c: Likewise.
* w65-dis.c: Likewise.
* z8k-dis.c: Likewise.
* d10v-dis.c: Add missing prototype.
(dis_long): Remove unused variable.
(dis_2_short): Likewise.
* sh-dis.c: Add missing prototypes.
* v850-opc.c: Likewise.
Add unused attributes where needed.
* ns32k-dis.c: Add missing prototypes.
(bit_extract_simple): Remove unused variable.
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(OPCODE_IS_MEMBER): Remove gp32 parameter.
(M_MOVE): New macro identifier.
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* ppc-opc.c: Include "bfd.h".
(powerpc_operands): Add new field for reloc type.
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* include/opcode/mips.h (INSN_ISA_MASK): Nuke bits 12-15.
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* opcode/cgen.h (CGEN_INSN): Add regex support.
(build_insn_regex): Declare.
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[cgen/ChangeLog]
2001-07-11 Frank Ch. Eigler <fche@redhat.com>
* desc-cpu.scm (-gen-mach-table-defns): Emit fourth field: the
mach->cpu insn-chunk-bitsize.
(-gen-cpu-open): In @arch@_cgen_rebuild_tables, process above new
field toward CGEN_CPU_TABLE->insn_chunk_bitsize.
* mach.scm (<cpu>): New field insn-chunk-bitsize.
(-cpu-parse, -cpu-read): Parse/initialize it.
* doc/rtl.texi (define-cpu): Document it.
[opcodes/ChangeLog]
2001-07-11 Frank Ch. Eigler <fche@redhat.com>
* cgen-dis.in (print_insn): Use cgen_get_insn_value instead of
bfd_get_bits.
* cgen-opc.c (cgen_get_insn_value, cgen_put_insn_value): Respect
non-zero CGEN_CPU_DESC->insn_chunk_bitsize.
[include/opcode/ChangeLog]
2001-07-11 Frank Ch. Eigler <fche@redhat.com>
* cgen.h (CGEN_MACH): Add insn_chunk_bitsize field.
(cgen_cpu_desc): Ditto.
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* m88k.h: Clean up and reformat. Remove unused code.
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2001-06-13 Geoffrey Keating <geoffk@redhat.com>
* cgen-asm.c (cgen_parse_keyword): When looking for the
boundaries of a keyword, allow any special characters
that are actually in one of the allowed keyword.
* cgen-opc.c (cgen_keyword_add): Add any special characters
to the nonalpha_chars field.
Index: cgen/ChangeLog
2001-06-13 Geoffrey Keating <geoffk@redhat.com>
* desc.scm (<keyword> 'gen-defn): Add extra zero into
CGEN_KEYWORD_ENTRY initializers.
Index: include/opcode/ChangeLog
2001-06-13 Geoffrey Keating <geoffk@redhat.com>
* cgen.h (cgen_keyword): Add nonalpha_chars field.
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* cgen.h: Increased CGEN_MAX_SYNTAX_ELEMENTS to 48.
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cris_ver_v3p.
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* h8300.h: Fix formatting.
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64bit versions on x86-64.
* i386-dis.c (prefix_user_t): Add 'Y' to SSE ineger converison
instructions.
(putop): Handle 'Y'
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operands is greater than 127.
2001-02-02 Patrick Macdonald <patrickm@redhat.com>
* cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short.
(CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES.
(CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS.
* fr30-desc.h: Regenerate with CGEN_MAX_SYNTAX_ELEMENTS.
* m32r-desc.h: Regenerate.
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mode, 16 bit forms of ldi, ldo, ldw and stw instructions.
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* i386.h (i386_optab): Fix pusha and ret templates.
* i386-dis.c (dis386_att, disx86_64_att): Fix ret, lret and iret
templates.
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(pshufw): Remove.
(cvttpd2dq): Fix operands.
(cvttps2dq): Likewise.
(movq2q): Rename to movdq2q.
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* cgen.h (CGEN_SYNTAX_CHAR_TYPE): New typedef based on max number
of operands (unsigned char or unsigned short).
(CGEN_SYNTAX): Changed to make array CGEN_SYNTAX_CHAR_TYPE.
(CGEN_SYNTAX_CHAR): Changed to cast to unsigned char.
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* i386.h (i386_optab): Make [sml]fence template to use immext field.
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CpuUnknown): Renumber
(CpuP4, CpuSSE2): New.
(CpuUnknownFlags): Add CpuP4 and CpuSSE2
* i386.h (i386_optab): Fix 64bit pushf template; Add instructions
introduced by Pentium4
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* NEWS: Add x86_64.
* i386.h (i386_optab): Add "rex*" instructions;
add swapgs; disable jmp/call far direct instructions for
64bit mode; add syscall and sysret; disable registers for 0xc6
template. Add 'q' suffixes to extendable instructions, disable
obsoletted instructions, add new sign/zero extension ones.
(i386_regtab): Add extended registers.
(*Suf): Add No_qSuf.
(q_Suf, wlq_Suf, bwlq_Suf): New.
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(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
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mode; convert 'd' suffix to 's' or 'l'; remove all DWORD_MNEM_SUFFIX
references.
(intel_e09_1): Convert QWORD to 'l' suffix for FP operations; refuse
otherwise.
* tc-i386.h (DWORD_MNEM_SUFFIX): Kill.
(No_dSuf): Kill.
* i386.h (*_Suf): Remove No_dSuf.
(d_suf, wld_Suf,sld_Suf, sldx_Suf, bwld_Suf, d_FP, sld_FP, sldx_FP)
Remove.
(i386_optab): Remove 'd' in the suffixes.
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