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AgeCommit message (Expand)AuthorFilesLines
2016-09-26[ARC] ISA alignment.Claudiu Zissulescu1-1/+3
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford1-1/+1
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-0/+13
2016-09-21[AArch64][SVE 30/32] Add SVE instruction classesRichard Sandiford1-0/+12
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford1-0/+6
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-0/+4
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford1-0/+21
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford1-0/+7
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford1-0/+39
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford1-1/+3
2016-09-21[AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford1-0/+5
2016-09-21[AArch64][SVE 22/32] Add qualifiers for merging and zeroing predicationRichard Sandiford1-0/+3
2016-09-21[AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford1-0/+21
2016-09-21[AArch64][SVE 20/32] Add support for tied operandsRichard Sandiford1-0/+9
2016-09-21[AArch64][SVE 13/32] Add an F_STRICT flagRichard Sandiford1-1/+3
2016-09-07[arm] Automatically enable CRC instructions on supported ARMv8-A CPUs.Richard Earnshaw1-0/+2
2016-08-26Fixes to legacy ARC relocations.Cupertino Miranda1-0/+15
2016-08-01 Fix some PowerPC VLE BFD issues and add some PowerPC VLE instructions.Andrew Jenner1-0/+3
2016-07-27Begin implementing ARC NPS-400 Accelerator instructionsGraham Markall1-59/+135
2016-07-01[AArch64] Fix +nofp16 handlingSzabolcs Nagy1-4/+7
2016-06-30[ARM][GAS] ARMv8.2 should enable ARMv8.1 NEON instructions.Matthew Wahab1-1/+1
2016-06-29sparc: make SPARC_OPCODE_ARCH_MAX part of its enumTrevor Saunders1-2/+1
2016-06-28[AArch64] Make register indices be full 64-bit valuesRichard Sandiford1-3/+3
2016-06-23[ARC] Misc minor edits/fixesGraham Markall1-3/+3
2016-06-22addmore extern CTrevor Saunders1-0/+8
2016-06-22tilegx: move TILEGX_NUM_PIPELINE_ENCODINGS to tilegx_pipeline enumTrevor Saunders1-3/+1
2016-06-21Arc assembler: Convert nps400 from a machine type to an extension.Graham Markall1-1/+2
2016-06-17bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine nu...Jose E. Marchesi1-0/+6
2016-06-14Change the size field of MSP430_Opcode_Decoded to a plain integer.John Baldwin1-8/+1
2016-06-14[ARC] Add deep packet inspection instructions for npsGraham Markall1-0/+1
2016-06-09sparc: add missing comment about hyperprivileged register operandsJose E. Marchesi1-0/+2
2016-06-07[ARM] Add command line option for RAS extension.Matthew Wahab1-3/+4
2016-06-02Add support for 48 and 64 bit ARC instructions.Andrew Burgess1-1/+25
2016-06-01add more extern CTrevor Saunders8-0/+62
2016-05-26metag: add extern C to headerTrevor Saunders1-0/+8
2016-05-23[ARC] Update instruction type and delay slot info.Claudiu Zissulescu1-1/+5
2016-05-23[ARC] Rename "class" named attributes.Claudiu Zissulescu1-2/+2
2016-05-23tic54x: rename typedef of struct symbol_Trevor Saunders1-4/+4
2016-05-11Add MIPS32 DSPr3 support.Matthew Fortune1-0/+1
2016-05-10Allow extension availability to depend on several architecture bitsThomas Preud'homme1-0/+6
2016-05-10Add support for ARMv8-M security extensions instructionsThomas Preud'homme1-1/+4
2016-05-04[ARC] Add SYNTAX_NOP and SYNTAX_1OP for extension instructionsClaudiu Zissulescu1-2/+10
2016-04-28Add support to AArch64 disassembler for verifying instructions. Add verifier...Nick Clifton1-0/+3
2016-04-19opcodes/arc: Add yet more nps instructionsAndrew Burgess1-1/+1
2016-04-19opcodes/arc: Add more nps instructionsAndrew Burgess1-0/+2
2016-04-14arc/nps400 : New cmem instructions and associated relocationAndrew Burgess1-0/+3
2016-04-12Add support for .extCondCode, .extCoreRegister and .extAuxRegister.Claudiu Zissulescu1-3/+21
2016-04-12Add support for .extInstruction pseudo-op.Claudiu Zissulescu1-1/+50
2016-04-05[ARC] Fix support for double assist instructions.Claudiu Zissulescu1-2/+9
2016-04-05[ARC] 24 bit reloc and overflow detection fix.Claudiu Zissulescu1-1/+16
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