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2000-09-22Fix ia64 gas testsuite. Update ia64 DV tables. Fix ia64 gas testsuite again.Jim Wilson2-1/+7
gas/ChangeLog * config/tc-ia64.c (dv_sem): Add "stop". (specify_resource, case IA64_RS_PR): Only handles regs 1 to 15 now. (specify_resource, case IA64_RS_PRr): New for regs 16 to 62. (specify_resource, case IA64_RS_PR63): Reorder (note == 7) test to match above. (mark_resources): Check IA64_RS_PRr. gas/testsuite/ChangeLog * gas/ia64/dv-raw-err.s: Add new testcases for PR%, 16 - 62. * gas/ia64/dv-waw-err.s: Likewise. * gas/ia64/dv-imply.d: Regenerate. * gas/ia64/dv-mutex.d, gas/ia64/dv-raw-err.l, gas/ia64/dv-safe.d, gas/ia64/dv-srlz.d, gas/ia64/dv-war-err.l, gas/ia64/dv-waw-err.l, gas/ia64/opc-f.d, gas/ia64/opc-i.d, gas/ia64/opc-m.d: Likewise. include/opcode/ChangeLog * ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP. opcodes/ChangeLog * ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change. * ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP. (lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62". * ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update. * ia64-asmtab.c: Regnerate.
2000-09-14Add support for the MIPS32Nick Clifton2-17/+58
2000-09-05doco addition.Alan Modra2-1/+7
2000-08-16Fix 3 DV bugs, and a few minor cleanups.Jim Wilson2-1/+6
gas/ * config/tc-ia64.c (specify_resource, case IA64_RS_GR): Handle postincrement modified registers. Handle IA64_OPND_R3_2 addl source registers. (note_register_values): Handle IA64_OPND_R3_2 operands. gas/testsuite/ * gas/ia64/dv-raw-err.s: Add new tests for addl and postinc. * gas/ia64/dv-raw-err.l: Likewise. * gas/ia64/dv-waw-err.l: Update sed pattern. * gas/ia64/opc-f.pl: Delete fpsub, and fpadd comment. * gas/ia64/opc-f.s, gas/ia64/opc-f.d: Regenerate. include/opcode/ * ia64.h (IA64_OPCODE_POSTINC): New. opcodes/ * ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds. Delete break, mov-immediate, nop. * ia64-opc-f.c: Delete fpsub instructions. * ia64-opc-m.c: Add POSTINC to all instructions with postincrement address operand. Rewrite using macros to avoid long lines. * ia64-opc.h (POSTINC): Define. * ia64-asmtab.c: Regenerate.
2000-08-162000-08-15 H.J. Lu <hjl@gnu.org>H.J. Lu2-2/+7
* i386.h: Swap the Intel syntax "movsx"/"movzx" due to the IgnoreSize change.
2000-08-09gas:Jason Eckhardt1-29/+29
2000-08-08 Jason Eckhardt <jle@cygnus.com> * config/tc-i860.h: Rework completely for BFD_ASSEMBLER. (i860_fix_info): New enum. (MD_APPLY_FIX3): Define. (WORKING_DOT_WORD): Define. (TC_HANDLES_FX_DONE): Define. (DIFF_EXPR_OK): Define. (LISTING_HEADER): Define. (TARGET_FORMAT): Select target format based on endian flag. (TARGET_BYTES_BIG_ENDIAN): Default to little endian. (target_big_endian): Add external declaration. * config/tc-i860.c: All existing code reworked completely. Other new code shown below. (SYNTAX_SVR4): Define. (target_warn_expand): New variable. (md_shortopts): Declare and define (-Qy, -Qn, and -V options). (md_longopts): Declare and define with new options (-EL, -EB, and -mwarn-expand). (md_show_usage): New function. (md_operand): New function. (obtain_reloc_for_imm16): New function. (md_apply_fix3): New function. (tc_gen_reloc): New function. include: 2000-08-08 Jason Eckhardt <jle@cygnus.com> * opcode/i860.h: Small formatting adjustments. opcode: 2000-08-08 Jason Eckhardt <jle@cygnus.com> * i860-dis.c (print_br_address): Change third argument from int to long. bfd: 2000-08-08 Jason Eckhardt <jle@cygnus.com> * elf32-i860.c (elf32_i860_howto_table): Updated some fields.
2000-08-06 * avr.h (AVR_UNDEF_P, AVR_SKIP_P, AVR_DISP0_P): New macros.Denis Chertykov2-24/+79
Move related opcodes closer to each other. Minor changes in comments, list undefined opcodes.
2000-07-282000-07-22 Jason Eckhardt <jle@cygnus.com>Jason Eckhardt1-300/+306
* include/opcode/i860.h (btne, bte, bla): Changed these opcodes to use sbroff ('r') instead of split16 ('s'). (J, K, L, M): New operand types for 16-bit aligned fields. (ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to use I, J, K, L, M instead of just I. (T, U): New operand types for split 16-bit aligned fields. (st.x): Changed these opcodes to use S, T, U instead of just S. (andh, andnoth, orh, xorh): Deleted 3-register forms as they do not exist on the i860. (pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860. (pfeq.ss, pfeq.dd): New opcodes. (st.s): Fixed incorrect mask bits. (fmlow): Fixed incorrect mask bits. (fzchkl, pfzchkl): Fixed incorrect mask bits. (faddz, pfaddz): Fixed incorrect mask bits. (form, pform): Fixed incorrect mask bits. (pfld.l): Fixed incorrect mask bits. (fst.q): Fixed incorrect mask bits. (all floating point opcodes): Fixed incorrect mask bits for handling of dual bit. * include/elf/i860.h: New file. (elf_i860_reloc_type): Defined ELF32 i860 relocations. * bfd/cpu-i860.c: Added comments. * bfd/elf32-i860.c (TARGET_LITTLE_SYM): Defined to bfd_elf32_i860_little_vec. (TARGET_LITTLE_NAME): Defined to "elf32-i860-little". (ELF_MAXPAGESIZE): Changed to 4096. * bfd/targets.c (bfd_elf32_i860_little_vec): Declaration of new target. (bfd_target_vector): Added bfd_elf32_i860_little_vec. * bfd/config.bfd (i860-stardent-sysv4*, i860-stardent-elf*): Added config for little endian elf32 i860. (targ_defvec): Define for the new config above as "bfd_elf32_i860_little_vec". (targ_selvecs): Define for the new config above as "bfd_elf32_i860_vec bfd_elf32_i860_little_vec" * bfd/configure.in (bfd_elf32_i860_little_vec): Added recognition of new target vec. * bfd/configure: Regenerated. * opcodes/i860-dis.c: New file. (print_insn_i860): New function. (print_br_address): New function. (sign_extend): New function. (BITWISE_OP): New macro. (I860_REG_PREFIX): New macro. (grnames, frnames, crnames): New structures. * opcodes/disassemble.c (ARCH_i860): Define. (disassembler): Add check for bfd_arch_i860 to set disassemble function to print_insn_i860. * include/dis-asm.h (print_insn_i860): Add prototype. * opcodes/Makefile.in (CFILES): Added i860-dis.c. (ALL_MACHINES): Added i860-dis.lo. (i860-dis.lo): New dependences. * opcodes/configure.in: New bits for bfd_i860_arch. * opcodes/configure: Regenerated.
2000-07-262000-07-26 Dave Brolley <brolley@redhat.com>Dave Brolley2-1/+5
* cgen.h (cgen_hw_lookup_by_num): Second parameter is unsigned.
2000-07-20 cris.h: New file.Hans-Peter Nilsson2-0/+302
2000-06-27Applied Marek Michalkiewicz <marekm@linux.org.pl>'s patch to ehance the AVR ↵Nick Clifton2-11/+20
port.
2000-06-19Applied Stephane Carrez <Stephane.Carrez@worldnet.fr> patches to add supportNick Clifton3-1/+423
for m68hc11 and m68hc12 processors.
2000-06-09 * avr.h: clr,lsl,rol, ... moved after add,adc, ...Denis Chertykov2-5/+9
2000-06-07 * avr.h: New file with AVR opcodes.Denis Chertykov2-0/+211
2000-05-25Define the ALONE flag bit, for use in the opcode table.Donald Lindsay2-0/+5
2000-05-23Allow d suffix on iretAlan Modra2-2/+7
2000-05-17Fix fild.Alan Modra2-3/+7
2000-05-16* cgen/opcodes fixFrank Ch. Eigler2-4/+27
* approved by nickc [opcodes/ChangeLog] 2000-05-16 Frank Ch. Eigler <fche@redhat.com> * fr30-desc.h: Partially regenerated to account for changed CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros. * m32r-desc.h: Ditto. [include/opcode/ChangeLog] 2000-05-16 Frank Ch. Eigler <fche@redhat.com> * cgen.h (CGEN_MAX_SYNTAX_BYTES): Increase to 32. Check that it exceeds CGEN_ACTUAL_MAX_SYNTAX_BYTES, if set. (CGEN_MAX_IFMT_OPERANDS): Increase to 16. Check that it exceeds CGEN_ACTUAL_MAX_IFMT_OPERANDS, if set.
2000-05-13Fix cpu_flags for sys{enter,exit} fx{save,restore}Alan Modra2-5/+9
2000-05-13`.arch cpu_type' pseudo for x86.Alan Modra2-774/+805
2000-05-06Support for tic54x target.Timothy Wall2-0/+171
2000-05-03* ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit.J.T. Conklin2-0/+13
(PPC_OPERAND_VR): New operand flag for vector registers.
2000-05-01 * h8300.h (EOP): Add missing initializer.Jeff Law2-1/+5
2000-04-21 * hppa.h (pa_opcodes): New opcodes for PA2.0 wide modeJeff Law2-25/+44
forms of ld/st{b,h,w,d} and fld/fst{w,d} (16-bit displacements). New operand types l,y,&,fe,fE,fx added to support above forms. (pa_opcodes): Replaced usage of 'x' as source/target for floating point double-word loads/stores with 'fx'. Fr
2000-04-21IA-64 ELF support.Jim Wilson2-0/+395
2000-03-27Fix value of SHORT_A1.Nick Clifton2-15/+21
Move SHORT_AR to end of list of short instructions.
2000-03-26Mostly cosmetic. Fixes to comments. Don't start as_bad and as_warnAlan Modra2-62/+80
messages with capital. Don't malign Unixware, malign SysV386 instead.
2000-03-02Apply patch for 100679Nick Clifton2-35/+56
2000-02-25Extend the i386 gas testsuite to do some tests for intel_syntax. Fix allAlan Modra2-2/+7
the errors exposed by this addition. These were intel mode "fi... word ptr", "fi... dword ptr", "jmp Imm seg, Imm offset", "out dx,al". The failure with intel "out dx,al" was also present in att "out al,dx". Extend testsuite to catch this case too.
2000-02-24Rename 'flags' to 'signed_overflow_ok_p'Nick Clifton2-9/+8
2000-02-242000-02-24 Andrew Haley <aph@cygnus.com>Andrew Haley2-1/+27
* cgen.h (CGEN_INSN_MACH_HAS_P): New macro. (CGEN_CPU_TABLE): flags: new field. Add prototypes for new functions.
2000-02-24Forgot Changelog for last i386.h change.Alan Modra1-0/+4
2000-02-24Correct intel_syntax fsub* and fdiv* handling. Oh, how I'd like to be ridAlan Modra1-4/+9
of UNIXWARE_COMPAT.
2000-02-23Add IBM 370 support.Alan Modra2-0/+269
2000-02-22 * opcode/d30v.h (FLAG_NOT_WITH_ADDSUBppp): Redefined as operation cannotChandra Chavva1-1/+3
be combined in parallel with ADD/SUBppp.
2000-02-22g2000-02-22 Andrew Haley <aph@cygnus.com>Andrew Haley2-1/+8
* mips.h: (OPCODE_IS_MEMBER): Add comment.
2000-02-22ChangeLog change only.Andrew Haley1-1/+3
2000-02-221999-12-30 Andrew Haley <aph@cygnus.com>Andrew Haley2-2/+10
* mips.h (OPCODE_IS_MEMBER): Add gp32 arg.
2000-01-15Cosmetic changes to tc-i386.[ch] + extend x86 gas testsuite jmp andAlan Modra2-2/+6
call tests + tweak intel mode far call and jmp.
1999-12-27x86 indirect jump/call syntax fixes. Disassembly fix for lcall.Alan Modra2-2/+10
1999-12-01 * mn10300.h: Add new operand types. Add new instruction formats.Jeff Law2-0/+27
1999-11-25 * hppa.h (pa_opcodes): Correctly handle immediate for PA2.0 "bb"Jeff Law2-2/+10
instruction.
1999-11-18For include/opcode:Gavin Romig-Koch2-0/+5
* mips.h (INSN_ISA5): New. For opcodes: * mips-opc.c (I5): New. (abs.ps,add.ps,alnv.ps,c.COND.ps,cvt.s.pl,cvt.s.pu,cvt.ps.s madd.ps,movf.ps,movt.ps,mul.ps,net.ps,nmadd.ps,nmsub.ps, pll.ps,plu.ps,pul.ps,puu.ps,sub.ps,suxc1,luxc1): New.
1999-11-01For include/opcode:Gavin Romig-Koch2-0/+22
* mips.h (OPCODE_IS_MEMBER): New. For gas: * config/tc-mips.c (macro_build): Use OPCODE_IS_MEMBER. (mips_ip): Use OPCODE_IS_MEMBER. For opcodes: * mips-dis.c (_print_insn_mips): Use OPCODE_IS_MEMBER.
1999-10-29Define SHORT_AR (fix for CR: 101340)Nick Clifton2-0/+5
1999-10-18Add md expression support; Cleanup alpha warningsMichael Meissner2-2/+7
1999-10-10 * hppa.h (pa_opcodes): Add load and store cache control toJeff Law2-75/+123
instructions. Add ordered access load and store. * hppa.h (pa_opcode): Add new entries for addb and addib. * hppa.h (pa_opcodes): Fix cmpb and cmpib entries. * hppa.h (pa_opcodes): Add entries for cmpb and cmpib.
1999-10-07Added seven new instructions ld, ld2w, sac, sachi, slae, st andDiego Novillo2-0/+8
st2w for d10v. Created new testsuite for d10v to verify new instructions.
1999-09-23Add missing initializer lost in last change.Jeff Law1-1/+1
1999-09-23 * hppa.h (pa_opcodes): Add "call" and "ret". Clean up "b", "bve"Jeff Law2-17/+29
and "be" using completer prefixes.
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