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2016-07-01[AArch64] Fix +nofp16 handlingSzabolcs Nagy1-4/+7
2016-06-30[ARM][GAS] ARMv8.2 should enable ARMv8.1 NEON instructions.Matthew Wahab1-1/+1
2016-06-29sparc: make SPARC_OPCODE_ARCH_MAX part of its enumTrevor Saunders1-2/+1
2016-06-28[AArch64] Make register indices be full 64-bit valuesRichard Sandiford1-3/+3
2016-06-23[ARC] Misc minor edits/fixesGraham Markall1-3/+3
2016-06-22addmore extern CTrevor Saunders1-0/+8
2016-06-22tilegx: move TILEGX_NUM_PIPELINE_ENCODINGS to tilegx_pipeline enumTrevor Saunders1-3/+1
2016-06-21Arc assembler: Convert nps400 from a machine type to an extension.Graham Markall1-1/+2
2016-06-17bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine nu...Jose E. Marchesi1-0/+6
2016-06-14Change the size field of MSP430_Opcode_Decoded to a plain integer.John Baldwin1-8/+1
2016-06-14[ARC] Add deep packet inspection instructions for npsGraham Markall1-0/+1
2016-06-09sparc: add missing comment about hyperprivileged register operandsJose E. Marchesi1-0/+2
2016-06-07[ARM] Add command line option for RAS extension.Matthew Wahab1-3/+4
2016-06-02Add support for 48 and 64 bit ARC instructions.Andrew Burgess1-1/+25
2016-06-01add more extern CTrevor Saunders8-0/+62
2016-05-26metag: add extern C to headerTrevor Saunders1-0/+8
2016-05-23[ARC] Update instruction type and delay slot info.Claudiu Zissulescu1-1/+5
2016-05-23[ARC] Rename "class" named attributes.Claudiu Zissulescu1-2/+2
2016-05-23tic54x: rename typedef of struct symbol_Trevor Saunders1-4/+4
2016-05-11Add MIPS32 DSPr3 support.Matthew Fortune1-0/+1
2016-05-10Allow extension availability to depend on several architecture bitsThomas Preud'homme1-0/+6
2016-05-10Add support for ARMv8-M security extensions instructionsThomas Preud'homme1-1/+4
2016-05-04[ARC] Add SYNTAX_NOP and SYNTAX_1OP for extension instructionsClaudiu Zissulescu1-2/+10
2016-04-28Add support to AArch64 disassembler for verifying instructions. Add verifier...Nick Clifton1-0/+3
2016-04-19opcodes/arc: Add yet more nps instructionsAndrew Burgess1-1/+1
2016-04-19opcodes/arc: Add more nps instructionsAndrew Burgess1-0/+2
2016-04-14arc/nps400 : New cmem instructions and associated relocationAndrew Burgess1-0/+3
2016-04-12Add support for .extCondCode, .extCoreRegister and .extAuxRegister.Claudiu Zissulescu1-3/+21
2016-04-12Add support for .extInstruction pseudo-op.Claudiu Zissulescu1-1/+50
2016-04-05[ARC] Fix support for double assist instructions.Claudiu Zissulescu1-2/+9
2016-04-05[ARC] 24 bit reloc and overflow detection fix.Claudiu Zissulescu1-1/+16
2016-03-29[ARC] Add support for Quarkse opcodes.Claudiu Zissulescu1-0/+72
2016-03-22make more variables constTrevor Saunders2-2/+2
2016-03-21arc/nps400: Add first nps400 instructionsAndrew Burgess1-0/+1
2016-03-21arc/opcodes: Use flag operand class to handle multiple flag matchesAndrew Burgess1-9/+9
2016-03-21arc: Add nps400 machine type, and assembler flag.Andrew Burgess1-0/+1
2016-03-21arc/gas: default mach is arc700, initialised in md_beginAndrew Burgess1-5/+0
2016-03-08[ARC] Allow non-instruction relocations within .text sectionsClaudiu Zissulescu1-2/+2
2016-03-07Add const qualifiers at various places.Trevor Saunders8-17/+17
2016-03-04[ARM] Add feature check for ARMv8.1 AdvSIMD instructions.Matthew Wahab1-1/+2
2016-02-19[ARM] Add FP16 feature extension for ARMv8.2 architectureJiong Wang1-1/+2
2016-02-10Add support for ARC instruction relaxation in the assembler.Claudiu Zissulescu1-0/+8
2016-02-09Fix compile time warnings building the binutils with a gcc6 compiler.Nick Clifton3-7/+8
2016-02-04Fix the encoding of the MSP430's RRUX instruction.Nick Clifton1-5/+10
2016-01-19Add PIC and TLS support to the ARC target.Miranda Cupertino1-0/+16
2016-01-06MIPS/include: opcode/mips.h: Add a summary of MIPS16 operand codesMaciej W. Rozycki1-0/+6
2016-01-01Copyright update for binutilsAlan Modra68-69/+68
2016-01-01binutils ChangeLog rotationAlan Modra1-0/+0
2015-12-30Fix assorted ChangeLog errorsAlan Modra1-8/+127
2015-12-24Add assembler support for ARMv8-M BaselineThomas Preud'homme2-21/+57
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