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2013-11-112013-11-11 Catherine Moore <clm@codesourcery.com>Catherine Moore1-2/+2
gas/ * config/mips/tc-mips.c (convert_reg_type): Use INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY. (reg_needs_delay): Likewise. (insns_between): Likewise. include/ * opcode/mips.h (INSN_LOAD_MEMORY_DELAY): Rename to... (INSN_LOAD_MEMORY): ...this. opcodes/ * mips-dis.c (print_insn_mips): Use INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY. (print_insn_micromips): Likewise. * mips-opc.c (LDD): Remove. (CLD): Include INSN_LOAD_MEMORY. (LM): New. (mips_builtin_opcodes): Use LM instead of LDD. Add LM to load instructions.
2013-11-05gas/Yufeng Zhang2-1/+16
* config/tc-aarch64.c (parse_sys_reg): Update to use aarch64_sys_reg; call aarch64_sys_reg_deprecated_p and warn about the deprecated system registers. gas/testsuite/ * gas/aarch64/deprecated.d: New file. * gas/aarch64/deprecated.l: New file. * gas/aarch64/deprecated.s: New file. * gas/aarch64/sysreg-1.s: Add tests. * gas/aarch64/sysreg-1.d: Add tests. include/opcode/ * aarch64.h (aarch64_sys_reg): New typedef. (aarch64_sys_regs): Change to define with the new type. (aarch64_sys_reg_deprecated_p): Declare. opcodes/ * aarch64-opc.c (F_DEPRECATED): New macro. (aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with F_DEPRECATED. (aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on AARCH64_OPND_SYSREG.
2013-11-05gas/Yufeng Zhang2-0/+7
* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_COND1. gas/testsuite/ * gas/aarch64/alias.s: Add tests. * gas/aarch64/alias.d: Update. * gas/aarch64/no-aliases.d: Update. * gas/aarch64/diagnostic.s: Add tests. * gas/aarch64/diagnostic.l: Update. * gas/aarch64/illegal.s: Add tests. * gas/aarch64/illegal.l: Update. include/opcode/ * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND. (enum aarch64_opnd): Add AARCH64_OPND_COND1. opcodes/ * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'. (convert_from_csel): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): Handle AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1. (aarch64_print_operand): Handle AARCH64_OPND_COND1. * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of COND for cinc, cset, cinv, csetm and cneg. (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1. * aarch64-asm-2.c: Re-generated. * aarch64-dis-2.c: Ditto. * aarch64-opc-2.c: Ditto.
2013-10-142013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>Chao-ying Fu2-7/+89
* mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX. (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL. For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. For MIPS, update extension character sequences after +. (ASE_MSA): New define. (ASE_MSA64): New define. For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. For microMIPS, update extension character sequences after +.
2013-10-11 * Removed short_hand field from opcode table andSean Keys1-36/+16
refactored assembler/disassember accordingly. Testsuite checkout OK.
2013-08-23 PR binutils/15834Nick Clifton2-3/+8
Fix typos: --- bfd/bfdio.c | 2 +- bfd/elf32-spu.c | 2 +- bfd/elfnn-aarch64.c | 2 +- binutils/od-xcoff.c | 2 +- config/tcl.m4 | 2 +- gas/config/tc-ia64.c | 2 +- gas/config/tc-sparc.c | 2 +- gas/config/tc-z80.c | 12 ++++++------ gas/doc/c-i386.texi | 6 +++--- gas/doc/c-m32r.texi | 2 +- gas/testsuite/gas/d10v/instruction_packing.d | 2 +- gas/testsuite/gas/z80/atend.d | 2 +- gold/object.h | 2 +- include/gdb/remote-sim.h | 2 +- include/opcode/ChangeLog | 2 +- include/opcode/i960.h | 2 +- ld/testsuite/ld-mips-elf/mips16-pic-1.inc | 2 +- opcodes/aarch64-asm.c | 2 +- opcodes/aarch64-dis.c | 2 +- opcodes/msp430-dis.c | 2 +-
2013-08-19include/opcode/Richard Sandiford2-4/+6
* mips.h: Remove references to "+I" and imm2_expr. gas/ * config/tc-mips.c (imm2_expr): Delete. (md_assemble, match_insn, imm2_expr.X_op, mips_ip): Update accordingly.
2013-08-19include/opcode/Richard Sandiford2-2/+4
* mips.h (M_DEXT, M_DINS): Delete. opcodes/ * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins" macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases. Use +H rather than +C for the real "dext". * mips-opc.c (mips_builtin_opcodes): Likewise. gas/ * config/tc-mips.c (report_bad_range, report_bad_field): Delete. (macro): Remove M_DEXT and M_DINS handling. gas/testsuite/ * gas/mips/ext-ill.l, gas/mips/mips64r2-ill.l: Expect DEXT and DINS error messages to have the same form as the EXT and INS ones. * gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d, gas/mips/micromips.d, gas/mips/micromips@mips64r2.d, gas/mips/mips64r2.d: Expect "dext" and "dins" instead of "dextm", "dextu", "dinsm" and "dinsu".
2013-08-19include/opcode/Richard Sandiford2-0/+18
* mips.h (OP_OPTIONAL_REG): New mips_operand_type. (mips_optional_operand_p): New function. opcodes/ * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros. * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG and OPTIONAL_MAPPED_REG. * mips-opc.c (decode_mips_operand): Likewise. * mips16-opc.c (decode_mips16_operand): Likewise. * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG. gas/ * config/tc-mips.c (operand_reg_mask, match_operand): Handle OP_OPTIONAL_REG. (mips_ip, mips16_ip): Use mips_optional_operand_p to check for optional operands.
2013-08-05gas/Eric Botcazou1-0/+1
* config/tc-sparc.c (sparc_arch_types): Add leon. (sparc_arch): Move sparc4 around and add leon. (sparc_target_format): Document -Aleon. * doc/c-sparc.texi: Likewise. include/ * opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_LEON. opcodes/ * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for bfd_mach_sparc. * sparc-opc.c (MASK_LEON): Define. (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON. (letandleon): New macro. (v9andleon): Likewise. (sparc_opc): Add leon. (umac): Enable for letandleon. (smac): Likewise. (casa): Enable for v9andleon. (cas): Likewise. (casl): Likewise.
2013-08-04include/opcode/Richard Sandiford2-6/+59
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> Richard Sandiford <rdsandiford@googlemail.com> * mips.h: Document new VU0 operand characters. (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types. (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R) (OP_REG_R5900_ACC): New mips_reg_operand_types. (INSN2_VU0_CHANNEL_SUFFIX): New macro. (mips_vu0_channel_mask): Declare. opcodes/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> Richard Sandiford <rdsandiford@googlemail.com> * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC. (print_vu0_channel): New function. (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. (print_insn_args): Handle '#'. (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX. * mips-opc.c (mips_vu0_channel_mask): New constant. (decode_mips_operand): Handle new VU0 operand types. (VU0, VU0CH): New macros. (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E" for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2. Use "+6" rather than "G" for QMFC2 and QMTC2. gas/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> Richard Sandiford <rdsandiford@googlemail.com> * config/tc-mips.c (MAX_OPERANDS): Bump to 6. (RWARN): Bump to 0x8000000. (RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R) (RTYPE_R5900_ACC): New register types. (RTYPE_MASK): Include them. (R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New macros. (reg_names): Include them. (mips_parse_register_1): New function, split out from... (mips_parse_register): ...here. Add a channels_ptr parameter. Look for VU0 channel suffixes when nonnull. (reg_lookup): Update the call to mips_parse_register. (mips_parse_vu0_channels): New function. (OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types. (mips_operand_token): Add a "channels" field to the union. Extend the comment above "ch" to OT_DOUBLE_CHAR. (mips_parse_base_start): Match -- and ++. Handle channel suffixes. (mips_parse_argument_token): Handle channel suffixes here too. (validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX. Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits. Handle '#' formats. (md_begin): Register $vfN and $vfI registers. (operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. (convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC. (match_vu0_suffix_operand): New function. (match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. (macro): Use "+7" rather than "E" for LDQ2 and STQ2. (mips_lookup_insn): New function. (mips_ip): Use it. Allow "+K" operands to be elided at the end of an instruction. Handle '#' sequences. gas/testsuite/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> * gas/mips/r5900-vu0.d: Expect $vfN and $viN instead of numeric coprocessor registers. * gas/mips/r5900-all-vu0.s, gas/mips/r5900-all-vu0.d, gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d, gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l: New tests. * gas/mips/mips.exp: Run them.
2013-08-03include/opcode/Richard Sandiford2-11/+30
* mips.h (mips_pcrel_operand): Inherit from mips_int_operand. (mips_int_operand_min, mips_int_operand_max): New functions. (mips_decode_pcrel_operand): Use mips_decode_int_operand. opcodes/ * mips-formats.h (PCREL): Reorder parameters and update the definition to match new mips_pcrel_operand layout. (JUMP, JALX, BRANCH): Update accordingly. * mips16-opc.c (decode_mips16_operand): Likewise. gas/ * config/tc-mips.c (match_int_operand): Use mips_int_operand_min and mips_int_operand_max. (mips16_immed_operand, mips16_immed_operands, MIPS16_NUM_IMMED): Delete. (mips16_immed_operand, mips16_immed_in_range_p): New functions. (mips16_immed, mips16_extended_frag): Use them. Use mips_int_operand instead of mips16_immed_operand.
2013-08-01include/opcode/Richard Sandiford2-121/+88
* mips.h (mips_decode_reg_operand): New function. (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL) (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4) (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI): New macros. (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D) (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T) (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S) (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z) (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D) (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD) (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG) (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP) (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP) (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other macros to cover the gaps. (INSN2_MOD_SP): Replace with... (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros. (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z) (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y) (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z) (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X): Delete. opcodes/ * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): New macros. (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R) (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete. (mips_builtin_opcodes): Use the new position-based read-write flags instead of field-based ones. Use UDI for "udi..." instructions. * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): New macros. (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete. (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags. (WR_SP, RD_16): New macros. (RD_SP): Redefine as an INSN2_* flag. (MOD_SP): Redefine in terms of RD_SP and WR_SP. (mips16_opcodes): Use the new position-based read-write flags instead of field-based ones. Use RD_16 for "nop". Move RD_SP to pinfo2 field. * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): New macros. (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj) (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D) (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete. (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP. (micromips_opcodes): Use the new position-based read-write flags instead of field-based ones. * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand. (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead of field-based flags. gas/ * config/tc-mips.c (MAX_OPERANDS): New macro. (mips_operand_array): New structure. (mips_operands, mips16_operands, micromips_operands): New arrays. (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map) (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map) (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map) (micromips_to_32_reg_q_map): Delete. (insn_operands, insn_opno, insn_extract_operand): New functions. (validate_mips_insn): Take a mips_operand_array as argument and use it to build up a list of operands. Extend to handle INSN_MACRO and MIPS16. (validate_mips16_insn): New function. (validate_micromips_insn): Take a mips_operand_array as argument. Handle INSN_MACRO. (md_begin): Initialize mips_operands, mips16_operands and micromips_operands. Call validate_mips_insn and validate_micromips_insn for macro instructions too. Call validate_mips16_insn for MIPS16 instructions. (insn_read_mask, insn_write_mask, operand_reg_mask, insn_reg_mask): New functions. (gpr_read_mask, gpr_write_mask, fpr_read_mask, fpr_write_mask): Use them. Handle INSN_UDI. (get_append_method): Use gpr_read_mask.
2013-08-01include/opcode/Richard Sandiford2-10/+6
* mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31) (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH) (MIPS16_INSN_COND_BRANCH): Delete. opcodes/ * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags. (WR_SP): Replace with... (MOD_SP): ...this. (mips16_opcodes): Update accordingly. * mips-dis.c (print_insn_mips16): Likewise. gas/ * config/tc-mips.c (compact_branch_p, uncond_branch_p): Use the same flags for MIPS16 and non-MIPS16 instructions. (gpr_mod_mask): Move the INSN2_MOD_SP case outside the micromips block. (gpr_read_mask): Use INSN2_READ_GPR_31 for MIPS16 instructions too. (gpr_write_mask): Remove MIPS16_INSN_WRITE_SP handling. (can_swap_branch_p, get_append_method): Use the same flags for MIPS16 and non-MIPS16 instructions. Fix formatting.
2013-07-24Support Intel MPXH.J. Lu2-0/+7
gas/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386.c (BND_PREFIX): New. (struct _i386_insn): Add new field bnd_prefix. (add_bnd_prefix): New. (cpu_arch): Add MPX. (i386_operand_type): Add regbnd. (md_assemble): Handle BND prefixes. (parse_insn): Likewise. (output_branch): Likewise. (output_jump): Likewise. (build_modrm_byte): Handle regbnd. (OPTION_MADD_BND_PREFIX): New. (md_longopts): Add entry for 'madd-bnd-prefix'. (md_parse_option): Handle madd-bnd-prefix option. (md_show_usage): Add description for madd-bnd-prefix option. * doc/c-i386.texi: Document mpx/.mpx and -madd-bnd-prefix. gas/testsuite/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/i386/mpx-add-bnd-prefix.s: New. * gas/i386/mpx-add-bnd-prefix.d: New. * gas/i386/mpx-inval-1.l: New. * gas/i386/mpx-inval-1.s: New. * gas/i386/mpx.d: New. * gas/i386/mpx.s: New. * gas/i386/x86-64-mpx-add-bnd-prefix.d: New. * gas/i386/x86-64-mpx-add-bnd-prefix.s: New. * gas/i386/x86-64-mpx-addr32.d: New. * gas/i386/x86-64-mpx-addr32.s: New. * gas/i386/x86-64-mpx-inval-1.l: New. * gas/i386/x86-64-mpx-inval-1.s: New. * gas/i386/x86-64-mpx-inval-2.l: New. * gas/i386/x86-64-mpx-inval-2.s: New. * gas/i386/x86-64-mpx.d: New. * gas/i386/x86-64-mpx.s: New. * gas/i386/nops.d: Adjust to MPX changes. * gas/i386/nops.s: Likewise. * gas/i386/x86-64-nops.d: Likewise. * gas/i386/x86-64-nops.s: Likewise. * gas/i386/ilp32/x86-64-nops.d: Likewise. * gas/i386/i386.exp: Run new MPX tests. include/opcode/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386.h (BND_PREFIX_OPCODE): New. opcodes/ 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis.c (BND_Fixup): New. (Ebnd): New. (Ev_bnd): New. (Gbnd): New. (BND): New. (v_bnd_mode): New. (bnd_mode): New. (MOD enum): Add new entries. (PREFIX enum): Likewise. (dis tables): Replace XX with BND for near branch and call instructions. (prefix_table): Add new entries. (mod_table): Likewise. (names_bnd): New. (intel_names_bnd): New. (att_names_bnd): New. (BND_PREFIX): New. (prefix_name): Handle BND_PREFIX. (print_insn): Initialize names_bnd. (intel_operand_size): Handle new modes. (OP_E_register): Likewise. (OP_E_memory): Likewise. (OP_G): Likewise. * i386-gen.c (cpu_flag_init): Add CpuMPX. (cpu_flags): Add CpuMPX. (operand_type_init): Add RegBND. (opcode_modifiers): Add BNDPrefixOk. (operand_types): Add RegBND. * i386-init.h: Regenerate. * i386-opc.h (CpuMPX): New. (CpuUnused): Comment out. (i386_cpu_flags): Add cpumpx. (BNDPrefixOk): New. (i386_opcode_modifier): Add bndprefixok. (RegBND): New. (i386_operand_type): Add regbnd. * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets. Add MPX instructions and bnd prefix. * i386-reg.tbl: Add bnd0-bnd3 registers. * i386-tbl.h: Regenerate.
2013-07-14include/opcode/Richard Sandiford2-0/+14
* mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and OP_SAVE_RESTORE_LIST. (decode_mips16_operand): Declare. opcodes/ * mips16-opc.c: Include mips-formats.h. (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New static arrays. (decode_mips16_operand): New function. * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete. (print_insn_arg): Handle OP_ENTRY_EXIT list. Abort for OP_SAVE_RESTORE_LIST. (print_mips16_insn_arg): Change interface. Use mips_operand structures. Delete GET_OP_S. Move GET_OP definition to... (print_insn_mips16): ...here. Call init_print_arg_state. Update the call to print_mips16_insn_arg.
2013-07-14include/opcode/Richard Sandiford2-0/+298
* mips.h (mips_operand_type, mips_reg_operand_type): New enums. (mips_operand, mips_int_operand, mips_mapped_int_operand) (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand) (mips_pcrel_operand): New structures. (mips_insert_operand, mips_extract_operand, mips_signed_operand) (mips_decode_int_operand, mips_decode_pcrel_operand): New functions. (decode_mips_operand, decode_micromips_operand): Declare. opcodes/ * mips-formats.h: New file. * mips-opc.c: Include mips-formats.h. (reg_0_map): New static array. (decode_mips_operand): New function. * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h. (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map) (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map) (int_c_map): New static arrays. (decode_micromips_operand): New function. * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map) (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map) (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map) (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2) (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map) (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map) (micromips_imm_b_map, micromips_imm_c_map): Delete. (print_reg): New function. (mips_print_arg_state): New structure. (init_print_arg_state, print_insn_arg): New functions. (print_insn_args): Change interface and use mips_operand structures. Delete GET_OP_S. Move GET_OP definition to... (print_insn_mips): ...here. Update the call to print_insn_args. (print_insn_micromips): Use print_insn_args. gas/ * config/tc-mips.c (validate_mips_insn): Move further up file. Add insn_bits and decode_operand arguments. Use the mips_operand fields to work out which bits an operand occupies. Detect double definitions. (validate_micromips_insn): Move further up file. Call into validate_mips_insn.
2013-07-14include/opcode/Richard Sandiford2-0/+6
* mips.h: Document MIPS16 "I" opcode. opcodes/ * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands in macros. gas/ * config/tc-mips.c (mips16_ip): Handle "I".
2013-07-07include/opcode/Richard Sandiford2-90/+28
* mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB) (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB) (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A) (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB) (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB) (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB) (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB) (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB) (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A) (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A) (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB) (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete. (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A): Rename to... (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB) (M_USD_AB): ...these. opcodes/ * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD and SD A(B) macros up. * micromips-opc.c (micromips_opcodes): Likewise. gas/ * config/tc-mips.c (gprel16_reloc_p): New function. (macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are BFD_RELOC_UNUSED. (offset_high_part, small_offset_p): New functions. (nacro): Use them. Remove *_OB and *_DOB cases. For single- register load and store macros, handle the 16-bit offset case first. If a 16-bit offset is not suitable for the instruction we're generating, load it into the temporary register using ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the M_L_DAB code once the address has been constructed. For double load and store macros, again handle the 16-bit offset case first. If the second register cannot be accessed from the same high part as the first, load it into AT using ADDRESS_ADDI_INSN. Fix the handling of LD in cases where the first register is the same as the base. Also handle the case where the offset is not 16 bits and the second register cannot be accessed from the same high part as the first. For unaligned loads and stores, fuse the offbits == 12 and old "ab" handling. Apply this handling whenever the second offset needs a different high part from the first. Construct the offset using ADDRESS_ADDI_INSN where possible, for offbits == 16 as well as offbits == 12. Use offset_reloc when constructing the individual loads and stores. (mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc and offset_reloc before matching against a particular opcode. Handle elided 'A' constants. Allow 'A' constants to use relocation operators. gas/testsuite/ * gas/mips/ldstla-32.d: Avoid "lui at,0x0" sequences for truncated constants. * gas/mips/ldstla-32-shared.d: Likewise. * gas/mips/mcu.d: Use ADDIU in preference to LI+ADDU when adding 16-bit constants to the base. * gas/mips/micromips@mcu.d: Likewise. * gas/mips/micromips@cache.d: Likewise. * gas/mips/micromips@pref.d: Likewise. * gas/mips/micromips.d, gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d: Likewise. Allow the full 16-bit offset range to be used for SB, LB and LBU in USH and ULH sequences. Fix the expected output for LD and SD when the two LW and SW offsets need different high parts. * gas/mips/eva.s: Test PREFE with relocation operators. * gas/mips/eva.d: Use ADDIU in preference to LI+ADDU for 16-bit constants. Update after eva.s change. * gas/mips/micromips@eva.d: Likewise. * gas/mips/ld-reloc.s, gas/mips/ld-reloc.d, gas/mips/l_d-reloc.s, gas/mips/l_d-reloc.d, gas/mips/ulw-reloc.s, gas/mips/ulw-reloc.d, gas/mips/micromips@ulw-reloc.d, gas/mips/ulh-reloc.s, gas/mips/ulh-reloc.d: New tests. * gas/mips/mips.exp: Run them.
2013-07-07include/opcode/Richard Sandiford2-10/+13
* mips.h: Remove documentation of "[" and "]". Update documentation of "k" and the MDMX formats. opcodes/ * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400 MDMX-like instructions. * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when printing "Q" operands for INSN_5400 instructions. gas/ * config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling. (mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions. Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions. gas/testsuite/ * gas/mips/vr5400-ill.s, gas/mips/vr5400-ill.l: New test. * gas/mips/mips.exp: Run it.
2013-07-07include/opcode/Richard Sandiford2-5/+8
* mips.h: Update documentation of "+s" and "+S". opcodes/ * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and "+S" for "cins". * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments. Combine cases. gas/ * config/tc-mips.c (mips_ip): Preserve the real bit number for "+p". Require the msb to be <= 31 for "+s". Check that the size is <= 31 for both "+s" and "+S".
2013-07-07include/opcode/Richard Sandiford2-3/+10
* mips.h: Document "+i". opcodes/ * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for "jalx". * mips16-opc.c (mips16_opcodes): Likewise. * micromips-opc.c (micromips_opcodes): Likewise. * mips-dis.c (print_insn_args, print_mips16_insn_arg) (print_insn_mips16): Handle "+i". (print_insn_micromips): Likewise. Conditionally preserve the ISA bit for "a" but not for "+i". gas/ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn): (mips_ip, mips16_ip): Handle "+i".
2013-07-07include/opcode/Richard Sandiford2-9/+11
* mips.h: Remove "mi" documentation. Update "mh" documentation. (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI): Delete. (INSN2_WRITE_GPR_MHI): Rename to... (INSN2_WRITE_GPR_MH): ...this. opcodes/ * micromips-opc.c (WR_mhi): Rename to.. (WR_mh): ...this. (micromips_opcodes): Update "movep" entry accordingly. Replace "mh,mi" with "mh". * mips-dis.c (micromips_to_32_reg_h_map): Rename to... (micromips_to_32_reg_h_map1): ...this. (micromips_to_32_reg_i_map): Rename to... (micromips_to_32_reg_h_map2): ...this. (print_micromips_insn): Remove "mi" case. Print both registers in the pair for "mh". gas/ * config/tc-mips.c (mips32_to_micromips_reg_h_map): Delete. (micromips_to_32_reg_h_map): Rename to... (micromips_to_32_reg_h_map1): ...this. (micromips_to_32_reg_i_map): Rename to... (micromips_to_32_reg_h_map2): ...this. (mips_lookup_reg_pair): New function. (gpr_write_mask, macro): Adjust after above renaming. (validate_micromips_insn): Remove "mi" handling. (mips_ip): Likewise. Parse both registers in a pair for "mh".
2013-07-07include/opcode/Richard Sandiford2-7/+6
* mips.h: Remove documentation of "+D" and "+T". opcodes/ * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries. * micromips-opc.c (micromips_opcodes): Likewise. * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D" and "+T" handling. Check for a "0" suffix when deciding whether to use coprocessor 0 names. In that case, also check for ",H" selectors. gas/ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn) (mips_ip): Remove "+D" and "+T" handling. gas/testsuite/ * gas/mips/lb.d, gas/mips/sb.d: Use coprocessor register names for LWC0 and SWC0.
2013-06-26include/opcode/Richard Sandiford2-4/+9
* mips.h: Fix comment for "1": it is now STYPE rather than SHAMT. Use "source" rather than "destination" for microMIPS "G". gas/ * config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT.
2013-06-25 bfd/Maciej W. Rozycki2-0/+8
* elfxx-mips.h (_bfd_mips_elf_insn32): New prototype. * elfxx-mips.c (mips_elf_link_hash_table): Add insn32 member. (STUB_MOVE32_MICROMIPS, STUB_JALR32_MICROMIPS): New macros. (MICROMIPS_INSN32_FUNCTION_STUB_NORMAL_SIZE): Likewise. (MICROMIPS_INSN32_FUNCTION_STUB_BIG_SIZE): Likewise. (micromips_insn32_o32_exec_plt0_entry): New variable. (micromips_insn32_o32_exec_plt_entry): Likewise. (_bfd_mips_elf_adjust_dynamic_symbol): Handle insn32 mode. (mips_elf_estimate_stub_size): Likewise. (_bfd_mips_elf_size_dynamic_sections): Likewise. (_bfd_mips_elf_finish_dynamic_symbol): Likewise. (mips_finish_exec_plt): Likewise. (_bfd_mips_elf_relax_section): Likewise. (_bfd_mips_elf_insn32): New function. (_bfd_mips_elf_get_synthetic_symtab): Handle insn32 PLT. gas/ * config/tc-mips.c (mips_set_options): Add insn32 member. (mips_opts): Initialize it. (NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode. (options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values. (md_longopts): Add "minsn32" and "mno-insn32" options. (is_size_valid): Handle insn32 mode. (md_assemble): Pass instruction string down to macro. (brk_fmt): Add second dimension and insn32 mode initializers. (mfhl_fmt): Likewise. (BRK_FMT, MFHL_FMT): Handle insn32 mode. (macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding. (macro_build_jalr, move_register): Handle insn32 mode. (macro_build_branch_rs): Likewise. (macro): Handle insn32 mode. <M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases. (mips_ip): Handle insn32 mode. (md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32. (s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops. (mips_handle_align): Handle insn32 mode. (md_show_usage): Add -minsn32 and -mno-insn32. * doc/as.texinfo (Target MIPS options): Add -minsn32 and -mno-insn32 options. (-minsn32, -mno-insn32): New options. * doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32 options. (MIPS assembly options): New node. Document .set insn32 and .set noinsn32. (MIPS-Dependent): List the new node. gas/testsuite/ * gas/mips/micromips-insn32.d: New test. * gas/mips/micromips-noinsn32.d: Likewise. * gas/mips/micromips.l: Rename to... * gas/mips/micromips-warn.l: ... this. * gas/mips/micromips.d: Update accordingly. * gas/mips/micromips-trap.d: Likewise. * gas/mips/micromips.l: New list test. * gas/mips/micromips.s: Add conditionals. * gas/mips/mips.exp: Run the new tests. include/opcode/ * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum values. ld/ * emultempl/mipself.em (insn32): New variable. (mips_create_output_section_statements): Handle insn32 mode. (PARSE_AND_LIST_PROLOGUE): New macro. (PARSE_AND_LIST_LONGOPTS): Likewise. (PARSE_AND_LIST_OPTIONS): Likewise. * gen-doc.texi: Set MIPS. * ld.texinfo: Likewise. (Options specific to MIPS targets): New section. (ld and MIPS family): New node. (Top, Machine Dependent): List the new node. opcodes/ * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc" and "movep" macros.
2013-06-23include/opcode/Richard Sandiford2-1/+5
* mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS. gas/ * config/tc-mips.c (mips_ip): Fix swapped bit numbers in comments.
2013-06-21 * msp430-decode.opc: New.Nick Clifton1-0/+130
* msp430-decode.c: New/generated. * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c. (MAINTAINER_CLEANFILES): Likewise. Add rule to build msp430-decode.c frommsp430decode.opc using the opc2c program. * Makefile.in: Regenerate. * configure.in: Add msp430-decode.lo to msp430 architecture files. * configure: Regenerate. * msp430-decode.h: New.
2013-06-172013-06-17 Catherine Moore <clm@codesourcery.com>Catherine Moore2-5/+77
Maciej W. Rozycki <macro@codesourcery.com> Chao-Ying Fu <fu@mips.com> gas/testsuite/ * gas/mips/mips.exp: Run new tests. * gas/mips/eva.d: New. * gas/mips/eva.s: New. * gas/mips/micromips@eva.d: New. gas/ * config/tc-mips.c (mips_set_options): Add ase_eva. (mips_set_options mips_opts): Add ase_eva. (file_ase_eva): Declare. (ISA_SUPPORTS_EVA_ASE): Define. (IS_SEXT_9BIT_NUM): Define. (MIPS_CPU_ASE_EVA): Define. (is_opcode_valid): Add support for ase_eva. (macro_build): Likewise. (macro): Likewise. (validate_mips_insn): Likewise. (validate_micromips_insn): Likewise. (mips_ip): Likewise. (options): Add OPTION_EVA and OPTION_NO_EVA. (md_longopts): Add -meva and -mno-eva. (md_parse_option): Process new options. (mips_after_parse_args): Check for valid EVA combinations. (s_mipsset): Likewise. include/ * opcode/mips.h (OP_SH_EVAOFFSET): Define. (OP_MASK_EVAOFFSET): Define. (INSN_ASE_MASK): Delete. (ASE_EVA): Define. (M_CACHEE_AB, M_CACHEE_OB): New. (M_LBE_OB, M_LBE_AB): New. (M_LBUE_OB, M_LBUE_AB): New. (M_LHE_OB, M_LHE_AB): New. (M_LHUE_OB, M_LHUE_AB): New. (M_LLE_AB, M_LLE_OB): New. (M_LWE_OB, M_LWE_AB): New. (M_LWLE_AB, M_LWLE_OB): New. (M_LWRE_AB, M_LWRE_OB): New. (M_PREFE_AB, M_PREFE_OB): New. (M_SCE_AB, M_SCE_OB): New. (M_SBE_OB, M_SBE_AB): New. (M_SHE_OB, M_SHE_AB): New. (M_SWE_OB, M_SWE_AB): New. (M_SWLE_AB, M_SWLE_OB): New. (M_SWRE_AB, M_SWRE_OB): New. (MICROMIPSOP_SH_EVAOFFSET): Define. (MICROMIPSOP_MASK_EVAOFFSET): Define. opcodes/ * micromips-opc.c (EVA): Define. (TLBINV): Define. (micromips_opcodes): Add EVA opcodes. * mips-dis.c (mips_arch_choices): Update for ASE_EVA. (print_insn_args): Handle EVA offsets. (print_insn_micromips): Likewise. * mips-opc.c (EVA): Define. (TLBINV): Define. (mips_builtin_opcodes): Add EVA opcodes.
2013-06-122013-06-12 Sandra Loosemore <sandra@codesourcery.com>Sandra Loosemore2-1/+5
include/opcode/ * nios2.h (OP_MATCH_ERET): Correct eret encoding. gas/testsuite/ * gas/nios2/tret.d: Correct eret encoding.
2013-06-08gas/Richard Sandiford1-23/+23
2013-06-08 Catherine Moore <clm@codesourcery.com> * config/tc-mips.c (is_opcode_valid): Build ASE mask. (is_opcode_valid_16): Pass ase value to opcode_is_member. (append_insn): Change INSN_xxxx to ASE_xxxx. include/ 2013-06-08 Catherine Moore <clm@codesourcery.com> * opcode/mips.h (mips_opcode): Add ase field. (INSN_ASE_MASK): Delete. (INSN_DSP): Rename to ASE_DSP. Provide new value. (INSN_DSPR2): Rename to ASE_DSPR2. Provide new value. (INSN_MCU): Rename to ASE_MCU. Provide new value. (INSN_MDMX): Rename to ASE_MDMX. Provide new value. (INSN_MIPS3d): Rename to ASE_MIPS3D. Provide new value. (INSN_MT): Rename to ASE_MT. Provide new value. (INSN_SMARTMIPS): Rename to ASE_SMARTMIPS. Provide new value. (INSN_VIRT): Rename to ASE_VIRT. Provide new value. (INSN_VIRT64): Rename to ASE_VIRT64. Provide new value. (opcode_is_member): Add ase argument. Check ase. opcodes/ 2013-06-08 Catherine Moore <clm@codesourcery.com> Richard Sandiford <rdsandiford@googlemail.com> * micromips-opc.c (D32, D33, MC): Update definitions. (micromips_opcodes): Initialize ase field. * mips-dis.c (mips_arch_choice): Add ase field. (mips_arch_choices): Initialize ase field. (set_default_mips_dis_options): Declare and setup mips_ase. * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64, MT32, MC): Update definitions. (mips_builtin_opcodes): Initialize ase field.
2013-06-01 * gas/config/tc-avr.c: Change ISA for devices with USB support toDenis Chertykov1-6/+7
AVR_ISA_XMEGAU * include/opcode/avr.h: Rename AVR_ISA_XCH to AVR_ISA_RMW. Remove from AVR_ISA_XMEGA and add new AVR_ISA_XMEGAU
2013-05-22include/opcode/Richard Sandiford2-0/+6
2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> * mips.h (M_LQC2_AB, M_SQC2_AB): New macros. opcodes/ 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions. gas/ 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> * config/tc-mips.c (macro): Handle M_LQC2_AB and M_SQC2_AB. gas/testsuite/ 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de> * gas/mips/r5900-full.s, gas/mips/r5900-full.d: Add tests for LQ and SQ macros. * gas/mips/r5900-vu0.s, gas/mips/r5900-vu0.d: New test. * gas/mips/mips.exp: Run it.
2013-05-10binutils/ChangeLog:Andrew Pinski2-4/+22
* doc/binutils.texi: Document -Mvirt disassembler option. gas/ChangeLog: * config/tc-mips.c (struct mips_set_options): New ase_virt field. (mips_opts): Update for the new field. (file_ase_virt): New variable. (ISA_SUPPORTS_VIRT_ASE): New macro. (ISA_SUPPORTS_VIRT64_ASE): New macro. (MIPS_CPU_ASE_VIRT): New define. (is_opcode_valid): Handle ase_virt. (macro_build): Handle "+J". (validate_mips_insn): Likewise. (mips_ip): Likewise. (enum options): Add OPTION_VIRT and OPTION_NO_VIRT. (md_longopts): Add mvirt and mnovirt (md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT. (mips_after_parse_args): Handle ase_virt field. (s_mipsset): Handle "virt" and "novirt". (mips_elf_final_processing): Add a comment about virt ASE might need a new flag. (md_show_usage): Print out the usage of -mvirt and mno-virt options. * doc/c-mips.texi: Document -mvirt and -mno-virt. Document ".set virt" and ".set novirt". gas/testsuite/ChangeLog: * gas/mips/mips.exp: Run virt and virt64 testcases. * gas/mips/virt.d: New file. * gas/mips/virt.s: New file. * gas/mips/virt64.d: New file. * gas/mips/virt64.s: New file. include/opcode/ChangeLog: * mips.h (OP_MASK_CODE10): Correct definition. (OP_SH_CODE10): Likewise. Add a comment that "+J" is used now for OP_*CODE10. (INSN_ASE_MASK): Update. (INSN_VIRT): New macro. (INSN_VIRT64): New macro opcodes/ChangeLog: * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2 . Add INSN_VIRT and INSN_VIRT64 to mips64r2. (parse_mips_dis_option): Handle the virt option. (print_insn_args): Handle "+J". (print_mips_disassembler_options): Print out message about virt64. * mips-opc.c (IVIRT): New define. (IVIRT64): New define. (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions. Move rfe to the bottom as it conflicts with tlbgp.
2013-05-02 * archures.c: Add some more MSP430 machine numbers.Nick Clifton2-1/+73
* config.bfd (msp430): Define targ_selvecs. * configure.in: Add bfd_elf32_msp430_ti_vec. * cpu-msp430.c: Add some more MSP430 machine numbers. * elf32-msp430.c Add support for MSP430X relocations. Add support for TI compiler generated relocations. Add support for sym_diff relocations. Add support for relaxing out of range short branches into long branches. Add support for MSP430 attribute section. * reloc.c: Add MSP430X relocations. * targets.c: Add bfd_elf32_msp430_ti_vec. * bfd-in2.h: Regenerate. * configure: Regenerate. * libbfd.h: Regenerate. * readelf.c: Add support for MSP430X architecture. * readelf.exp: Expect -wi test to fail for the MSP430. * config/tc-msp430.c: Add support for the MSP430X architecture. Add code to insert a NOP instruction after any instruction that might change the interrupt state. Add support for the LARGE memory model. Add code to initialise the .MSP430.attributes section. * config/tc-msp430.h: Add support for the MSP430X architecture. * doc/c-msp430.texi: Document the new -mL and -mN command line options. * NEWS: Mention support for the MSP430X architecture. * gas/all/gas.exp: Skip the DIFF1 test for the MSP430. Expect the FORWARD test to pass for the MSP430. Skip the REDEF tests for the MSP430. Expect the 930509A test to fail for the MSP430. * gas/all/sleb128-4.d: Skip for the MSP430. * gas/elf/elf.exp: Set target_machine to msp430 for the MSP430. Skip the EHOPT0 test for the MSP430. Skip the REDEF and EQU-RELOC tests for the MSP430. * gas/elf/section2.e-msp430: New file. * gas/lns/lns-big-delta.d: Remove expectation of 20-bit addresses. * gas/lns/lns.exp: Use alternate LNS COMMON test for the MSP430. * gas/msp430/msp430x.s: New test. * gas/msp430/msp430x.d: Expected disassembly. * gas/msp430/msp430.exp: Run new test. * gas/msp430/opcode.d: Update expected disassembly. * msp430.h: Add MSP430X relocs. Add some more MSP430 machine numbers. Add values used by .MSP430.attributes section. * msp430.h: Add patterns for MSP430X instructions. * Makefile.am: Add emsp430X.c * Makefine.in: Regenerate. * configure.tgt (msp430): Add msp430X emulation. * ldmain.c (multiple_definition): Only disable relaxation if it was enabled by the user. * ldmain.h (RELAXATION_ENABLED_BY_USER): New macro. * emulparams/msp430all.sh: Add support for MSP430X. * emultempl/generic.em: (before_parse): Enable relaxation for the MSP430. * scripttempl/msp430.sc: Reorganize sections. Add .rodata section. * scripttempl/msp430_3.sc: Likewise. * NEWS: Mention support for MSP430X. * ld-elf/flags1.d: Expect this test to pass on the MSP430. * ld-elf/init-fini-arrays.d: Expect this test to fail on the MSP430. * ld-elf/merge.d: Expect this test to pass on the MSP430. * ld-elf/sec64k.exp: Skip these tests for the MSP430. * ld-gc/pr13683.d: Expect this test to fail on the MSP430. * ld-srec/srec.exp: Expect these tests to fail on the MSP430. * ld-undefined/undefined.exp: Expect the UNDEFINED LINE test to fail on the MSP430. * msp430-dis.c: Add support for MSP430X instructions.
2013-04-06Increase the accuracy of sparc instruction aliases.David S. Miller2-0/+8
Make current with UA2011 specification. Add an F_PREFERRED opcode flag that indicates a preferred alias when multiple aliases for the same opcode exists. For 'lzd': Add 'lzcnt' as primary instruction, and make 'lzd' an alias. Add 'ldtw', 'ldtwa', 'sttw', 'sttwa': The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on integer registers. Mark the latter now as aliases. For 'flush': Support "[address]" syntax as well as plain "address". Rework 'mov' aliases for 'wr': Eliminate bogus three operand moves, and encode the instructions properly for the "mov REG, %ASR" cases, specifically we should encode the register in rs2 not rs1 as per The SPARC V8 Architecture Manual. Add missing cbcond aliases: c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu Add 'd' suffix VIS logical ops: The primary opcode for 'fzero' is now 'fzerod' (compare with 'fzeros'), for example. And thus 'fzero' is now an alias. Add modern opcodes for condition code setting edge instructions: They are now edgeN{,l}cc instead of plain edgeN{,l}. Add modern opcodes for VIS comparisons: All VIS comparisons now start with prefix "fp", retain the older variants as aliases. The signed variants for equal and not-equal have "u" aliases to show that these comparisons are equally suited for unsigned compares. Update existing test cases as needed, and add several new ones. include/opcode/ * sparc.h (F_PREFERRED): Define. (F_PREF_ALIAS): Define. opcodes/ * sparc-dis.c (compare_opcodes): When encountering multiple aliases of an opcode, prefer the one with F_PREFERRED set. * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa, lzcnt, flush with '[address]' syntax, and missing cbcond pseudo ops. Make 64-bit VIS logical ops have "d" suffix in their names, mark existing mnenomics as aliases. Add "cc" suffix to edge instructions generating condition codes, mark existing mnenomics as aliases. Add "fp" prefix to VIS compare instructions, mark existing mnenomics as aliases. gas/testsuite/ * gas/sparc/cbcond.s: Add tests for new opcode aliases. * gas/sparc/cbcond.d: Updated. * gas/sparc/hpcvis3.s: Add tests for new opcode aliases. * gas/sparc/hpcvis3.d: Updated. * gas/sparc/v8-movwr-imm.d: Fix expected disassembly. * gas/sparc/edge.s: New test. * gas/sparc/edge.d: Expected disassembly. * gas/sparc/flush.s: New test. * gas/sparc/flush.d: Expected disassembly. * gas/sparc/ldd_std.s: New test. * gas/sparc/ldd_std.d: Expected disassembly. * gas/sparc/ldtw_sttw.s: New test. * gas/sparc/ldtw_sttw.d: Expected disassembly. * gas/sparc/sparc.exp: Run new tests.
2013-04-03 * elf32-v850.c (v850_elf_is_target_special_symbol): New function.Nick Clifton2-0/+7
(bfd_elf32_bfd_is_target_special_symbol): Define. * v850.h (V850_INVERSE_PCREL): Define. * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the destination address by subtracting the operand from the current address. * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store a positive value in the insn. (extract_u16_loop): Do not negate the returned value. (D16_LOOP): Add V850_INVERSE_PCREL flag. (ceilf.sw): Remove duplicate entry. (cvtf.hs): New entry. (cvtf.sh): Likewise. (fmaf.s): Likewise. (fmsf.s): Likewise. (fnmaf.s): Likewise. (fnmsf.s): Likewise. (maddf.s): Restrict to E3V5 architectures. (msubf.s): Likewise. (nmaddf.s): Likewise. (nmsubf.s): Likewise.
2013-03-28 PR binutils/15068Nick Clifton2-9/+14
* tic6x-opcode-table.h: Fix patterns for add, ldnw and xor. * gas/tic6x/insns16-lsd-unit.s: Correct bit patterns for mvk, add and xor. * gas/tic6x/insns16-lsd-unit.d: Update expected output.
2013-03-27 PR binutils/15068Nick Clifton4-10/+1659
* tic6x-dis.c: Add support for displaying 16-bit insns. * tic6xc-insn-formats.h (FLD): Add use of bitfield array. Add 16-bit opcodes. * tic6xc-opcode-table.h: Add 16-bit insns. * tic6x.h: Add support for 16-bit insns. * config/tc-tic6x.c (tic6x_try_encode): Add use of bitfields array. * gas/tic6x/insns16-d-unit.s: New test. * gas/tic6x/insns16-d-unit.d: Expected disassembly. * gas/tic6x/insns16-ddec.s: New test. * gas/tic6x/insns16-ddec.d: Expected disassembly. * gas/tic6x/insns16-dinc.s: New test. * gas/tic6x/insns16-dinc.d: Expected disassembly. * gas/tic6x/insns16-dind.s: New test. * gas/tic6x/insns16-dind.d: Expected disassembly. * gas/tic6x/insns16-doff4.s: New test. * gas/tic6x/insns16-doff4.d: Expected disassembly. * gas/tic6x/insns16-l-unit.s: New test. * gas/tic6x/insns16-l-unit.d: Expected disassembly. * gas/tic6x/insns16-lsd-unit.s: New test. * gas/tic6x/insns16-lsd-unit.d: Expected disassembly. * gas/tic6x/insns16-m-unit.s: New test. * gas/tic6x/insns16-m-unit.d: Expected disassembly. * gas/tic6x/insns16-s-unit-pcrel.s: New test. * gas/tic6x/insns16-s-unit-pcrel.d: Expected disassembly. * gas/tic6x/insns16-s-unit: New test. * gas/tic6x/insns16-s-unit.d: Expected disassembly.
2013-03-21 * elf32-h8300 (h8_relax_section): Add new relaxation of movNick Clifton2-8/+11
@(disp:32,ERx) to mov @(disp:16,ERx). (R_H8_DISP32A16): New reloc. Comments added and corrected. * reloc.c (BFD_RELOC_H8_DISP32A16): New reloc. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * ld.texinfo (H8/300): Add description of relaxation of mov @(disp:32,ERx) to mov @(disp:16,ERx). * ld-h8300/h8300.exp: Add new relax-7 test on ELF. * ld-h8300/relax-2.s: Add other direction and .w/.l variants of mov insns. * ld-h8300/relax-2.d: Update expected disassembly. * ld-h8300/relax-7a.s: New: tests for mov @(disp:32,ERx) -> mov @(disp:16,ERx). * ld-h8300/relax-7b.s: New: Likewise. * ld-h8300/relax-7.d: New: expected disassembly. * config/tc-h8300.c (do_a_fix_imm): Add relaxation of mov @(disp:32,ERx) to mov @(disp:16,ERx) insns by new reloc R_H8_DISP32A16. * config/tc-h8300.h: Remove duplicated defines.
2013-03-20 PR gas/15082Nick Clifton2-7/+17
* tic6x-opcode-table.h: Rename mpydp's specific operand type macro from ORREGD1324 to ORXREGD1324 and make it cross-path-able through tic6x_operand_xregpair operand coding type. Make mpydp instruction cross-path-able, ie: remove the FIXed 'x' opcode field, usu ORXREGD1324 for the src2 operand and remove the TIC6X_FLAG_NO_CROSS. * gas/tic6x/insns-bad-1.s: Remove test-case for mpydp with cross-path. * gas/tic6x/insns-bad-1.l: Update expected output. * gas/tic6x/insns-c674x.s: Add a test-case for mpydp with cross-path. * gas/tic6x/insns-c674x.d: Update expected output.
2013-03-20* include/opcode/tic6x.h: add tic6x_coding_dreg_(msb|lsb) field coding type inNick Clifton3-16/+36
order to encode separately the msb and lsb of a register pair ; this will be needed to encode the opcodes the same way as Ti assembler does. * gas/config/tc-tic6x.c: handle tic6x_coding_dreg_(msb|lsb) field coding types and use it to encode register pair numbers when required. * opcodes/tic6x-dis.c: decodes opcodes that have individual msb and lsb halves in src1 & src2 fields ; discard the src1 (lsb) value and only use src2 (msb), discarding bit 0, to follow what Ti SDK does in that case as any value in the src1 field yields the same output with SDK disassembler. * include/opcode/tic6x-opcode-table.h: modify absdp, dpint, dpsp, dptrunc, rcpdp and rsqrdp opcodes to use the new field coding types. * gas/testsuite/gas/tic6x/insns-c674x.d, gas/testsuite/gas/tic6x/insns-c674x.s : add test case for the newly generated opcode but keep the old ones as they seem legit as per Ti disassembler output.
2013-03-122013-03-12 Sebastian Huber <sebastian.huber@embedded-brains.de>gdb_7_6-branchpointSandra Loosemore1-3/+4
include/ * opcode/nios2.h: Edit comment. gas/ * config/tc-nios2.c (nios2_consume_arg): Delete 'k' case. Add 'o' case. Add default BAD_CASE to switch. gas/testsuite/ * gas/nios2/break.d: Check instruction values.
2013-03-122013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>Sandra Loosemore1-0/+2
include/ * opcode/nios2.h (OPX_WRPRS): New define. (OP_MATCH_WRPRS): Likewise. opcodes/ * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs. gas/ * config/tc-nios2.c (nios2_assemble_args_ds): New function. (nios2_arg_info_structs): Add "d,s" and "d,s,E" entries. gas/testsuite/ * gas/nios2/nios2.exp: Run wrprs. * gas/nios2/wrprs.d: New file. * gas/nios2/wrprs.s: Likewise.
2013-03-122013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>Sandra Loosemore1-0/+2
include/ * opcode/nios2.h (OP_RDPRS): New define. (OP_MATCH_RDPRS): Likewise. opcodes/ * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs. gas/testsuite/ * gas/nios2/nios2.exp: Run rdprs. * gas/nios2/rdprs.d: New file. * gas/nios2/rdprs.s: Likewise.
2013-03-11Add support for AArch32 CRC instruction in ARMv8.Kyrylo Tkachov2-0/+7
gas/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-arm.c (crc_ext_armv8): New feature set. (UNPRED_REG): New macro. (do_crc32_1): New function. (do_crc32b, do_crc32h, do_crc32w, do_crc32cb, do_crc32ch, do_crc32cw): Likewise. (TUEc): New macro. (insns): Add entries for crc32 mnemonics. (arm_extensions): Add entry for crc. include/opcode/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * arm.h (CRC_EXT_ARMV8): New constant. (ARCH_CRC_ARMV8): New macro. opcodes/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * arm-dis.c (arm_opcodes): Add entries for CRC instructions. (thumb32_opcodes): Likewise. (print_insn_thumb32): Handle 'S' control char. gas/testsuite/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * gas/arm/crc32-bad.d: New file. * gas/arm/crc32-bad.l: Likewise. * gas/arm/crc32-bad.s: Likewise. * gas/arm/crc32.d: Likewise. * gas/arm/crc32.s: Likewise.
2013-02-28include/opcode/Yufeng Zhang2-0/+5
* aarch64.h (AARCH64_FEATURE_CRC): New macro. opcodes/ * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros. (aarch64_feature_crc): New static. (CRC): New macro. (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w, crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions. * aarch64-asm-2.c: Re-generate. * aarch64-dis-2.c: Ditto. * aarch64-opc-2.c: Ditto. gas/ * config/tc-aarch64.c (aarch64_features): Add the 'crc' option. gas/testsuite/ * gas/aarch64/crc32.s: New test. * gas/aarch64/crc32.d: Ditto.
2013-02-062013-02-06 Sandra Loosemore <sandra@codesourcery.com>Sandra Loosemore2-0/+524
Andrew Jenner <andrew@codesourcery.com> Based on patches from Altera Corporation. bfd/ * Makefile.am (ALL_MACHINES): Add cpu-nios2.lo. (ALL_MACHINES_CFILES): Add cpu-nios2.c. (BFD_BACKENDS): Add elf32-nios2.lo. (BFD32_BACKENDS_CFILES): Add elf32-nios2.c. * Makefile.in: Regenerated. * configure.in: Add entries for bfd_elf32_bignios2_vec and bfd_elf32_littlenios2_vec. * configure: Regenerated. * config.bfd: Add cases for nios2. * archures.c (enum bfd_architecture): Add bfd_arch_nios2. (bfd_mach_nios2): Define. (bfd_nios2_arch): Declare. (bfd_archures_list): Add bfd_nios2_arch. * targets.c (bfd_elf32_bignios2_vec): Declare. (bfd_elf32_littlenios2_vec): Declare. (_bfd_target_vector): Add entries for bfd_elf32_bignios2_vec and bfd_elf32_littlenios2_vec. * elf-bfd.h (enum elf_target_id): Add NIOS2_ELF_DATA. * reloc.c (enum bfd_reloc_code_real): Add Nios II relocations. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * cpu-nios2.c: New file. * elf32-nios2.c: New file. opcodes/ * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and nios2-opc.c. * Makefile.in: Regenerated. * configure.in: Add case for bfd_nios2_arch. * configure: Regenerated. * disassemble.c (ARCH_nios2): Define. (disassembler): Add case for bfd_arch_nios2. * nios2-dis.c: New file. * nios2-opc.c: New file. include/ * dis-asm.h (print_insn_big_nios2): Declare. (print_insn_little_nios2): Declare. include/elf * nios2.h: New file. include/opcode/ * nios2.h: New file. gas/ * Makefile.am (TARGET_CPU_CFILES): Add config/tc-nios2.c. (TARGET_CPU_HFILES): Add config/tc-nios2.h. * Makefile.in: Regenerated. * configure.tgt: Add case for nios2*-linux*. * config/obj-elf.c: Conditionally include elf/nios2.h. * config/tc-nios2.c: New file. * config/tc-nios2.h: New file. * doc/Makefile.am (CPU_DOCS): Add c-nios2.texi. * doc/Makefile.in: Regenerated. * doc/all.texi: Set NIOSII. * doc/as.texinfo (Overview): Add Nios II options. (Machine Dependencies): Include c-nios2.texi. * doc/c-nios2.texi: New file. * NEWS: Note Altera Nios II support. gas/testsuite/ * gas/nios2/add.d: New. * gas/nios2/add.s: New. * gas/nios2/align_fill.d: New. * gas/nios2/align_fill.s: New. * gas/nios2/align_text.d: New. * gas/nios2/align_text.s: New. * gas/nios2/and.d: New. * gas/nios2/and.s: New. * gas/nios2/branch.d: New. * gas/nios2/branch.s: New. * gas/nios2/break.d: New. * gas/nios2/break.s: New. * gas/nios2/bret.d: New. * gas/nios2/bret.s: New. * gas/nios2/cache.d: New. * gas/nios2/cache.s: New. * gas/nios2/call26.d: New. * gas/nios2/call26.s: New. * gas/nios2/call.d: New. * gas/nios2/call.s: New. * gas/nios2/cmp.d: New. * gas/nios2/cmp.s: New. * gas/nios2/comments.d: New. * gas/nios2/comments.s: New. * gas/nios2/complex.d: New. * gas/nios2/complex.s: New. * gas/nios2/ctl.d: New. * gas/nios2/ctl.s: New. * gas/nios2/custom.d: New. * gas/nios2/custom.s: New. * gas/nios2/etbt.d: New. * gas/nios2/etbt.s: New. * gas/nios2/flushda.d: New. * gas/nios2/flushda.s: New. * gas/nios2/illegal.l: New. * gas/nios2/illegal.s: New. * gas/nios2/jmp.d: New. * gas/nios2/jmp.s: New. * gas/nios2/ldb.d: New. * gas/nios2/ldb.s: New. * gas/nios2/ldh.d: New. * gas/nios2/ldh.s: New. * gas/nios2/ldw.d: New. * gas/nios2/ldw.s: New. * gas/nios2/lineseparator.d: New. * gas/nios2/lineseparator.s: New. * gas/nios2/mov.d: New. * gas/nios2/movia.d: New. * gas/nios2/movia.s: New. * gas/nios2/movi.d: New. * gas/nios2/movi.s: New. * gas/nios2/mov.s: New. * gas/nios2/mul.d: New. * gas/nios2/mul.s: New. * gas/nios2/nios2.exp: New. * gas/nios2/nor.d: New. * gas/nios2/nor.s: New. * gas/nios2/or.d: New. * gas/nios2/or.s: New. * gas/nios2/ret.d: New. * gas/nios2/ret.s: New. * gas/nios2/rol.d: New. * gas/nios2/rol.s: New. * gas/nios2/rotate.d: New. * gas/nios2/rotate.s: New. * gas/nios2/stb.d: New. * gas/nios2/stb.s: New. * gas/nios2/sth.d: New. * gas/nios2/sth.s: New. * gas/nios2/stw.d: New. * gas/nios2/stw.s: New. * gas/nios2/sub.d: New. * gas/nios2/sub.s: New. * gas/nios2/sync.d: New. * gas/nios2/sync.s: New. * gas/nios2/trap.d: New. * gas/nios2/trap.s: New. * gas/nios2/tret.d: New. * gas/nios2/tret.s: New. * gas/nios2/warn_noat.l: New. * gas/nios2/warn_noat.s: New. * gas/nios2/warn_nobreak.l: New. * gas/nios2/warn_nobreak.s: New. * gas/nios2/xor.d: New. * gas/nios2/xor.s: New. ld/ * Makefile.am (enios2elf.c): New rule. * Makefile.in: Regenerated. * configure.tgt: Add case for nios2*-*-*. * emulparams/nios2elf.sh: New file. * NEWS: Note Altera Nios II support. ld/testsuite/ * ld-nios2/emit-relocs-1a.s: New. * ld-nios2/emit-relocs-1b.s: New. * ld-nios2/emit-relocs-1.d: New. * ld-nios2/emit-relocs-1.ld: New. * ld-nios2/gprel.d: New. * ld-nios2/gprel.s: New. * ld-nios2/hilo16.d: New. * ld-nios2/hilo16.s: New. * ld-nios2/hilo16_symbol.s: New. * ld-nios2/imm5.d: New. * ld-nios2/imm5.s: New. * ld-nios2/imm5_symbol.s: New. * ld-nios2/nios2.exp: New. * ld-nios2/pcrel16.d: New. * ld-nios2/pcrel16_label.s: New. * ld-nios2/pcrel16.s: New. * ld-nios2/relax_callr.d: New. * ld-nios2/relax_callr.ld: New. * ld-nios2/relax_callr.s: New. * ld-nios2/relax_cjmp.d: New. * ld-nios2/relax_cjmp.s: New. * ld-nios2/relax_jmp.ld: New. * ld-nios2/relax_section.d: New. * ld-nios2/relax_section.s: New. * ld-nios2/relax_ujmp.d: New. * ld-nios2/relax_ujmp.s: New. * ld-nios2/reloc.d: New. * ld-nios2/reloc.s: New. * ld-nios2/reloc_symbol.s: New. * ld-nios2/s16.d: New. * ld-nios2/s16.s: New. * ld-nios2/s16_symbol.s: New. * ld-nios2/u16.d: New. * ld-nios2/u16.s: New. * ld-nios2/u16_symbol.s: New. * ld-elf/indirect.exp: Skip on targets that don't support -shared -fPIC. * ld-elfcomm/elfcomm.exp: Build with -G0 for nios2. * ld-plugin/lto.exp: Skip shared library tests on targets that don't support them. Skip execution tests on non-native targets. binutils/ * readelf.c: Include elf/nios2.h. (dump_relocations): Add case for EM_ALTERA_NIOS2. (get_nios2_dynamic_type): New. (get_dynamic_type): Add case for EM_ALTERA_NIOS2. (is_32bit_abs_reloc): Fix EM_ALTERA_NIOS2 case. (is_16bit_abs_reloc): Likewise. (is_none_reloc): Add EM_ALTERA_NIOS2 and EM_NIOS32 cases. * NEWS: Note Altera Nios II support. * MAINTAINERS: Add Nios II maintainers.
2013-01-30include/opcode/Yufeng Zhang2-1/+10
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2. opcodes/ 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2. * aarch64-asm.c (convert_xtl_to_shll): New function. (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by calling convert_xtl_to_shll. * aarch64-dis.c (convert_shll_to_xtl): New function. (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by calling convert_shll_to_xtl. * aarch64-gen.c: Update copyright year. * aarch64-asm-2.c: Re-generate. * aarch64-dis-2.c: Re-generate. * aarch64-opc-2.c: Re-generate. gas/testsuite/ 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com> * gas/aarch64/alias.s: Add new tests. * gas/aarch64/alias.d: Update. * gas/aarch64/no-aliases.d: Update.
2013-01-28 PR gas/15069Nick Clifton2-1/+6
* tic6x-opcode-table.h: Fix encoding of BNOP instruction. * gas/tic6x/insns-c674x-pcrel.s: Add test of BNOP instruction within header based fetch packet. * gas/tic6x/insns-c674x-pcrel.d: Update expected disassembly.
generated by cgit v1.1 at 2024-12-20 08:10:40 +0000