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AgeCommit message (Expand)AuthorFilesLines
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra66-66/+70
2014-12-27Limit moxie sto/ldo offsets to 16 bitsAnthony Green2-4/+9
2014-12-06Add Visium support to opcodesEric Botcazou2-0/+341
2014-11-28Remove broken nios2 assembler dwim support.Sandra Loosemore2-6/+7
2014-11-21Support ARM Cortex-M7Terry Guo1-2/+7
2014-11-06Add mach parameter to nios2_find_opcode_hash.Sandra Loosemore2-3/+8
2014-10-31MIPS: Add Octeon 3 supportNaveen H.S1-0/+5
2014-10-23Refactoring/cleanup of nios2 opcodes and assembler code.Sandra Loosemore3-388/+551
2014-10-17opcodes, elf: annotate instructions with HWCAP2_VIS3B.Jose E. Marchesi2-1/+5
2014-10-09This is a series of patches that add support for the SPARC M7 cpu toJose E. Marchesi2-1/+39
2014-09-16NDS32/opcodes: Add audio ISA extension and modify the disassemble implemnt.Kuan-Lin Chen2-4/+10
2014-09-15Add support for MIPS R6.Andrew Bennett2-8/+113
2014-09-03[PATCH/AArch64] Implement LSE featureJiong Wang2-2/+15
2014-08-26MIPS: Make the CODE10 operand code consistent between ISAsMaciej W. Rozycki2-3/+9
2014-07-29[MIPS] Rename COPROC related macrosMatthew Fortune2-4/+11
2014-07-01Add support for the AVR Tiny series of microcontrollers.Barney Stratford2-17/+37
2014-05-20Fix MSP430 assembler to support #hi(<symbol>).Nick Clifton2-1/+6
2014-05-07Add MIPS r3 and r5 support.Andrew Bennett2-9/+54
2014-05-01include/opcode/Richard Sandiford2-10/+31
2014-04-23Add support for the MIPS eXtended Physical Address (XPA) ASE.Andrew Bennett1-0/+2
2014-04-22Remove support for the (deprecated) openrisc and or32 configurations and replaceChristian Svensson2-181/+4
2014-03-05Update copyright yearsAlan Modra65-86/+69
2013-12-16Range of element index is too large on MIPS MSA element selection instructions.Andrew Bennett2-8/+13
2013-12-13Add support for Andes NDS32:Kuan-Lin Chen2-0/+834
2013-12-07strip off +x bits on non-executable/script filesMike Frysinger2-0/+4
2013-11-20gas/testsuite/Yufeng Zhang2-1/+6
2013-11-18Add support for armv7ve to gas.Yufeng Zhang2-5/+9
2013-11-18Revert "Add support for AArch64 trace unit registers."Yufeng Zhang2-2/+9
2013-11-15gas/Yufeng Zhang2-0/+7
2013-11-112013-11-11 Catherine Moore <clm@codesourcery.com>Catherine Moore1-2/+2
2013-11-05gas/Yufeng Zhang2-1/+16
2013-11-05gas/Yufeng Zhang2-0/+7
2013-10-142013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>Chao-ying Fu2-7/+89
2013-10-11 * Removed short_hand field from opcode table andSean Keys1-36/+16
2013-08-23 PR binutils/15834Nick Clifton2-3/+8
2013-08-19include/opcode/Richard Sandiford2-4/+6
2013-08-19include/opcode/Richard Sandiford2-2/+4
2013-08-19include/opcode/Richard Sandiford2-0/+18
2013-08-05gas/Eric Botcazou1-0/+1
2013-08-04include/opcode/Richard Sandiford2-6/+59
2013-08-03include/opcode/Richard Sandiford2-11/+30
2013-08-01include/opcode/Richard Sandiford2-121/+88
2013-08-01include/opcode/Richard Sandiford2-10/+6
2013-07-24Support Intel MPXH.J. Lu2-0/+7
2013-07-14include/opcode/Richard Sandiford2-0/+14
2013-07-14include/opcode/Richard Sandiford2-0/+298
2013-07-14include/opcode/Richard Sandiford2-0/+6
2013-07-07include/opcode/Richard Sandiford2-90/+28
2013-07-07include/opcode/Richard Sandiford2-10/+13
2013-07-07include/opcode/Richard Sandiford2-5/+8
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