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AgeCommit message (Expand)AuthorFilesLines
2015-11-11Add assembler, disassembler and linker support for power9.Peter Bergner2-0/+12
2015-11-02Disassemble RX NOP instructions as such.Nick Clifton2-0/+8
2015-11-02Fix disassembly of RX zero-offset register indirect instructions.Nick Clifton2-0/+5
2015-10-28Pass noaliases_p to aarch64_decode_insnYao Qi2-1/+5
2015-10-07Avoid using 'template' C++ keywordYao Qi2-1/+6
2015-10-07Wrap include/opcode/aarch64.h in extern "C" for C++Yao Qi2-0/+12
2015-10-07New ARC implementation.Nick Clifton3-258/+592
2015-10-02Make aarch64_zero_register_p declaration starts from column oneYao Qi2-2/+7
2015-10-02[aarch64] expose disas_aarch64_insn and rename it to aarch64_decode_insnYao Qi2-0/+7
2015-09-29Add support for extensions in the .machine pseudoop on S/390, e.g. ".machine ...Dominik Vogt2-0/+9
2015-09-28FT32: define macros for instruction recognition.jamesbowman1-0/+6
2015-09-23Fix compile time warnings generated when compiling with clang.Nick Clifton2-1/+6
2015-09-22Enhance the RX disassembler to detect and report bad instructions.Nick Clifton2-0/+6
2015-09-09Make register name tables in visium.h static in order to prevent multiple def...Nick Clifton2-3/+9
2015-07-24Remove leading/trailing white spaces in ChangeLogH.J. Lu1-5/+5
2015-07-21[ARM] Support correctly spelled ARMv6KZ architecture namesMatthew Wahab2-4/+11
2015-07-03Remove ppc860, ppc750cl, ppc7450 insns from common ppc.Alan Modra2-0/+13
2015-07-01Opcodes and assembler support for Nios II R2Sandra Loosemore3-4/+1174
2015-06-19Allow for optional operands with non-zero default values.Peter Bergner2-0/+18
2015-06-04[AArch64] Add support for ARMv8.1 command line optionMatthew Wahab2-0/+13
2015-06-03[ARM] Support for ARMv8.1 command line optionMatthew Wahab2-0/+25
2015-06-02[ARM] Support for ARMv8.1 Adv.SIMD extensionMatthew Wahab1-0/+6
2015-06-02[ARM] Add support for ARMv8.1 PAN extensionMatthew Wahab2-0/+8
2015-06-02[ARM] Rework CPU feature selection in the disassemblerMatthew Wahab2-0/+5
2015-06-02[AArch64] Support for ARMv8.1a Adv.SIMD instructionsMatthew Wahab2-0/+5
2015-06-02[AArch64] Support for ARMv8.1a Limited Ordering Regions extensionMatthew Wahab2-0/+5
2015-06-01[AArch64][libopcode] Add support for PAN architecture extensionMatthew Wahab2-0/+11
2015-04-30Make RL78 disassembler and simulator respect ISA for mul/divDJ Delorie2-1/+13
2015-03-24Extend arm_feature_set struct to provide more bitsTerry Guo2-85/+134
2015-02-19Wrap a few opcodes headers in extern "C" for C++Pedro Alves7-0/+57
2015-01-28FT32 initial supportAlan Modra2-0/+104
2015-01-16S/390: Add support for IBM z13.Andreas Krebbel2-3/+24
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra66-66/+70
2014-12-27Limit moxie sto/ldo offsets to 16 bitsAnthony Green2-4/+9
2014-12-06Add Visium support to opcodesEric Botcazou2-0/+341
2014-11-28Remove broken nios2 assembler dwim support.Sandra Loosemore2-6/+7
2014-11-21Support ARM Cortex-M7Terry Guo1-2/+7
2014-11-06Add mach parameter to nios2_find_opcode_hash.Sandra Loosemore2-3/+8
2014-10-31MIPS: Add Octeon 3 supportNaveen H.S1-0/+5
2014-10-23Refactoring/cleanup of nios2 opcodes and assembler code.Sandra Loosemore3-388/+551
2014-10-17opcodes, elf: annotate instructions with HWCAP2_VIS3B.Jose E. Marchesi2-1/+5
2014-10-09This is a series of patches that add support for the SPARC M7 cpu toJose E. Marchesi2-1/+39
2014-09-16NDS32/opcodes: Add audio ISA extension and modify the disassemble implemnt.Kuan-Lin Chen2-4/+10
2014-09-15Add support for MIPS R6.Andrew Bennett2-8/+113
2014-09-03[PATCH/AArch64] Implement LSE featureJiong Wang2-2/+15
2014-08-26MIPS: Make the CODE10 operand code consistent between ISAsMaciej W. Rozycki2-3/+9
2014-07-29[MIPS] Rename COPROC related macrosMatthew Fortune2-4/+11
2014-07-01Add support for the AVR Tiny series of microcontrollers.Barney Stratford2-17/+37
2014-05-20Fix MSP430 assembler to support #hi(<symbol>).Nick Clifton2-1/+6
2014-05-07Add MIPS r3 and r5 support.Andrew Bennett2-9/+54
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