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AgeCommit message (Expand)AuthorFilesLines
2020-12-10RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.Nelson Chu1-0/+4
2020-12-10RISC-V: Control fence.i and csr instructions by zifencei and zicsr.Nelson Chu1-2/+4
2020-12-01RISC-V: Support to add implicit extensions for G.Nelson Chu1-0/+2
2020-12-01RISC-V: Improve the version parsing for arch string.Nelson Chu1-2/+2
2020-11-16aarch64: Extract Condition flag manipulation feature from Armv8.4-APrzemyslaw Wirkus1-1/+3
2020-11-09Add support for the LMBD (left-most bit detect) instruction to the PRU assemb...Spencer E. Olson1-16/+18
2020-11-09aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus1-0/+1
2020-11-06aarch64: Extract Pointer Authentication feature from Armv8.3-APrzemyslaw Wirkus1-0/+2
2020-11-04aarch64: Update feature RAS system registersPrzemyslaw Wirkus1-2/+2
2020-11-03[PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7Przemyslaw Wirkus1-1/+3
2020-10-28aarch64: Add CSR PDEC instructionPrzemyslaw Wirkus1-0/+2
2020-10-28aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus1-0/+2
2020-10-28aarch64: Add basic support for armv8.7-a architecturePrzemyslaw Wirkus1-0/+3
2020-10-26CSKY: Add version flag in eflag and fix bug in disassembling register.Cooper Qu1-0/+5
2020-09-12CSKY: Change ISA flag's type to bfd_uint64_t and fix build error.Cooper Qu1-31/+36
2020-09-10Fix compile time warnings when building for the CSKY target on a 32-bit host.Nick Clifton1-1/+1
2020-09-09CSKY: Change mvtc and mulsw's ISA flag.Cooper Qu1-0/+1
2020-09-09CSKY: Add FPUV3 instructions, which supported by ck860f.Cooper Qu1-0/+2
2020-09-08aarch64: Add support for Armv8-R system registersAlex Coplan1-2/+4
2020-09-08aarch64: Add base support for Armv8-RAlex Coplan1-1/+7
2020-09-02ubsan: v850-opc.c:412 left shift cannot be representedAlan Modra1-1/+1
2020-09-02CSKY: Add CPU CK803r3.Cooper Qu1-0/+1
2020-08-31PR26493 UBSAN: elfnn-riscv.c left shift of negative valueAlan Modra1-4/+4
2020-08-28CSKY: Support attribute section.Cooper Qu1-27/+28
2020-08-24CSKY: Add new arch CK860.Cooper Qu1-0/+2
2020-08-24CSKY: Add ck803r2 series cpu.Cooper Qu1-0/+1
2020-08-10aarch64: Don't assert on long sysreg namesAlex Coplan1-0/+2
2020-08-10[aarch64] GAS doesn't validate the architecture version for any tlbi register...Przemyslaw Wirkus1-5/+3
2020-06-30RISC-V: Support debug and float CSR as the unprivileged ones.Nelson Chu2-24/+43
2020-06-30RISC-V: Cleanup the include/opcode/riscv-opc.h.Nelson Chu1-33/+26
2020-06-22aarch64: Normalize and sort feature bit macrosAlex Coplan1-64/+47
2020-06-22RISC-V: Report warning when linking the objects with different priv specs.Nelson Chu1-4/+0
2020-06-12RISC-V: Drop the privileged spec v1.9 support.Nelson Chu2-219/+217
2020-06-11[PATCH]: aarch64: Refactor representation of system registersAlex Coplan1-0/+4
2020-06-04opcodes: discriminate endianness and insn-endianness in CGEN portsJose E. Marchesi1-2/+2
2020-06-04opcodes: support insn endianness in cgen_cpu_openJose E. Marchesi1-1/+8
2020-06-03RISC-V: Fix the error when building RISC-V linux native gdbserver.Nelson Chu1-3/+2
2020-05-28PR26044, Some targets can't be compiled with GCC 10 (tilepro)Alan Modra1-3/+1
2020-05-20[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions...Nelson Chu2-261/+324
2020-05-19Fix the ARM assembler to generate a Realtime profile for armv8-r.Alexander Fedotov1-1/+2
2020-05-11Power10 Reduced precision outer product operationsAlan Modra1-13/+16
2020-05-11PowerPC Rename powerxx to power10Alan Modra1-2/+2
2020-04-30AArch64: add GAS support for UDF instructionAlex Coplan1-0/+1
2020-03-30RISC-V: Update CSR to privileged spec 1.11.Nelson Chu1-6/+19
2020-02-20RISC-V: Support the ISA-dependent CSR checking.Nelson Chu1-244/+244
2020-02-10[binutils][arm] arm support for ARMv8.m Custom Datapath ExtensionMatthew Malcomson1-0/+9
2020-02-04ubsan: d30v: negation of -2147483648Alan Modra1-1/+1
2020-01-16[binutils][arm] PR25376 Change MVE into a CORE_HIGH featureAndre Vieira1-4/+3
2020-01-15MSP430: Fix relocation overflow when using #lo(EXP) macroJozef Lawrynowicz1-0/+15
2020-01-13tic4x: sign extension using shiftsAlan Modra1-5/+7
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