| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-12-06 | PowerPC @l, @h and @ha warnings, plus VLE e_li | Alan Modra | 1 | -0/+5 |
| 2018-12-06 | opcodes/riscv: Hide '.L0 ' fake symbols | Andrew Burgess | 1 | -0/+6 |
| 2018-12-03 | RISC-V: Accept version, supervisor ext and more than one NSE for -march. | Jim Wilson | 1 | -1/+1 |
| 2018-11-27 | RISC-V: Add .insn CA support. | Jim Wilson | 1 | -0/+4 |
| 2018-11-13 | [ARM] Improve indentation of ARM architecture declarations | Thomas Preud'homme | 1 | -254/+281 |
| 2018-11-12 | [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension | Sudakshina Das | 1 | -0/+2 |
| 2018-11-12 | [BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten... | Sudakshina Das | 1 | -0/+8 |
| 2018-11-12 | [BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex... | Sudakshina Das | 1 | -0/+2 |
| 2018-11-12 | [BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-A | Sudakshina Das | 1 | -0/+2 |
| 2018-11-06 | [BINUTILS, ARM] Add Armv8.5-A to select_arm_features and update macros. | Sudakshina Das | 1 | -4/+3 |
| 2018-10-09 | [PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRS | Sudakshina Das | 1 | -1/+4 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers | Sudakshina Das | 1 | -1/+8 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction | Sudakshina Das | 1 | -1/+12 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructions | Sudakshina Das | 1 | -0/+2 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instruction | Sudakshina Das | 1 | -1/+4 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions | Sudakshina Das | 1 | -1/+6 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-A | Sudakshina Das | 1 | -1/+4 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-A | Sudakshina Das | 1 | -1/+8 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea... | Sudakshina Das | 1 | -0/+4 |
| 2018-10-05 | [Arm, 3/3] Add Execution and Data Prediction instructions for AArch32 | Sudakshina Das | 1 | -1/+3 |
| 2018-10-05 | [Arm, 2/3] Add instruction SB for AArch32 | Sudakshina Das | 1 | -1/+3 |
| 2018-10-05 | [Arm, 1/3] Add -march=armv8.5-a and related internal feature macros to AArch32 | Sudakshina Das | 1 | -0/+5 |
| 2018-10-03 | AArch64: Add SVE constraints verifier. | Tamar Christina | 1 | -2/+8 |
| 2018-10-03 | AArch64: Refactor verifiers to make more general. | Tamar Christina | 1 | -1/+3 |
| 2018-10-03 | AArch64: Refactor err_type. | Tamar Christina | 1 | -1/+11 |
| 2018-10-03 | AArch64: Wire through instr_sequence | Tamar Christina | 1 | -2/+22 |
| 2018-10-03 | AArch64: Mark sve instructions that require MOVPRFX constraints | Tamar Christina | 1 | -2/+16 |
| 2018-10-02 | RISC-V: Add fence.tso instruction | Palmer Dabbelt | 1 | -0/+2 |
| 2018-09-20 | Andes Technology has good news for you, we plan to update the nds32 port of b... | Nick Clifton | 1 | -23/+181 |
| 2018-08-30 | RISC-V: Allow instruction require more than one extension | Jim Wilson | 1 | -2/+8 |
| 2018-08-29 | [MIPS] Add Loongson 2K1000 proccessor support. | Chenghua Xu | 1 | -0/+1 |
| 2018-08-29 | [MIPS] Add Loongson 3A2000/3A3000 proccessor support. | Chenghua Xu | 1 | -0/+1 |
| 2018-08-29 | [MIPS] Add Loongson 3A1000 proccessor support. | Chenghua Xu | 1 | -7/+2 |
| 2018-08-29 | [MIPS/GAS] Add Loongson EXT2 Instructions support. | Chenghua Xu | 1 | -0/+2 |
| 2018-08-29 | [MIPS/GAS] Split Loongson EXT Instructions from loongson3a. | Chenghua Xu | 1 | -0/+2 |
| 2018-08-29 | [MIPS/GAS] Split Loongson CAM Instructions from loongson3a | Chenghua Xu | 1 | -0/+2 |
| 2018-08-21 | Use operand->extract to provide defaults for optional PowerPC operands | Alan Modra | 1 | -18/+22 |
| 2018-08-18 | S12Z: Move opcode header to public include directory. | John Darrington | 1 | -0/+71 |
| 2018-08-06 | [ARC] Update handling AUX-registers. | claziss | 1 | -0/+1 |
| 2018-07-30 | RISC-V: Set insn info fields correctly when disassembling. | Jim Wilson | 1 | -0/+26 |
| 2018-07-30 | Add support for the C_SKY series of processors. | Andrew Jenner | 1 | -0/+110 |
| 2018-07-26 | PowerPC Improve support for Gekko & Broadway | Alex Chadwick | 1 | -1/+1 |
| 2018-07-20 | MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3a | Chenghua Xu | 1 | -0/+2 |
| 2018-06-29 | Fix AArch64 encodings for by element instructions. | Tamar Christina | 1 | -0/+2 |
| 2018-06-14 | MIPS: Add Global INValidate ASE support | Faraz Shahbazker | 1 | -1/+6 |
| 2018-06-13 | MIPS: Add CRC ASE support | Scott Egerton | 1 | -0/+3 |
| 2018-05-21 | Remove fake operand handling for extended mnemonics. | Peter Bergner | 1 | -8/+0 |
| 2018-05-15 | Implement Read/Write constraints on system registers on AArch64 | Tamar Christina | 1 | -1/+5 |
| 2018-05-15 | Allow non-fatal errors to be emitted and for disassembly notes be placed on A... | Tamar Christina | 1 | -1/+3 |
| 2018-05-15 | Modify AArch64 Assembly and disassembly functions to be able to fail and repo... | Tamar Christina | 1 | -3/+12 |
