| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2019-11-22 | Arm: Change CRC from fpu feature to archititectural extension | Mihail Ionescu | 1 | -16/+16 |
| 2019-11-07 | [Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10] | Matthew Malcomson | 1 | -0/+1 |
| 2019-11-07 | [binutils][aarch64] Matrix Multiply extension enablement [8/X] | Matthew Malcomson | 1 | -1/+9 |
| 2019-11-07 | [binutils][arm] BFloat16 enablement [4/X] | Matthew Malcomson | 1 | -0/+6 |
| 2019-11-07 | [binutils][aarch64] Bfloat16 enablement [2/X] | Matthew Malcomson | 1 | -5/+10 |
| 2019-11-07 | [gas][aarch64] Armv8.6-a option [1/X] | Matthew Malcomson | 1 | -1/+3 |
| 2019-09-17 | RISC-V: Gate opcode tables by enum rather than string. | Jim Wilson | 1 | -3/+20 |
| 2019-08-30 | [ARC] [COMMITTED] Fix FASTMATH field. | Claudiu Zissulescu | 1 | -1/+1 |
| 2019-08-08 | Update the handling of shift rotate and load/store multiple instructions in ... | Yoshinori Sato | 1 | -47/+47 |
| 2019-07-24 | [ARC] Update ARC opcode table | Claudiu Zissulescu | 1 | -0/+2 |
| 2019-07-16 | x86: fold SReg{2,3} | Jan Beulich | 1 | -0/+1 |
| 2019-07-01 | [gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AES | Matthew Malcomson | 1 | -1/+1 |
| 2019-05-24 | PowerPC add initial -mfuture instruction support | Peter Bergner | 1 | -0/+18 |
| 2019-05-16 | [PATCH 1/57][Arm][GAS]: Add support for +mve and +mve.fp | Andre Vieira | 1 | -0/+2 |
| 2019-05-09 | [binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand. | Matthew Malcomson | 1 | -0/+1 |
| 2019-05-09 | [binutils][aarch64] New sve_size_tsz_bhs iclass. | Matthew Malcomson | 1 | -0/+1 |
| 2019-05-09 | [binutils][aarch64] New SVE_Zm4_11_INDEX operand. | Matthew Malcomson | 1 | -0/+1 |
| 2019-05-09 | [binutils][aarch64] New sve_shift_tsz_bhsd iclass. | Matthew Malcomson | 1 | -0/+1 |
| 2019-05-09 | [binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand. | Matthew Malcomson | 1 | -0/+2 |
| 2019-05-09 | [binutils][aarch64] New sve_size_013 iclass. | Matthew Malcomson | 1 | -0/+1 |
| 2019-05-09 | [binutils][aarch64] New sve_size_bh iclass. | Matthew Malcomson | 1 | -0/+1 |
| 2019-05-09 | [binutils][aarch64] New sve_size_sd2 iclass. | Matthew Malcomson | 1 | -0/+1 |
| 2019-05-09 | [binutils][aarch64] New SVE_ADDR_ZX operand. | Matthew Malcomson | 1 | -0/+1 |
| 2019-05-09 | [binutils][aarch64] New SVE_Zm3_11_INDEX operand. | Matthew Malcomson | 1 | -0/+1 |
| 2019-05-09 | [binutils][aarch64] New iclass sve_size_hsd2. | Matthew Malcomson | 1 | -0/+1 |
| 2019-05-09 | [binutils][aarch64] Introduce SVE_IMM_ROT3 operand. | Matthew Malcomson | 1 | -0/+1 |
| 2019-05-09 | [binutils][aarch64] SVE2 feature extension flags. | Matthew Malcomson | 1 | -0/+7 |
| 2019-05-06 | Add load-link, store-conditional paired EVA instructions | Faraz Shahbazker | 1 | -0/+5 |
| 2019-05-01 | [BINUTILS, AArch64] Enable Transactional Memory Extension | Sudakshina Das | 1 | -1/+3 |
| 2019-04-26 | [MIPS] Add load-link, store-conditional paired instructions | Andrew Bennett | 1 | -0/+4 |
| 2019-04-25 | MIPS/include: opcode/mips.h: Update stale comment for CODE20 operand | Maciej W. Rozycki | 1 | -2/+2 |
| 2019-04-15 | [binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI | Andre Vieira | 1 | -0/+6 |
| 2019-04-11 | [BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions | Sudakshina Das | 1 | -0/+1 |
| 2019-04-01 | [GAS, Arm] CLI with architecture sensitive extensions | Andre Vieira | 1 | -7/+24 |
| 2019-03-28 | PR24390, Don't decode mtfsb field as a cr field | Alan Modra | 1 | -1/+4 |
| 2019-01-31 | S/390: Implement instruction set extensions | Andreas Krebbel | 1 | -0/+1 |
| 2019-01-25 | AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte... | Sudi Das | 1 | -2/+0 |
| 2019-01-05 | RX: include - Add RXv3 support. | Yoshinori Sato | 1 | -0/+32 |
| 2019-01-01 | Update year range in copyright notice of binutils files | Alan Modra | 69 | -69/+69 |
| 2018-12-28 | PR24028, PPC_INT_FMT | Alan Modra | 1 | -8/+0 |
| 2018-12-06 | PowerPC @l, @h and @ha warnings, plus VLE e_li | Alan Modra | 1 | -0/+5 |
| 2018-12-06 | opcodes/riscv: Hide '.L0 ' fake symbols | Andrew Burgess | 1 | -0/+6 |
| 2018-12-03 | RISC-V: Accept version, supervisor ext and more than one NSE for -march. | Jim Wilson | 1 | -1/+1 |
| 2018-11-27 | RISC-V: Add .insn CA support. | Jim Wilson | 1 | -0/+4 |
| 2018-11-13 | [ARM] Improve indentation of ARM architecture declarations | Thomas Preud'homme | 1 | -254/+281 |
| 2018-11-12 | [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension | Sudakshina Das | 1 | -0/+2 |
| 2018-11-12 | [BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten... | Sudakshina Das | 1 | -0/+8 |
| 2018-11-12 | [BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex... | Sudakshina Das | 1 | -0/+2 |
| 2018-11-12 | [BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-A | Sudakshina Das | 1 | -0/+2 |
| 2018-11-06 | [BINUTILS, ARM] Add Armv8.5-A to select_arm_features and update macros. | Sudakshina Das | 1 | -4/+3 |
