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path: root/include/opcode/riscv.h
AgeCommit message (Expand)AuthorFilesLines
2019-09-17RISC-V: Gate opcode tables by enum rather than string.Jim Wilson1-3/+20
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-12-06opcodes/riscv: Hide '.L0 ' fake symbolsAndrew Burgess1-0/+6
2018-12-03RISC-V: Accept version, supervisor ext and more than one NSE for -march.Jim Wilson1-1/+1
2018-11-27RISC-V: Add .insn CA support.Jim Wilson1-0/+4
2018-08-30RISC-V: Allow instruction require more than one extensionJim Wilson1-2/+8
2018-07-30RISC-V: Set insn info fields correctly when disassembling.Jim Wilson1-0/+26
2018-03-14RISC-V: Add .insn support.Jim Wilson1-0/+21
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-10-24RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2Andrew Waterman1-1/+1
2017-01-03Add support for the Q extension to the RISCV ISA.Kito Cheng1-0/+2
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-11-01Add support for RISC-V architecture.Nick Clifton1-0/+342