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path: root/include/opcode/aarch64.h
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2018-10-09[PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea...Sudakshina Das1-0/+4
2018-10-03AArch64: Add SVE constraints verifier.Tamar Christina1-2/+8
2018-10-03AArch64: Refactor verifiers to make more general.Tamar Christina1-1/+3
2018-10-03AArch64: Refactor err_type.Tamar Christina1-1/+11
2018-10-03AArch64: Wire through instr_sequenceTamar Christina1-2/+22
2018-10-03AArch64: Mark sve instructions that require MOVPRFX constraintsTamar Christina1-2/+16
2018-06-29Fix AArch64 encodings for by element instructions.Tamar Christina1-0/+2
2018-05-15Implement Read/Write constraints on system registers on AArch64Tamar Christina1-1/+5
2018-05-15Allow non-fatal errors to be emitted and for disassembly notes be placed on A...Tamar Christina1-1/+3
2018-05-15Modify AArch64 Assembly and disassembly functions to be able to fail and repo...Tamar Christina1-3/+12
2018-03-28Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton1-0/+1
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-12-19Correct disassembly of dot product instructions.Tamar Christina1-0/+5
2017-12-19Add support for V_4B so we can properly reject it.Tamar Christina1-0/+1
2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina1-1/+3
2017-11-09Enable the Dot Product extension by default for Armv8.4-a.Tamar Christina1-1/+2
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina1-0/+7
2017-11-09Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options...Tamar Christina1-0/+5
2017-11-09Change the type of the aarch64_feature_set typedef to unsigned long long so t...Nick Clifton1-1/+1
2017-11-08Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio...Nick Clifton1-0/+2
2017-11-02aarch64: Remove AARCH64_FEATURE_F16 from AARCH64_ARCH_V8_2Siddhesh Poyarekar1-1/+0
2017-06-28[AArch64] Add dot product support for AArch64 to binutilsTamar Christina1-0/+2
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford1-0/+6
2017-02-24[AArch64] Add a "compnum" featureRichard Sandiford1-1/+3
2017-01-04[AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy1-1/+3
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li1-3/+3
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy1-0/+5
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy1-0/+2
2016-11-11[AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy1-0/+1
2016-11-11[AArch64] Add ARMv8.3 command line option and feature flagSzabolcs Nagy1-14/+7
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford1-1/+1
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-0/+13
2016-09-21[AArch64][SVE 30/32] Add SVE instruction classesRichard Sandiford1-0/+12
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford1-0/+6
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-0/+4
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford1-0/+21
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford1-0/+7
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford1-0/+39
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford1-1/+3
2016-09-21[AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford1-0/+5
2016-09-21[AArch64][SVE 22/32] Add qualifiers for merging and zeroing predicationRichard Sandiford1-0/+3
2016-09-21[AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford1-0/+21
2016-09-21[AArch64][SVE 20/32] Add support for tied operandsRichard Sandiford1-0/+9
2016-09-21[AArch64][SVE 13/32] Add an F_STRICT flagRichard Sandiford1-1/+3
2016-07-01[AArch64] Fix +nofp16 handlingSzabolcs Nagy1-4/+7
2016-06-28[AArch64] Make register indices be full 64-bit valuesRichard Sandiford1-3/+3
2016-04-28Add support to AArch64 disassembler for verifying instructions. Add verifier...Nick Clifton1-0/+3
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-12-14[AArch64][PATCH 11/14] Add support for the 2H vector type.Matthew Wahab1-0/+1
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