| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2019-01-25 | AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte... | Sudi Das | 1 | -2/+0 |
| 2019-01-01 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2018-11-12 | [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension | Sudakshina Das | 1 | -0/+2 |
| 2018-11-12 | [BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten... | Sudakshina Das | 1 | -0/+8 |
| 2018-11-12 | [BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex... | Sudakshina Das | 1 | -0/+2 |
| 2018-11-12 | [BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-A | Sudakshina Das | 1 | -0/+2 |
| 2018-10-09 | [PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRS | Sudakshina Das | 1 | -1/+4 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers | Sudakshina Das | 1 | -1/+8 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction | Sudakshina Das | 1 | -1/+12 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructions | Sudakshina Das | 1 | -0/+2 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instruction | Sudakshina Das | 1 | -1/+4 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions | Sudakshina Das | 1 | -1/+6 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-A | Sudakshina Das | 1 | -1/+4 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-A | Sudakshina Das | 1 | -1/+8 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea... | Sudakshina Das | 1 | -0/+4 |
| 2018-10-03 | AArch64: Add SVE constraints verifier. | Tamar Christina | 1 | -2/+8 |
| 2018-10-03 | AArch64: Refactor verifiers to make more general. | Tamar Christina | 1 | -1/+3 |
| 2018-10-03 | AArch64: Refactor err_type. | Tamar Christina | 1 | -1/+11 |
| 2018-10-03 | AArch64: Wire through instr_sequence | Tamar Christina | 1 | -2/+22 |
| 2018-10-03 | AArch64: Mark sve instructions that require MOVPRFX constraints | Tamar Christina | 1 | -2/+16 |
| 2018-06-29 | Fix AArch64 encodings for by element instructions. | Tamar Christina | 1 | -0/+2 |
| 2018-05-15 | Implement Read/Write constraints on system registers on AArch64 | Tamar Christina | 1 | -1/+5 |
| 2018-05-15 | Allow non-fatal errors to be emitted and for disassembly notes be placed on A... | Tamar Christina | 1 | -1/+3 |
| 2018-05-15 | Modify AArch64 Assembly and disassembly functions to be able to fail and repo... | Tamar Christina | 1 | -3/+12 |
| 2018-03-28 | Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R... | Nick Clifton | 1 | -0/+1 |
| 2018-01-03 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2017-12-19 | Correct disassembly of dot product instructions. | Tamar Christina | 1 | -0/+5 |
| 2017-12-19 | Add support for V_4B so we can properly reject it. | Tamar Christina | 1 | -0/+1 |
| 2017-11-16 | Add new AArch64 FP16 FM{A|S} instructions. | Tamar Christina | 1 | -1/+3 |
| 2017-11-09 | Enable the Dot Product extension by default for Armv8.4-a. | Tamar Christina | 1 | -1/+2 |
| 2017-11-09 | Adds the new Fields and Operand types for the new instructions in Armv8.4-a. | Tamar Christina | 1 | -0/+7 |
| 2017-11-09 | Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options... | Tamar Christina | 1 | -0/+5 |
| 2017-11-09 | Change the type of the aarch64_feature_set typedef to unsigned long long so t... | Nick Clifton | 1 | -1/+1 |
| 2017-11-08 | Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio... | Nick Clifton | 1 | -0/+2 |
| 2017-11-02 | aarch64: Remove AARCH64_FEATURE_F16 from AARCH64_ARCH_V8_2 | Siddhesh Poyarekar | 1 | -1/+0 |
| 2017-06-28 | [AArch64] Add dot product support for AArch64 to binutils | Tamar Christina | 1 | -0/+2 |
| 2017-02-24 | [AArch64] Additional SVE instructions | Richard Sandiford | 1 | -0/+6 |
| 2017-02-24 | [AArch64] Add a "compnum" feature | Richard Sandiford | 1 | -1/+3 |
| 2017-01-04 | [AArch64] Add separate feature flag for weaker release consistent load insns | Szabolcs Nagy | 1 | -1/+3 |
| 2017-01-02 | Update year range in copyright notice of all files. | Alan Modra | 1 | -1/+1 |
| 2016-12-13 | [Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm field | Renlin Li | 1 | -3/+3 |
| 2016-11-18 | [AArch64] Add ARMv8.3 FCMLA and FCADD instructions | Szabolcs Nagy | 1 | -0/+5 |
| 2016-11-18 | [AArch64] Add ARMv8.3 combined pointer authentication load instructions | Szabolcs Nagy | 1 | -0/+2 |
| 2016-11-11 | [AArch64] Add ARMv8.3 PACGA instruction | Szabolcs Nagy | 1 | -0/+1 |
| 2016-11-11 | [AArch64] Add ARMv8.3 command line option and feature flag | Szabolcs Nagy | 1 | -14/+7 |
| 2016-09-21 | [AArch64] Add SVE condition codes | Richard Sandiford | 1 | -1/+1 |
| 2016-09-21 | [AArch64][SVE 31/32] Add SVE instructions | Richard Sandiford | 1 | -0/+13 |
| 2016-09-21 | [AArch64][SVE 30/32] Add SVE instruction classes | Richard Sandiford | 1 | -0/+12 |
| 2016-09-21 | [AArch64][SVE 29/32] Add new SVE core & FP register operands | Richard Sandiford | 1 | -0/+6 |
| 2016-09-21 | [AArch64][SVE 28/32] Add SVE FP immediate operands | Richard Sandiford | 1 | -0/+4 |
