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2000-12-01Improve MIPS32 supportNick Clifton1-0/+10
2000-10-20gas/Jakub Jelinek1-0/+5
* config/tc-sparc.c (sparc_ip): Fix a bug which caused v9_arg_p instructions to loose any special insn->architecture mask. * config/tc-sparc.c (v9a_asr_table): Add v9b ASRs. (sparc_md_end, sparc_arch_types, sparc_arch, sparc_elf_final_processing): Handle v8plusb and v9b architectures. (sparc_ip): Handle siam mode operands. Support v9b ASRs (and request v9b architecture if they are used). bfd/ * elf32-sparc.c (elf32_sparc_merge_private_bfd_data, elf32_sparc_object_p, elf32_sparc_final_write_processing): Support v8plusb. * elf64-sparc.c (sparc64_elf_merge_private_bfd_data, sparc64_elf_object_p): Support v9b. * archures.c: Declare v8plusb and v9b machines. * bfd-in2.h: Ditto. * cpu-sparc.c: Ditto. include/opcode/ * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B. Note that '3' is used for siam operand. opcodes/ * sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs. (compute_arch_mask): Add v8plusb and v9b machines. (print_insn_sparc): siam mode decoding, accept ASRs up to 25. * opcodes/sparc-opc.c: Support for Cheetah instruction set. (prefetch_table): Add #invalidate.
2000-09-22Fix ia64 gas testsuite. Update ia64 DV tables. Fix ia64 gas testsuite again.Jim Wilson1-0/+4
gas/ChangeLog * config/tc-ia64.c (dv_sem): Add "stop". (specify_resource, case IA64_RS_PR): Only handles regs 1 to 15 now. (specify_resource, case IA64_RS_PRr): New for regs 16 to 62. (specify_resource, case IA64_RS_PR63): Reorder (note == 7) test to match above. (mark_resources): Check IA64_RS_PRr. gas/testsuite/ChangeLog * gas/ia64/dv-raw-err.s: Add new testcases for PR%, 16 - 62. * gas/ia64/dv-waw-err.s: Likewise. * gas/ia64/dv-imply.d: Regenerate. * gas/ia64/dv-mutex.d, gas/ia64/dv-raw-err.l, gas/ia64/dv-safe.d, gas/ia64/dv-srlz.d, gas/ia64/dv-war-err.l, gas/ia64/dv-waw-err.l, gas/ia64/opc-f.d, gas/ia64/opc-i.d, gas/ia64/opc-m.d: Likewise. include/opcode/ChangeLog * ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP. opcodes/ChangeLog * ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change. * ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP. (lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62". * ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update. * ia64-asmtab.c: Regnerate.
2000-09-14Add support for the MIPS32Nick Clifton1-0/+17
2000-09-05doco addition.Alan Modra1-0/+4
2000-08-16Fix 3 DV bugs, and a few minor cleanups.Jim Wilson1-0/+4
gas/ * config/tc-ia64.c (specify_resource, case IA64_RS_GR): Handle postincrement modified registers. Handle IA64_OPND_R3_2 addl source registers. (note_register_values): Handle IA64_OPND_R3_2 operands. gas/testsuite/ * gas/ia64/dv-raw-err.s: Add new tests for addl and postinc. * gas/ia64/dv-raw-err.l: Likewise. * gas/ia64/dv-waw-err.l: Update sed pattern. * gas/ia64/opc-f.pl: Delete fpsub, and fpadd comment. * gas/ia64/opc-f.s, gas/ia64/opc-f.d: Regenerate. include/opcode/ * ia64.h (IA64_OPCODE_POSTINC): New. opcodes/ * ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds. Delete break, mov-immediate, nop. * ia64-opc-f.c: Delete fpsub instructions. * ia64-opc-m.c: Add POSTINC to all instructions with postincrement address operand. Rewrite using macros to avoid long lines. * ia64-opc.h (POSTINC): Define. * ia64-asmtab.c: Regenerate.
2000-08-162000-08-15 H.J. Lu <hjl@gnu.org>H.J. Lu1-0/+5
* i386.h: Swap the Intel syntax "movsx"/"movzx" due to the IgnoreSize change.
2000-08-06 * avr.h (AVR_UNDEF_P, AVR_SKIP_P, AVR_DISP0_P): New macros.Denis Chertykov1-0/+6
Move related opcodes closer to each other. Minor changes in comments, list undefined opcodes.
2000-07-262000-07-26 Dave Brolley <brolley@redhat.com>Dave Brolley1-0/+4
* cgen.h (cgen_hw_lookup_by_num): Second parameter is unsigned.
2000-07-20 cris.h: New file.Hans-Peter Nilsson1-0/+4
2000-06-27Applied Marek Michalkiewicz <marekm@linux.org.pl>'s patch to ehance the AVR ↵Nick Clifton1-0/+9
port.
2000-06-19Applied Stephane Carrez <Stephane.Carrez@worldnet.fr> patches to add supportNick Clifton1-0/+4
for m68hc11 and m68hc12 processors.
2000-06-09 * avr.h: clr,lsl,rol, ... moved after add,adc, ...Denis Chertykov1-0/+4
2000-06-07 * avr.h: New file with AVR opcodes.Denis Chertykov1-0/+4
2000-05-25Define the ALONE flag bit, for use in the opcode table.Donald Lindsay1-0/+4
2000-05-23Allow d suffix on iretAlan Modra1-0/+4
2000-05-17Fix fild.Alan Modra1-0/+4
2000-05-16* cgen/opcodes fixFrank Ch. Eigler1-0/+7
* approved by nickc [opcodes/ChangeLog] 2000-05-16 Frank Ch. Eigler <fche@redhat.com> * fr30-desc.h: Partially regenerated to account for changed CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros. * m32r-desc.h: Ditto. [include/opcode/ChangeLog] 2000-05-16 Frank Ch. Eigler <fche@redhat.com> * cgen.h (CGEN_MAX_SYNTAX_BYTES): Increase to 32. Check that it exceeds CGEN_ACTUAL_MAX_SYNTAX_BYTES, if set. (CGEN_MAX_IFMT_OPERANDS): Increase to 16. Check that it exceeds CGEN_ACTUAL_MAX_IFMT_OPERANDS, if set.
2000-05-13Fix cpu_flags for sys{enter,exit} fx{save,restore}Alan Modra1-0/+4
2000-05-13`.arch cpu_type' pseudo for x86.Alan Modra1-0/+10
2000-05-06Support for tic54x target.Timothy Wall1-0/+4
2000-05-03* ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit.J.T. Conklin1-0/+5
(PPC_OPERAND_VR): New operand flag for vector registers.
2000-05-01 * h8300.h (EOP): Add missing initializer.Jeff Law1-0/+4
2000-04-21 * hppa.h (pa_opcodes): New opcodes for PA2.0 wide modeJeff Law1-0/+8
forms of ld/st{b,h,w,d} and fld/fst{w,d} (16-bit displacements). New operand types l,y,&,fe,fE,fx added to support above forms. (pa_opcodes): Replaced usage of 'x' as source/target for floating point double-word loads/stores with 'fx'. Fr
2000-04-21IA-64 ELF support.Jim Wilson1-0/+7
2000-03-27Fix value of SHORT_A1.Nick Clifton1-0/+6
Move SHORT_AR to end of list of short instructions.
2000-03-26Mostly cosmetic. Fixes to comments. Don't start as_bad and as_warnAlan Modra1-0/+9
messages with capital. Don't malign Unixware, malign SysV386 instead.
2000-03-02Apply patch for 100679Nick Clifton1-0/+11
2000-02-25Extend the i386 gas testsuite to do some tests for intel_syntax. Fix allAlan Modra1-0/+5
the errors exposed by this addition. These were intel mode "fi... word ptr", "fi... dword ptr", "jmp Imm seg, Imm offset", "out dx,al". The failure with intel "out dx,al" was also present in att "out al,dx". Extend testsuite to catch this case too.
2000-02-24Rename 'flags' to 'signed_overflow_ok_p'Nick Clifton1-0/+6
2000-02-242000-02-24 Andrew Haley <aph@cygnus.com>Andrew Haley1-0/+6
* cgen.h (CGEN_INSN_MACH_HAS_P): New macro. (CGEN_CPU_TABLE): flags: new field. Add prototypes for new functions.
2000-02-24Forgot Changelog for last i386.h change.Alan Modra1-0/+4
2000-02-23Add IBM 370 support.Alan Modra1-0/+4
2000-02-22g2000-02-22 Andrew Haley <aph@cygnus.com>Andrew Haley1-0/+4
* mips.h: (OPCODE_IS_MEMBER): Add comment.
2000-02-22ChangeLog change only.Andrew Haley1-1/+3
2000-02-221999-12-30 Andrew Haley <aph@cygnus.com>Andrew Haley1-0/+4
* mips.h (OPCODE_IS_MEMBER): Add gp32 arg.
2000-01-15Cosmetic changes to tc-i386.[ch] + extend x86 gas testsuite jmp andAlan Modra1-0/+4
call tests + tweak intel mode far call and jmp.
1999-12-27x86 indirect jump/call syntax fixes. Disassembly fix for lcall.Alan Modra1-0/+5
1999-12-01 * mn10300.h: Add new operand types. Add new instruction formats.Jeff Law1-0/+4
1999-11-25 * hppa.h (pa_opcodes): Correctly handle immediate for PA2.0 "bb"Jeff Law1-0/+5
instruction.
1999-11-18For include/opcode:Gavin Romig-Koch1-0/+4
* mips.h (INSN_ISA5): New. For opcodes: * mips-opc.c (I5): New. (abs.ps,add.ps,alnv.ps,c.COND.ps,cvt.s.pl,cvt.s.pu,cvt.ps.s madd.ps,movf.ps,movt.ps,mul.ps,net.ps,nmadd.ps,nmsub.ps, pll.ps,plu.ps,pul.ps,puu.ps,sub.ps,suxc1,luxc1): New.
1999-11-01For include/opcode:Gavin Romig-Koch1-0/+4
* mips.h (OPCODE_IS_MEMBER): New. For gas: * config/tc-mips.c (macro_build): Use OPCODE_IS_MEMBER. (mips_ip): Use OPCODE_IS_MEMBER. For opcodes: * mips-dis.c (_print_insn_mips): Use OPCODE_IS_MEMBER.
1999-10-29Define SHORT_AR (fix for CR: 101340)Nick Clifton1-0/+4
1999-10-18Add md expression support; Cleanup alpha warningsMichael Meissner1-0/+5
1999-10-10 * hppa.h (pa_opcodes): Add load and store cache control toJeff Law1-0/+11
instructions. Add ordered access load and store. * hppa.h (pa_opcode): Add new entries for addb and addib. * hppa.h (pa_opcodes): Fix cmpb and cmpib entries. * hppa.h (pa_opcodes): Add entries for cmpb and cmpib.
1999-10-07Added seven new instructions ld, ld2w, sac, sachi, slae, st andDiego Novillo1-0/+4
st2w for d10v. Created new testsuite for d10v to verify new instructions.
1999-09-23 * hppa.h (pa_opcodes): Add "call" and "ret". Clean up "b", "bve"Jeff Law1-0/+3
and "be" using completer prefixes.
1999-09-23 * hppa.h (pa_opcodes): Add initializers to silence compiler.Jeff Law1-0/+2
1999-09-23 * hppa.h: Update comments about character usage.Jeff Law1-0/+4
1999-09-20 * hppa.h (pa_opcodes): Fix minor thinkos introduced while cleaningJeff Law1-0/+5
up the new fstw & bve instructions.
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