| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2013-12-16 | Range of element index is too large on MIPS MSA element selection instructions. | Andrew Bennett | 1 | -0/+5 |
| 2013-12-13 | Add support for Andes NDS32: | Kuan-Lin Chen | 1 | -0/+5 |
| 2013-12-07 | strip off +x bits on non-executable/script files | Mike Frysinger | 1 | -0/+4 |
| 2013-11-20 | gas/testsuite/ | Yufeng Zhang | 1 | -0/+5 |
| 2013-11-18 | Add support for armv7ve to gas. | Yufeng Zhang | 1 | -0/+6 |
| 2013-11-18 | Revert "Add support for AArch64 trace unit registers." | Yufeng Zhang | 1 | -0/+9 |
| 2013-11-15 | gas/ | Yufeng Zhang | 1 | -0/+5 |
| 2013-11-05 | gas/ | Yufeng Zhang | 1 | -0/+6 |
| 2013-11-05 | gas/ | Yufeng Zhang | 1 | -0/+5 |
| 2013-10-14 | 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> | Chao-ying Fu | 1 | -0/+13 |
| 2013-08-23 | PR binutils/15834 | Nick Clifton | 1 | -1/+6 |
| 2013-08-19 | include/opcode/ | Richard Sandiford | 1 | -0/+4 |
| 2013-08-19 | include/opcode/ | Richard Sandiford | 1 | -0/+4 |
| 2013-08-19 | include/opcode/ | Richard Sandiford | 1 | -0/+5 |
| 2013-08-04 | include/opcode/ | Richard Sandiford | 1 | -0/+10 |
| 2013-08-03 | include/opcode/ | Richard Sandiford | 1 | -0/+6 |
| 2013-08-01 | include/opcode/ | Richard Sandiford | 1 | -0/+26 |
| 2013-08-01 | include/opcode/ | Richard Sandiford | 1 | -0/+6 |
| 2013-07-24 | Support Intel MPX | H.J. Lu | 1 | -0/+6 |
| 2013-07-14 | include/opcode/ | Richard Sandiford | 1 | -0/+6 |
| 2013-07-14 | include/opcode/ | Richard Sandiford | 1 | -0/+10 |
| 2013-07-14 | include/opcode/ | Richard Sandiford | 1 | -0/+4 |
| 2013-07-07 | include/opcode/ | Richard Sandiford | 1 | -0/+19 |
| 2013-07-07 | include/opcode/ | Richard Sandiford | 1 | -0/+5 |
| 2013-07-07 | include/opcode/ | Richard Sandiford | 1 | -0/+4 |
| 2013-07-07 | include/opcode/ | Richard Sandiford | 1 | -0/+4 |
| 2013-07-07 | include/opcode/ | Richard Sandiford | 1 | -0/+8 |
| 2013-07-07 | include/opcode/ | Richard Sandiford | 1 | -0/+4 |
| 2013-06-26 | include/opcode/ | Richard Sandiford | 1 | -0/+5 |
| 2013-06-25 | bfd/ | Maciej W. Rozycki | 1 | -0/+5 |
| 2013-06-23 | include/opcode/ | Richard Sandiford | 1 | -0/+4 |
| 2013-06-17 | 2013-06-17 Catherine Moore <clm@codesourcery.com> | Catherine Moore | 1 | -0/+27 |
| 2013-06-12 | 2013-06-12 Sandra Loosemore <sandra@codesourcery.com> | Sandra Loosemore | 1 | -0/+4 |
| 2013-05-22 | include/opcode/ | Richard Sandiford | 1 | -0/+4 |
| 2013-05-10 | binutils/ChangeLog: | Andrew Pinski | 1 | -0/+9 |
| 2013-05-02 | * archures.c: Add some more MSP430 machine numbers. | Nick Clifton | 1 | -0/+4 |
| 2013-04-06 | Increase the accuracy of sparc instruction aliases. | David S. Miller | 1 | -0/+5 |
| 2013-04-03 | * elf32-v850.c (v850_elf_is_target_special_symbol): New function. | Nick Clifton | 1 | -0/+4 |
| 2013-03-28 | PR binutils/15068 | Nick Clifton | 1 | -0/+5 |
| 2013-03-27 | PR binutils/15068 | Nick Clifton | 1 | -0/+8 |
| 2013-03-21 | * elf32-h8300 (h8_relax_section): Add new relaxation of mov | Nick Clifton | 1 | -0/+5 |
| 2013-03-20 | PR gas/15082 | Nick Clifton | 1 | -0/+10 |
| 2013-03-20 | * include/opcode/tic6x.h: add tic6x_coding_dreg_(msb|lsb) field coding type in | Nick Clifton | 1 | -0/+10 |
| 2013-03-11 | Add support for AArch32 CRC instruction in ARMv8. | Kyrylo Tkachov | 1 | -0/+5 |
| 2013-02-28 | include/opcode/ | Yufeng Zhang | 1 | -0/+4 |
| 2013-02-06 | 2013-02-06 Sandra Loosemore <sandra@codesourcery.com> | Sandra Loosemore | 1 | -0/+7 |
| 2013-01-30 | include/opcode/ | Yufeng Zhang | 1 | -0/+4 |
| 2013-01-28 | PR gas/15069 | Nick Clifton | 1 | -0/+5 |
| 2013-01-24 | * v850.h: Add e3v5 support. | Nick Clifton | 1 | -0/+4 |
| 2013-01-17 | include/opcode/ | Yufeng Zhang | 1 | -0/+4 |
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