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2024-05-28Add new ELF section and segment types to readelf.Nick Clifton10-89/+134
2024-05-20readelf: add pretty printing for FDO Dlopen Metadata noteLuca Boccassi1-0/+3
2024-05-14arm: remove Maverick support from BFD.Richard Earnshaw1-1/+1
Remove the handling of Maverick from BFD. Where appropriate we handle legacy code by mapping ep9312 onto Armv4t.
2024-02-29RISC-V: Add TLSDESC reloc definitions.Tatsuyuki Ishi1-0/+5
bfd/ * elfxx-riscv.c: Add 5 TLSDESC reloc descriptions. * reloc.c: Likewise. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. include/ * elf/riscv.h: Add 5 TLSDESC reloc descriptions.
2024-02-24xtensa: move xtensa_make_property_section from bfd to gasAlan Modra1-1/+1
This function is only used by gas, so move it there. Necessary for gas to keep track of group sections as they are created. PR 25333 bfd/ * elf32-xtensa.c (xtensa_make_property_section): Delete. (xtensa_property_section_name): Make public. include/ * elf/xtensa.h (xtensa_make_property_section): Delete. (xtensa_property_section_name): Declare gas/ * config/tc-xtensa.c (xtensa_make_property_section): New, moved from elf32-xtensa.c.
2024-02-12Add support to readelf for the PT_OPENBSD_SYSCALLS segment type.Frederic Cambus1-0/+1
binutils * readelf.c (get_segment_type): Handle PT_OPENBSD_SYSCALLS segment type. include * elf/common.h (PT_OPENBSD_SYSCALLS): Define.
2024-02-08x86-64: Add R_X86_64_CODE_6_GOTTPOFFH.J. Lu1-0/+20
For add %reg1, name@gottpoff(%rip), %reg2 and add name@gottpoff(%rip), %reg1, %reg2 add #define R_X86_64_CODE_6_GOTTPOFF 50 if the instruction starts at 6 bytes before the relocation offset. They are similar to R_X86_64_GOTTPOFF. Linker can covert GOTTPOFF to add $name@tpoff, %reg1, %reg2 Rewrite fx_tcbit, fx_tcbit2 and fx_tcbit3 usage to generate R_X86_64_GOTPCRELX, R_X86_64_REX_GOTPCRELX, R_X86_64_CODE_4_GOTPCRELX, R_X86_64_CODE_4_GOTTPOFF, R_X86_64_CODE_4_GOTPC32_TLSDESC and R_X86_64_CODE_6_GOTTPOFF. NB: There is no need to check BFD_RELOC_X86_64_CODE_4_GOTTPOFF in md_assemble since there is only BFD_RELOC_X86_64_GOTTPOFF at this stage, which will be converted to BFD_RELOC_X86_64_CODE_4_GOTTPOFF or BFD_RELOC_X86_64_CODE_6_GOTTPOFF in i386_validate_fix. 5 relocations: #define R_X86_64_CODE_5_GOTPCRELX 46 #define R_X86_64_CODE_5_GOTTPOFF 47 #define R_X86_64_CODE_5_GOTPC32_TLSDESC 48 #define R_X86_64_CODE_6_GOTPCRELX 49 #define R_X86_64_CODE_6_GOTPC32_TLSDESC 51 are added for completeness and they are unused. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX, R_X86_64_CODE_6_GOTTPOFF and R_X86_64_CODE_6_GOTPC32_TLSDESC. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX, R_X86_64_CODE_6_GOTTPOFF and R_X86_64_CODE_6_GOTPC32_TLSDESC. (elf_x86_64_check_tls_transition): Handle R_X86_64_CODE_6_GOTTPOFF. (elf_x86_64_tls_transition): Likewise. (elf_x86_64_scan_relocs): Handle R_X86_64_CODE_6_GOTTPOFF. Issue an error for R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX and R_X86_64_CODE_6_GOTPC32_TLSDESC. (elf_x86_64_relocate_section): Handle R_X86_64_CODE_6_GOTTPOFF. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_5_GOTPCRELX, BFD_RELOC_X86_64_CODE_5_GOTTPOFF, BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC, BFD_RELOC_X86_64_CODE_6_GOTPCRELX, BFD_RELOC_X86_64_CODE_6_GOTTPOFF and BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. elfcpp/ * x86_64.h (R_X86_64_CODE_5_GOTPCRELX): New. (R_X86_64_CODE_5_GOTTPOFF): Likewise. (R_X86_64_CODE_5_GOTPC32_TLSDESC): Likewise. (R_X86_64_CODE_6_GOTPCRELX): Likewise. (R_X86_64_CODE_6_GOTTPOFF): Likewise. (R_X86_64_CODE_6_GOTPC32_TLSDESC): Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. (md_assemble): Don't check BFD_RELOC_X86_64_CODE_4_GOTTPOFF. Allow "add %reg1, foo@gottpoff(%rip), %reg2". (output_disp): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. Rewrite setting fx_tcbitX bits for BFD_RELOC_X86_64_GOTTPOFF, BFD_RELOC_X86_64_GOTPC32_TLSDESC and BFD_RELOC_32_PCREL. (md_apply_fix): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. (i386_validate_fix): Rewrite fx_tcbitX bit checking for BFD_RELOC_X86_64_GOTTPOFF, BFD_RELOC_X86_64_GOTPC32_TLSDESC and BFD_RELOC_32_PCREL. (tc_gen_reloc): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. * testsuite/gas/i386/x86-64-gottpoff.d: Updated. * testsuite/gas/i386/x86-64-gottpoff.s: Add tests for "add %reg1, foo@gottpoff(%rip), %reg2" and "add foo@gottpoff(%rip), %reg, %reg2". gold/ * x86_64.cc (Target_x86_64::optimize_tls_reloc): Handle R_X86_64_CODE_6_GOTTPOFF. (Target_x86_64::Scan::get_reference_flags): Likewise. (Target_x86_64::Scan::local): Likewise. (Target_x86_64::Scan::global): Likewise. (Target_x86_64::Relocate::relocate): Likewise. (Target_x86_64::Relocate::relocate_tls): Likewise. (Target_x86_64::Relocate::tls_ie_to_le): Handle. R_X86_64_CODE_6_GOTTPOFF. * testsuite/x86_64_ie_to_le.s: Add tests for "add %reg1, foo@gottpoff(%rip), %reg2" and "add foo@gottpoff(%rip), %reg, %reg2". * testsuite/x86_64_ie_to_le.sh: Updated. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX, R_X86_64_CODE_6_GOTTPOFF and R_X86_64_CODE_6_GOTPC32_TLSDESC. ld/ * testsuite/ld-x86-64/tlsbindesc.s: Add R_X86_64_CODE_6_GOTTPOFF tests. * testsuite/ld-x86-64/tlsbindesc.d: Updated. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise.
2024-01-04Update year range in copyright notice of binutils filesAlan Modra85-85/+85
Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out */po/*.pot which we don't update frequently.
2023-12-29LoongArch: include: Add support for tls le relax.changjiachen1-0/+12
Add new relocs number for tls le relax. include/ChangeLog: * elf/loongarch.h: (RELOC_NUMBER (R_LARCH_TLS_LE_HI20_R, 121)): New relocs number. (RELOC_NUMBER (R_LARCH_TLS_LE_ADD_R, 122)): Likewise. (RELOC_NUMBER (R_LARCH_TLS_LE_LO12_R, 123)): Likewise.
2023-12-28x86-64: Add R_X86_64_CODE_4_GOTTPOFF/R_X86_64_CODE_4_GOTPC32_TLSDESCH.J. Lu1-0/+6
For add name@gottpoff(%rip), %reg mov name@gottpoff(%rip), %reg add # define R_X86_64_CODE_4_GOTTPOFF 44 and for lea name@tlsdesc(%rip), %reg add # define R_X86_64_CODE_4_GOTPC32_TLSDESC 45 if the instruction starts at 4 bytes before the relocation offset. They are similar to R_X86_64_GOTTPOFF and R_X86_64_GOTPC32_TLSDESC, respectively. Linker can covert GOTTPOFF to add $name@tpoff, %reg mov $name@tpoff, %reg and GOTPC32_TLSDESC to mov $name@tpoff, %reg mov name@gottpoff(%rip), %reg if the instruction is encoded with the REX2 prefix when possible. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. (elf_x86_64_check_tls_transition): Handle R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC. (elf_x86_64_tls_transition): Likewise. (elf_x86_64_scan_relocs): Likewise. (elf_x86_64_relocate_section): Likewise. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. (md_assemble): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF. (output_insn): Don't add empty REX prefix with REX2 prefix. (output_disp): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. (md_apply_fix): Likewise. (i386_validate_fix): Generate BFD_RELOC_X86_64_CODE_4_GOTTPOFF or BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC if ixp->fx_tcbit3 is set. (tc_gen_reloc): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. * testsuite/gas/i386/x86-64-gottpoff.d: New file. * testsuite/gas/i386/x86-64-gottpoff.s: Likewise. * testsuite/gas/i386/x86-64-tlsdesc.d: Likewise. * testsuite/gas/i386/x86-64-tlsdesc.s: Likewise. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC ld/ * testsuite/ld-x86-64/tlsbindesc.d: Updated. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc.s: Add R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC tests.
2023-12-28x86-64: Add R_X86_64_CODE_4_GOTPCRELXH.J. Lu1-1/+5
For mov name@GOTPCREL(%rip), %reg test %reg, name@GOTPCREL(%rip) binop name@GOTPCREL(%rip), %reg where binop is one of adc, add, add, cmp, or, sbb, sub, xor instructions, add # define R_X86_64_CODE_4_GOTPCRELX 43 if the instruction starts at 4 bytes before the relocation offset. It similar to R_X86_64_GOTPCRELX. Linker can treat R_X86_64_CODE_4_GOTPCRELX as R_X86_64_GOTPCREL or convert the above instructions to lea name(%rip), %reg mov $name, %reg test $name, %reg binop $name, %reg if the instruction is encoded with the REX2 prefix when possible. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_4_GOTPCRELX. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_convert_load_reloc): Handle R_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_scan_relocs): Likewise. (elf_x86_64_relocate_section): Likewise. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * write.h (fix): Add fx_tcbit3. Change fx_unused to 1 bit. * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (tc_gen_reloc): Likewise. (output_disp): Set fixP->fx_tcbit3 for REX2 prefix. (i386_validate_fix): Generate BFD_RELOC_X86_64_CODE_4_GOTPCRELX if fixp->fx_tcbit3 is set. * config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (TC_FORCE_RELOCATION_ABS): Likewise. * testsuite/gas/i386/x86-64-gotpcrel.s: Add tests for R_X86_64_CODE_4_GOTPCRELX. * testsuite/gas/i386/x86-64-localpic.s: Likewise. * testsuite/gas/i386/x86-64-gotpcrel.d: Updated. * testsuite/gas/i386/x86-64-localpic.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_4_GOTPCRELX. ld/ * testsuite/ld-x86-64/apx-load1.s: New file. * testsuite/ld-x86-64/apx-load1a.d: Likewise. * testsuite/ld-x86-64/apx-load1b.d: Likewise. * testsuite/ld-x86-64/apx-load1c.d: Likewise. * testsuite/ld-x86-64/apx-load1d.d: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run apx-load1a, apx-load1b, apx-load1c and apx-load1d.
2023-12-28x86: Add NT_X86_SHSTK noteSchimpe, Christina1-0/+3
Define NT_X86_SHSTK which is the note for x86 Shadow Stack (SHSTK) to support Intel SHSTK in Linux kernel. For now only userspace shadow stack and kernel IBT are supported by the linux kernel. This note should be used instead of NT_X86_CET introduced in the commit "x86: Add NT_X86_CET note", as it is outdated and only used by old binutils versions.
2023-12-25LoongArch: Add support for TLS LD/GD/DESC relaxationmengqinggang1-0/+4
The pcalau12i + addi.d of TLS LD/GD/DESC relax to pcaddi. Relaxation is only performed when the TLS model transition is not possible.
2023-12-25LoongArch: Add new relocs and macro for TLSDESC.Lulu Cai1-1/+21
The normal DESC instruction sequence is: pcalau12i $a0,%desc_pc_hi20(var) #R_LARCH_TLS_DESC_PC_HI20 addi.d $a0,$a0,%desc_pc_lo12(var) #R_LARCH_TLS_DESC_PC_LO12 ld.d $ra,$a0,%desc_ld(var) #R_LARCH_TLS_DESC_LD jirl $ra,$ra,%desc_call(var) #R_LARCH_TLS_DESC_CALL add.d $a0,$a0,$tp
2023-12-18LoongArch: Add new relocation R_LARCH_CALL36mengqinggang1-0/+2
R_LARCH_CALL36 is used for medium code model function call pcaddu18i+jirl, and these two instructions must adjacent. The LoongArch ABI v2.20 at here: https://github.com/loongson/la-abi-specs.
2023-11-10bfd, binutils: add gfx11 amdgpu architecturesSimon Marchi1-0/+3
Teach bfd and readelf about some recent gfx11 architectures. This code is taken from the rocgdb 5.7.x branch [1]. [1] https://github.com/rocm-Developer-Tools/rocgdb/tree/rocm-5.7.x bfd/ChangeLog: * archures.c (bfd_mach_amdgcn_gfx1100, bfd_mach_amdgcn_gfx1101, bfd_mach_amdgcn_gfx1102): New. * bfd-in2.h (bfd_mach_amdgcn_gfx1100, bfd_mach_amdgcn_gfx1101, bfd_mach_amdgcn_gfx1102): New. * cpu-amdgcn.c (arch_info_struct): Add entries for bfd_mach_amdgcn_gfx1100, bfd_mach_amdgcn_gfx1101, bfd_mach_amdgcn_gfx1102. binutils/ChangeLog: * readelf.c (decode_AMDGPU_machine_flags): Handle gfx1100, gfx1101, gfx1102. include/ChangeLog: * elf/amdgpu.h (EF_AMDGPU_MACH_AMDGCN_GFX1100, EF_AMDGPU_MACH_AMDGCN_GFX1101, EF_AMDGPU_MACH_AMDGCN_GFX1102): New. Change-Id: I95a8a62942e359781a1c9fa2079950fbcf2a78b8 Co-Authored-By: Laurent Morichetti <laurent.morichetti@amd.com> Cc: Lancelot Six <lancelot.six@amd.com>
2023-11-10MIPS: Change all E_MIPS_* to EF_MIPS_*Ying Huang1-38/+81
2023-11-06RISC-V: Moved out linker internal relocations after R_RISCV_max.Nelson Chu1-0/+8
Just the lightest modifications about this, without any further checks and considering --emit-relocs. We will need to improve it in the future, but first do this to avoid conflicts between linker internal relocations and the new definition of psabi. For example, TLSDESC relocs. Passed riscv-gnu-toolchain regressions, so should be safe enough to commit. Co-authored-by: Tsukasa OI <research_trasio@irq.a4lg.com> bfd/ * reloc.c: Removed linker internal relocations. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * elfnn-riscv.c: Defined R_RISCV_DELETE in include/elf/riscv.h. * elfxx-riscv.c (howto_table, howto_table_internal): Moved linker internal relocations from howto_table into howto_table_internal. (riscv_reloc_map): Removed linker internal relocations mapping. (riscv_elf_rtype_to_howto): Return howto of linker internal relocations from howto_table_internal. include/ * elf/riscv.h: Defined linker internal relocations after R_RISCV_max.
2023-10-30Accept and ignore the R_BPF_64_NODLYD32 relocation.Nick Clifton1-2/+2
2023-10-20bfd: microblaze: Add 32_NONE reloc typeNeal Frager1-0/+1
This patch adds the R_MICROBLAZE_32_NONE relocation type. This is a 32-bit reloc that stores the 32-bit pc relative value in two words (with an imm instruction). Add test case to gas test suite. Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-10-07Revert "opcodes: microblaze: Add new bit-field instructions"Michael J. Eager1-1/+0
This reverts commit 6bbf249557ba17cfebe01c67370df4da9e6a56f9. Maciej W. Rozycki <macro@orcam.me.uk>: Yet it has caused numerous regressions: microblaze-elf +FAIL: unordered .debug_info references to .debug_ranges microblaze-elf +FAIL: binutils-all/pr26548 microblaze-elf +FAIL: readelf -Wwi pr26548e (reason: unexpected output) microblaze-elf +FAIL: readelf --debug-dump=loc locview-1 (reason: unexpected output) Yet it has caused numerous regressions: microblaze-elf +FAIL: unordered .debug_info references to .debug_ranges microblaze-elf +FAIL: binutils-all/pr26548 microblaze-elf +FAIL: readelf -Wwi pr26548e (reason: unexpected output) ...
2023-10-06gdb: support rseq auxvsIlya Leoshkevich1-0/+2
Linux kernel commit commit 317c8194e6ae ("rseq: Introduce feature size and alignment ELF auxiliary vector entries") introduced two new auxvs: AT_RSEQ_FEATURE_SIZE and AT_RSEQ_ALIGN. Support them in GDB. This fixes auxv.exp on kernels >= v6.3. Change-Id: I8966c4d5c73eb7b45de6d410a9b28a6628edad2e Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=30540 Approved-By: Tom Tromey <tom@tromey.com>
2023-10-06opcodes: microblaze: Add new bit-field instructionsNeal Frager1-0/+1
This patches adds new bsefi and bsifi instructions. BSEFI- The instruction shall extract a bit field from a register and place it right-adjusted in the destination register. The other bits in the destination register shall be set to zero. BSIFI- The instruction shall insert a right-adjusted bit field from a register at another position in the destination register. The rest of the bits in the destination register shall be unchanged. Further documentation of these instructions can be found here: https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref This patch has been tested for years of AMD Xilinx Yocto releases as part of the following patch set: https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils Signed-off-by: nagaraju <nagaraju.mekala@amd.com> Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> Signed-off-by: Neal Frager <neal.frager@amd.com> Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-09-29x86-64: Add -z mark-plt and -z nomark-pltH.J. Lu1-0/+5
The PLT entry in executables and shared libraries contains an indirect branch, like jmp *foo@GOTPCREL(%rip) push $index_foo jmp .PLT0 or endbr64 jmp *foo@GOTPCREL(%rip) NOP padding which is used to branch to the function, foo, defined in another object. Each R_X86_64_JUMP_SLOT relocation has a corresponding PLT entry. The dynamic tags have been added to the x86-64 psABI to mark such PLT entries: https://gitlab.com/x86-psABIs/x86-64-ABI/-/commit/6d824a52a42d173eb838b879616c1be5870b593e Add an x86-64 linker option, -z mark-plt, to mark PLT entries with #define DT_X86_64_PLT (DT_LOPROC + 0) #define DT_X86_64_PLTSZ (DT_LOPROC + 1) #define DT_X86_64_PLTENT (DT_LOPROC + 3) 1. DT_X86_64_PLT: The address of the procedure linkage table. 2. DT_X86_64_PLTSZ: The total size, in bytes, of the procedure linkage table. 3. DT_X86_64_PLTENT: The size, in bytes, of a procedure linkage table entry. and set the r_addend field of the R_X86_64_JUMP_SLOT relocation to the memory offset of the indirect branch instruction. The dynamic linker can use these tags to update the PLT section to direct branch. bfd/ * elf-linker-x86.h (elf_linker_x86_params): Add mark_plt. * elf64-x86-64.c (elf_x86_64_finish_dynamic_symbol): Set the r_addend of R_X86_64_JUMP_SLOT to the indirect branch offset in PLT entry for -z mark-plt. * elfxx-x86.c (_bfd_x86_elf_size_dynamic_sections): Add DT_X86_64_PLT, DT_X86_64_PLTSZ and DT_X86_64_PLTENT for -z mark-plt. (_bfd_x86_elf_finish_dynamic_sections): Set DT_X86_64_PLT, DT_X86_64_PLTSZ and DT_X86_64_PLTENT. (_bfd_x86_elf_get_synthetic_symtab): Ignore addend for JUMP_SLOT relocation. (_bfd_x86_elf_link_setup_gnu_properties): Set plt_indirect_branch_offset. * elfxx-x86.h (elf_x86_plt_layout): Add plt_indirect_branch_offset. binutils/ * readelf.c (get_x86_64_dynamic_type): New function. (get_dynamic_type): Call get_x86_64_dynamic_type. include/ * elf/x86-64.h (DT_X86_64_PLT): New. (DT_X86_64_PLTSZ): Likewise. (DT_X86_64_PLTENT): Likewise. ld/ * ld.texi: Document -z mark-plt and -z nomark-plt. * emulparams/elf32_x86_64.sh: Source x86-64-plt.sh. * emulparams/elf_x86_64.sh: Likewise. * emulparams/x86-64-plt.sh: New file. * testsuite/ld-x86-64/mark-plt-1.s: Likewise. * testsuite/ld-x86-64/mark-plt-1a-x32.d: Likewise. * testsuite/ld-x86-64/mark-plt-1a.d: Likewise. * testsuite/ld-x86-64/mark-plt-1b-x32.d: Likewise. * testsuite/ld-x86-64/mark-plt-1b.d: Likewise. * testsuite/ld-x86-64/mark-plt-1c-x32.d: Likewise. * testsuite/ld-x86-64/mark-plt-1c.d: Likewise. * testsuite/ld-x86-64/mark-plt-1d-x32.d: Likewise. * testsuite/ld-x86-64/mark-plt-1d.d: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run -z mark-plt tests.
2023-09-28Add support to readelf for the PT_OPENBSD_NOBTCFI segment type.Frederic Cambus1-0/+1
2023-09-25Revert "arc: Update opcode related include files for ARCv3."Claudiu Zissulescu3-195/+40
This reverts commit 04414221df53bb5129e34bec354dae3121db436a.
2023-09-25arc: Update opcode related include files for ARCv3.Claudiu Zissulescu3-40/+195
Add new ARCv3 CPUs and required bits to decode/encode ARCv3 ISA opcodes. Fix 32 bit relocations which were set as signed but should be bitfield: ARC_32_ME, ARC_GLOB_DAT, ARC_JMP_SLOT, ARC_RELATIVE. Remove non-ABI relocation ARC_32_ME_S. include/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> Cupertino Miranda <cupertinomiranda@gmail.com> Bruno Mauricio <brunoasmauricio@gmail.com> * include/elf/arc-cpu.def: Add new HS5x and HS6x CPUs. * include/elf/arc-reloc.def: Add new ARC64 relocations. * include/elf/arc.h (EF_ARC_CPU_ARC64): New define. * include/opcode/arc-attrs.h (FEATURE_LIST_NAME): Update predicate. * include/opcode/arc-func.h: Update formating. (replace_disp8ls): New function. (replace_disp9s): Likewise. (replace_disp6s): Likewise. (replace_disp7s): Likewise. (replace_disp12s): Likewise. * include/opcode/arc.h (ARC_OPCODE_ARC64): New define. (ARC_OPCODE_ARC32): Likewise. (ARC_OPERAND_FP): Likewise. (HARD_FIELDF): Likewise. (ARC_OPCODE_ARCVx): New macro. (arc_flag_class): Update structure to hold new extract/insert functions for flags. (INSN3OP): Update macro. (FP_SIZE, TPOF, DPOF, SOPF, COPF, CONVOPS): New enums. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2023-08-21aarch64/sme2: Teach binutils/BFD about the NT_ARM_ZT register setLuis Machado1-0/+2
The Scalable Matrix Extension v2 (SME2) defines a new register, ZT0, that the Linux Kernel handles through a new NT_ARM_ZT register set. Teach binutils/BFD about it so that gdb can make use of it for reading and writing core files. This also enables readelf/objdump to show the correct identification for the NT_ARM_ZT register set. Validated under Fast Models.
2023-08-16kvx: New port.Paul Iannetta2-0/+196
2023-08-02Revert "2.41 Release sources"Sam James1-0/+6
This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton1-6/+0
2023-07-30bpf: include, bfd, opcodes: add EF_BPF_CPUVER ELF header flagsJose E. Marchesi1-0/+5
This patch adds support for EF_BPF_CPUVER bits in the ELF machine-dependent header flags. These bits encode the BPF CPU version for which the object file has been compiled for. The BPF assembler is updated so it annotates the object files it generates with these bits. The BPF disassembler is updated so it honors EF_BPF_CPUVER to use the appropriate ISA version if the user didn't specify an explicit ISA version in the command line. Note that a value of zero in EF_BPF_CPUVER is interpreted by the disassembler as "use the later supported version" (the BPF CPU versions start with v1.) The readelf utility is updated to pretty print EF_BPF_CPUVER when it prints out the ELF header: $ readelf -h a.out ELF Header: ... Flags: 0x4, CPU Version: 4 Tested in bpf-unknown-none. include/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * elf/bpf.h (EF_BPF_CPUVER): Define. * opcode/bpf.h (BPF_XBPF): Change from 0xf to 0xff so it fits in EF_BPF_CPUVER. binutils/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * readelf.c (get_machine_flags): Recognize and pretty print BPF machine flags. opcodes/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-dis.c: Initialize asm_bpf_version to -1. (print_insn_bpf): Set BPF ISA version from the cpu version ELF header flags if no explicit version set in the command line. * disassemble.c (disassemble_init_for_target): Remove unused code. gas/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.h (elf_tc_final_processing): Define. * config/tc-bpf.c (bpf_elf_final_processing): New function.
2023-07-21DesCGENization of the BPF binutils portJose E. Marchesi1-0/+1
CGEN is cool, but the BPF architecture is simply too bizarre for it. The weird way of BPF to handle endianness in instruction encoding, the weird C-like alternative assembly syntax, the weird abuse of multi-byte (or infra-byte) instruction fields as opcodes, the unusual presence of opcodes beyond the first 32-bits of some instructions, are all examples of what makes it a PITA to continue using CGEN for this port. The bpf.cpu file is becoming so complex and so nested with p-macros that it is very difficult to read, and quite challenging to update. Also, every time we are forced to change something in CGEN to accommodate BPF requirements (which is often) we have to do extensive testing to make sure we do not break any other target using CGEN. This is getting un-maintenable. So I have decided to bite the bullet and revamp/rewrite the port so it no longer uses CGEN. Overall, this involved: * To remove the cpu/bpf.{cpu,opc} descriptions. * To remove the CGEN generated files. * To replace the CGEN generated opcodes table with a new hand-written opcodes table for BPF. * To replace the CGEN generated disassembler wih a new disassembler that uses the new opcodes. * To replace the CGEN generated assembler with a new assembler that uses the new opcodes. * To replace the CGEN generated simulator with a new simulator that uses the new opcodes. [This is pushed in GDB in another patch.] * To adapt the build systems to the new situation. Additionally, this patch introduces some extensions and improvements: * A new BPF relocation BPF_RELOC_BPF_DISP16 plus corresponding ELF relocation R_BPF_GNU_64_16 are added to the BPF BFD port. These relocations are used for section-relative 16-bit offsets used in load/store instructions. * The disassembler now has support for the "pseudo-c" assembly syntax of BPF. What dialect to use when disassembling is controlled by a command line option. * The disassembler now has support for dumping instruction immediates in either octal, hexadecimal or decimal. The used output base is controlled by a new command-line option. * The GAS BPF test suite has been re-structured and expanded in order to test the disassembler pseudoc syntax support. Minor bugs have been also fixed there. The assembler generic tests that were disabled for bpf-*-* targets due to the previous implementation of pseudoc syntax are now re-enabled. Additional tests have been added to test the new features of the assembler. .dump files are no longer used. * The linker BPF test suite has been adapted to the command line options used by the new disassembler. The result is very satisfactory. This patchs adds 3448 lines of code and removes 10542 lines of code. Tested in: * Target bpf-unknown-none with 64-bit little-endian host and 32-bit little-endian host. * Target x86-64-linux-gnu with --enable-targets=all Note that I have not tested in a big-endian host yet. I will do so once this lands upstream so I can use the GCC compiler farm. I have not included ChangeLog entries in this patch: these would be massive and not very useful, considering this is pretty much a rewrite of the port. I beg the indulgence of the global maintainers.
2023-06-28LoongArch: Add R_LARCH_64_PCREL relocation supportmengqinggang1-0/+2
Gas defaults to emit R_LARCH_ADD64/R_LARCH_SUB64 unless explcitly declared to emit R_LARCH_64_PCREL. The LoongArch ABI at here: https://github.com/loongson/la-abi-specs/blob/release/la-abi.adoc bfd/ChangeLog: * bfd-in2.h (not): Add R_LARCH_64_PCREL * elfnn-loongarch.c (perform_relocation): Likewise. * elfxx-loongarch.c: Likewise. * libbfd.h: Likewise. * reloc.c: Likewise. gas/ChangeLog: * config/tc-loongarch.c (loongarch_args_parser_can_match_arg_helper): (md_apply_fix): Add R_LARCH_64_PCREL. * testsuite/gas/loongarch/64_pcrel.d: New test. * testsuite/gas/loongarch/64_pcrel.s: New test. include/ChangeLog: * elf/loongarch.h (RELOC_NUMBER): Add R_LARCH_64_PCREL. ld/ChangeLog: * testsuite/ld-loongarch-elf/ld-loongarch-elf.exp: Add test. * testsuite/ld-loongarch-elf/64_pcrel.d: New test. * testsuite/ld-loongarch-elf/64_pcrel.s: New test.
2023-06-15Add MIPS Allegrex CPU as a MIPS2-based CPUDavid Guillen Fandos1-0/+1
The Allegrex CPU was created by Sony Interactive Entertainment to power their portable console, the PlayStation Portable. The pspdev organization maintains all sorts of tools to create software for said device including documentation. Signed-off-by: David Guillen Fandos <david@davidgf.net>
2023-05-30LoongArch: include: Add support for linker relaxation.mengqinggang1-0/+20
Add relocs and gas LARCH_opts.relax option. include/ChangeLog: * elf/loongarch.h: Add relocs. * opcode/loongarch.h: Add LARCH_opts.relax and macro LARCH_NOP.
2023-05-22Re: readelf: Support SHT_RELR/DT_RELR for -rAlan Modra1-1/+4
Revert value of DT_ENCODING to as it was before commit a7fd118627, and adjust readelf. include/ * elf/common.h (DT_ENCODING): Set back to 32. binutils/ * readelf.c (struct filedata): Don't size dynamic_info array using DT_ENCODING.
2023-05-19RISC-V: Support subtraction of .uleb128.Kuan-Lin Chen1-0/+3
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/commit/96d6e190e9fc04a8517f9ff7fb9aed3e9876cbd6 There are some known limitations for now, * Do not shrink the length of the uleb128 value, even if the value is reduced after relaxations. Also reports error if the length grows up. * The R_RISCV_SET_ULEB128 needs to be paired with and be placed before the R_RISCV_SUB_ULEB128. bfd/ * bfd-in2.h: Regenerated. * elfnn-riscv.c (perform_relocation): Perform R_RISCV_SUB_ULEB128 and R_RISCV_SET_ULEB128 relocations. Do not shrink the length of the uleb128 value, and report error if the length grows up. Called the generic functions, _bfd_read_unsigned_leb128 and _bfd_write_unsigned_leb128, to encode the uleb128 into the section contents. (riscv_elf_relocate_section): Make sure that the R_RISCV_SET_ULEB128 must be paired with and be placed before the R_RISCV_SUB_ULEB128. * elfxx-riscv.c (howto_table): Added R_RISCV_SUB_ULEB128 and R_RISCV_SET_ULEB128. (riscv_reloc_map): Likewise. (riscv_elf_ignore_reloc): New function. * libbfd.h: Regenerated. * reloc.c (BFD_RELOC_RISCV_SET_ULEB128, BFD_RELOC_RISCV_SUB_ULEB128): New relocations to support .uleb128 subtraction. gas/ * config/tc-riscv.c (md_apply_fix): Added BFD_RELOC_RISCV_SET_ULEB128 and BFD_RELOC_RISCV_SUB_ULEB128. (s_riscv_leb128): Updated to allow uleb128 subtraction. (riscv_insert_uleb128_fixes): New function, scan uleb128 subtraction expressions and insert fixups for them. (riscv_md_finish): Called riscv_insert_uleb128_fixes for all sections. include/ * elf/riscv.h ((R_RISCV_SET_ULEB128, (R_RISCV_SUB_ULEB128): Defined. ld/ * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated. * testsuite/ld-riscv-elf/uleb128*: New testcase for uleb128 subtraction. binutils/ * testsuite/binutils-all/nm.exp: Updated since RISCV supports .uleb128.
2023-03-23Add support to readelf for the PT_OPENBSD_MUTABLE segment type.Frederic Cambus1-0/+1
binutils * readelf.c (get_segment_type): Handle PT_OPENBSD_MUTABLE segment type. include * elf/common.h (PT_OPENBSD_MUTABLE): Define.
2023-03-16readelf: add support for QNT_STACK note subsectionsClément Chigot1-0/+13
QNX provides some .note subsections. QNT_STACK is the one controling the stack allocation. bfd/ChangeLog: * elf.c (BFD_QNT_CORE_INFO): Delete. (BFD_QNT_CORE_STATUS): Likewise. (BFD_QNT_CORE_GREG): Likewise. (BFD_QNT_CORE_FPREG): Likewise. (elfcore_grok_nto_note): Replace BFD_QNT_* by QNT_*. binutils/ChangeLog: * readelf.c (get_qnx_elfcore_note_type): New function. (print_qnx_note): New function. (process_note): Add support for QNX support. include/ChangeLog: * elf/common.h (QNT_DEBUG_FULLPATH): New define. (QNT_DEBUG_RELOC): New define. (QNT_STACK): New define. (QNT_GENERATOR): New define. (QNT_DEFAULT_LIB): New define. (QNT_CORE_SYSINFO): New define. (QNT_CORE_INFO): New define. (QNT_CORE_STATUS): New define. (QNT_CORE_GREG): New define. (QNT_CORE_FPREG): New define. (QNT_LINK_MAP): New define.
2023-03-16BPF relocations review / refactoringCupertino Miranda1-14/+8
- Removed not needed relocations. - Renamed relocations to match llvm and linux kernel. Relocation changes: R_BPF_INSN_64 => R_BPF_64_64 R_BPF_INSN_DISP32 => R_BPF_64_32 R_BPF_DATA_32 => R_BPF_64_ABS32 R_BPF_DATA_64 => R_BPF_64_ABS64 ChangeLog: * bfd/bpf-reloc.def: Created file with BPF_HOWTO macro entries. * bfd/reloc.c: Removed non needed relocations. * bfd/bfd-in2.h: regenerated. * bfd/libbfd.h: regenerated. * bfd/elf64-bpf.c: Changed relocations. * include/elf/bpf.h: Adapted relocation values/names. * gas/config/tc-bpf.c: Changed relocation mapping.
2023-02-02bfd: use "stack trace" instead of "unwind" for SFrameIndu Bhagat1-1/+1
SFrame format is meant for generating stack traces only. bfd/ * elf-bfd.h: Replace the use of "unwind" with "stack trace". * elf-sframe.c: Likewise. * elf64-x86-64.c: Likewise. * elfxx-x86.c: Likewise. include/ * elf/common.h: Likewise.
2023-01-03Add new NT_ARM_ZA and NT_ARM_SSVE register set constants.Luis Machado1-0/+4
2023-01-01Update year range in copyright notice of binutils filesAlan Modra83-83/+83
The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
2022-11-15bfd: linker: merge .sframe sectionsIndu Bhagat2-0/+2
The linker merges all the input .sframe sections. When merging, the linker verifies that all the input .sframe sections have the same abi/arch. The linker uses libsframe library to perform key actions on the .sframe sections - decode, read, and create output data. This implies buildsystem changes to make and install libsframe before libbfd. The linker places the output .sframe section in a new segment of its own: PT_GNU_SFRAME. A new segment is not added, however, if the generated .sframe section is empty. When a section is discarded from the final link, the corresponding entries in the .sframe section for those functions are also deleted. The linker sorts the SFrame FDEs on start address by default and sets the SFRAME_F_FDE_SORTED flag in the .sframe section. This patch also adds support for generation of SFrame unwind information for the .plt* sections on x86_64. SFrame unwind info is generated for IBT enabled PLT, lazy/non-lazy PLT. The existing linker option --no-ld-generated-unwind-info has been adapted to include the control of whether .sframe unwind information will be generated for the linker generated sections like PLT. Changes to the linker script have been made as necessary. ChangeLog: * Makefile.def: Add install dependency on libsframe for libbfd. * Makefile.in: Regenerated. * bfd/Makefile.am: Add elf-sframe.c * bfd/Makefile.in: Regenerated. * bfd/bfd-in2.h (SEC_INFO_TYPE_SFRAME): Regenerated. * bfd/configure: Regenerate. * bfd/configure.ac: Add elf-sframe.lo. * bfd/elf-bfd.h (struct sframe_func_bfdinfo): New struct. (struct sframe_dec_info): Likewise. (struct sframe_enc_info): Likewise. (struct elf_link_hash_table): New member for encoded .sframe object. (struct output_elf_obj_tdata): New member. (elf_sframe): New access macro. (_bfd_elf_set_section_sframe): New declaration. * bfd/elf.c (get_segment_type): Handle new segment PT_GNU_SFRAME. (bfd_section_from_phdr): Likewise. (get_program_header_size): Likewise. (_bfd_elf_map_sections_to_segments): Likewise. * bfd/elf64-x86-64.c (elf_x86_64_link_setup_gnu_properties): Add contents to the .sframe sections or .plt* entries. * bfd/elflink.c (elf_section_ignore_discarded_relocs): Handle SEC_INFO_TYPE_SFRAME. (_bfd_elf_default_action_discarded): Handle .sframe section. (elf_link_input_bfd): Merge .sframe section. (bfd_elf_final_link): Write the output .sframe section. (bfd_elf_discard_info): Handle discarding .sframe section. * bfd/elfxx-x86.c (_bfd_x86_elf_size_dynamic_sections): Create .sframe section for .plt and .plt.sec. (_bfd_x86_elf_finish_dynamic_sections): Handle .sframe from .plt* sections. * bfd/elfxx-x86.h (PLT_SFRAME_FDE_START_OFFSET): New definition. (SFRAME_PLT0_MAX_NUM_FRES): Likewise. (SFRAME_PLTN_MAX_NUM_FRES): Likewise. (struct elf_x86_sframe_plt): New structure. (struct elf_x86_link_hash_table): New member. (struct elf_x86_init_table): New members for .sframe creation. * bfd/section.c: Add new definition SEC_INFO_TYPE_SFRAME. * binutils/readelf.c (get_segment_type): Handle new segment PT_GNU_SFRAME. * ld/ld.texi: Update documentation for --no-ld-generated-unwind-info. * ld/scripttempl/elf.sc: Support .sframe sections. * ld/Makefile.am (TESTSFRAMELIB): Use it. (check-DEJAGNU): Likewise. * ld/Makefile.in: Regenerated. * ld/configure.ac (TESTSFRAMELIB): Set to the .so or .a like TESTBFDLIB. * ld/configure: Regenerated. * bfd/elf-sframe.c: New file. include/ChangeLog: * elf/common.h (PT_GNU_SFRAME): New definition. * elf/internal.h (struct elf_segment_map): Handle new segment type PT_GNU_SFRAME. ld/testsuite/ChangeLog: * ld/testsuite/ld-bootstrap/bootstrap.exp: Add SFRAMELIB. * ld/testsuite/ld-aarch64/aarch64-elf.exp: Add new test sframe-simple-1. * ld/testsuite/ld-aarch64/sframe-bar.s: New file. * ld/testsuite/ld-aarch64/sframe-foo.s: Likewise. * ld/testsuite/ld-aarch64/sframe-simple-1.d: Likewise. * ld/testsuite/ld-sframe/sframe-empty.d: New test. * ld/testsuite/ld-sframe/sframe-empty.s: New file. * ld/testsuite/ld-sframe/sframe.exp: New testsuite. * ld/testsuite/ld-x86-64/sframe-bar.s: New file. * ld/testsuite/ld-x86-64/sframe-foo.s: Likewise. * ld/testsuite/ld-x86-64/sframe-simple-1.d: Likewise. * ld/testsuite/ld-x86-64/sframe-plt-1.d: Likewise. * ld/testsuite/ld-x86-64/sframe-simple-1.d: Likewise. * ld/testsuite/ld-x86-64/x86-64.exp: Add new tests - sframe-simple-1, sframe-plt-1. * ld/testsuite/lib/ld-lib.exp: Add new proc to check if assembler supports SFrame section. * ld/testsuite/ld-sframe/discard.d: New file. * ld/testsuite/ld-sframe/discard.ld: Likewise. * ld/testsuite/ld-sframe/discard.s: Likewise.
2022-09-30LoongArch: Update ELF e_flags handling according to specification.liuzhensong1-23/+21
Update handling of e_flags according to the documentation update [1] (discussions [2][3]). Object file bitness is now represented in the EI_CLASS byte. The e_flags field is now interpreted as follows: e_flags[2:0]: Base ABI modifier - 0x1: soft-float - 0x2: single-precision hard-float - 0x3: double-precision hard-float e_flags[7:6]: ELF object ABI version - 0x0: v0 - 0x1: v1 [1]: https://github.com/loongson/LoongArch-Documentation/blob/main/docs/LoongArch-ELF-ABI-EN.adoc#e_flags-identifies-abi-type-and-version [2]: https://github.com/loongson/LoongArch-Documentation/pull/61 [3]: https://github.com/loongson/LoongArch-Documentation/pull/47
2022-09-23Support AT_USRSTACKBASE and AT_USRSTACKLIM.John Baldwin1-0/+2
FreeBSD's kernel has recently added two new ELF auxiliary vector entries to describe the location of the user stack for the initial thread in a process. This change displays the proper name and description of these entries in 'info auxv'.
2022-09-21RISC-V: Implement Ztso extensionShihua1-0/+3
This patch support ZTSO extension. It will turn on the tso flag for elf_flags once we have enabled Ztso extension. This is intended to implement v0.1 of the proposed specification which can be found in Chapter 25 of, https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf. bfd\ChangeLog: * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Set TSO flag. * elfxx-riscv.c: Add Ztso's arch. binutils\ChangeLog: * readelf.c (get_machine_flags): Set TSO flag. gas\ChangeLog: * config/tc-riscv.c (riscv_set_tso): Ditto. (riscv_set_arch): Ditto. * testsuite/gas/riscv/ztso.d: New test. include\ChangeLog: * elf/riscv.h (EF_RISCV_TSO): Ditto.
2022-08-10RISC-V: Remove R_RISCV_GNU_VTINHERIT/R_RISCV_GNU_VTENTRYFangrui Song1-2/+0
They were legacy relocation types copied from other ports. The related -fvtable-gc was removed from GCC in 2003. The associated assembler directives (.vtable_inherit and .vtable_entry) have never been supported by the RISC-V port. Remove related ld code. Link: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/323
2022-08-02Add ELFCOMPRESS_ZSTD.Cary Coutant1-0/+2
include/elf/ * common.h: Add ELFCOMPRESS_ZSTD.
generated by cgit v1.1 at 2025-02-21 12:31:59 +0000