| Age | Commit message (Collapse) | Author | Files | Lines |
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Generally, glibc dynamic linker should have two ways to deal with ifunc
- one is to handle the IRELATIVE relocations for the non-preemtive ifunc
symbols, the other is to handle the R_RISCV_32/64 and R_RISCV_JUMP_SLOT
relocations with the STT_IFUNC preemtive symbols. No matter which method
is used, both of them should get the resolved ifunc symbols at runtime.
Therefore, linker needs to generate the correct dynamic relocations for
ifunc to make sure the the dynamic linker works well. For now, there are
thirteen relocations are supported for ifunc in GNU ld,
* R_RISCV_CALL and R_RISCV_CALL_PLT:
The RISC-V compiler won't generate R_RISCV_JAL directly to jump to an
ifunc. Besides, we disable the relaxations for the relocation referenced
to ifunc, so just handling the R_RISCV_CALL and R_RISCV_CALL_PLT should be
enough. Linker should generate a .plt entry and a .got.plt entry for it,
and also needs to insert a dynamic IRELATIVE in the .got.plt enrty, or
insert a R_RISCV_JUMP_SLOT when generating shared library.
* R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO12_I/S:
LA/LLA pattern with local fPIC ifunc symbol, or any non-PIC ifunc symbol.
The PC-relative relocation. The current linker will deal with them in
the same way as R_RISCV_CALL_PLT.
* R_RISCV_GOT_HI20 and R_RISCV_PCREL_LO12_I/S:
LA pattern with global PIC ifunc symbol. Linker should insert a dynamic
IRELATIVE in the .got entry, or insert a R_RISCV_32/64 when generating
shared library.
* R_RISCV_32 and R_RISCV_64:
Store the ifunc symbol into the data section. Linker should insert a
dynamic IRELATIVE in the data section, or insert a R_RISCV_32/64 when
generating shared library.
* R_RISCV_HI20 and R_RISCV_LO12_I/S:
The LUI + ADDI/LW/SW patterns. The absolute access relocation. The
medlow model without the -fPIC compiler option should generate them.
The ld ifunc testsuites "Build pr23169a" and "Build pr23169d" need the
relocations, they are in the ld/testsuite/ld-ifunc/, and need compiler
support.
However, we also made some optimizations with reference to x86,
* If GOT and PLT relocations refer to the same ifunc symbol when generating
pie, then they can actually share a .got entry without creating two entries
to store the same value and relocation.
* If GOT, PLT and DATA relocations refer to the same ifunc symbol when
generating position dependency executable, then linker will fill the address
of .plt entry into the corresponding .got entry and data section, without
insert any dynamic relocations for the GOT and DATA relocations.
For the ifunc testcases, there are three types of them,
1. ifunc-reloc-*: Only check the single type of relocation refers to
ifunc symbol.
* ifunc-reloc-call: R_RISCV_CALL and R_RISCV_CALL_PLT.
* ifunc-reloc-data: R_RISCV_32 and R_RISCV_64.
* ifunc-reloc-got: R_RISCV_GOT_HI20 and R_RISCV_PCREL_LO_I/S.
* ifunc-reloc-pcrel: R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO_I/S.
2. ifunc-[nonplt|plt]-*: If we don't have PLT relocs, then don't need to
create the PLT and it's .plt entries.
* ifunc-nonplt: Combine R_RISCV_GOT_HI20 and R_RISCV_32/64.
* ifunc-plt: Combine all ifunc relocations.
3. ifunc-seperate-*: If we link the ifunc caller and resolver into the
same module (link the objects), then the results are the same as the
ifunc-reloc-* and ifunc-[noplt|plt]-* testcases. Consider the cases that
the ifunc callers and resolver are in the different modules, that is, we
compile the ifunc resolver to the shared library first, and then link it
with the ifunc callers. The output of ifunc callers should be the same as
the normal STT_FUNC cases, and the shared ifunc resolver should define the
symbols as STT_IFUNC.
The R_RISCV_PCREL_HI20 reloc is special. It should be linked and resolved
locally, so if the ifunc resolver is defined in other modules (other shared
libraries), then the R_RISCV_PCREL_HI20 is unresolvable, and linker should
issue an unresolvable reloc error.
bfd/
* elfnn-riscv.c: Include "objalloc.h" since we need objalloc_alloc.
(riscv_elf_link_hash_table): Add loc_hash_table and loc_hash_memory
for local STT_GNU_IFUNC symbols.
(riscv_elf_got_plt_val): Removed.
(riscv_elf_local_htab_hash, riscv_elf_local_htab_eq): New functions.
Use to compare local hash entries.
(riscv_elf_get_local_sym_hash): New function. Find a hash entry for
local symbol, and create a new one if needed.
(riscv_elf_link_hash_table_free): New function. Destroy an riscv
elf linker hash table.
(riscv_elf_link_hash_table_create): Create hash table for local ifunc.
(riscv_elf_check_relocs): Create a fake global symbol to track the
local ifunc symbol. Add support to check and handle the relocations
reference to ifunc symbols.
(allocate_dynrelocs): Let allocate_ifunc_dynrelocs and
allocate_local_ifunc_dynrelocs to handle the ifunc symbols if they
are defined and referenced in a non-shared object.
(allocate_ifunc_dynrelocs): New function. Allocate space in .plt,
.got and associated reloc sections for ifunc dynamic relocs.
(allocate_local_ifunc_dynrelocs): Likewise, but for local ifunc
dynamic relocs.
(riscv_elf_relocate_section): Add support to handle the relocation
referenced to ifunc symbols.
(riscv_elf_size_dynamic_sections): Updated.
(riscv_elf_adjust_dynamic_symbol): Updated.
(riscv_elf_finish_dynamic_symbol): Finish up the ifunc handling,
including fill the PLT and GOT entries for ifunc symbols.
(riscv_elf_finish_local_dynamic_symbol): New function. Called by
riscv_elf_finish_dynamic_symbol to handle the local ifunc symbols.
(_bfd_riscv_relax_section): Don't do the relaxation for ifunc.
* elfxx-riscv.c: Add R_RISCV_IRELATIVE.
* configure.ac: Link elf-ifunc.lo to use the generic ifunc support.
* configure: Regenerated.
include/
* elf/riscv.h: Add R_RISCV_IRELATIVE to 58.
ld/
* emulparams/elf32lriscv-defs.sh: Add IREL_IN_PLT.
* testsuite/ld-ifunc/ifunc.exp: Enable ifunc tests for RISC-V.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp (run_dump_test_ifunc):
New dump test for ifunc. There are two arguments, 'target` and
`output`. The `target` is rv32 or rv64, and the `output` is used
to choose which output you want to test (exe, pie or .so).
* testsuite/ld-riscv-elf/ifunc-reloc-call-01.s: New testcase.
* testsuite/ld-riscv-elf/ifunc-reloc-call-01.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-01-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-01-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-01-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-02.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-02.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-02-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-02-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-call-02-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-data.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-data.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-data-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-data-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-data-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-got.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-got.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-got-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-got-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-got-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-pcrel.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-pcrel.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-pcrel-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-pcrel-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-reloc-pcrel-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-nonplt.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-nonplt.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-nonplt-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-nonplt-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-nonplt-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-01.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-01.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-01-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-01-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-01-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-02.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-02.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-02-exe.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-02-pic.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-plt-02-pie.rd: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-resolver.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-caller.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-exe.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-pic.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-pie.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-caller-pcrel.s: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-pcrel-pic.d: Likewise.
* testsuite/ld-riscv-elf/ifunc-seperate-pcrel-pie.d: Likewise.
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GCC 11 supports -march=x86-64-v[234] to enable x86 micro-architecture ISA
levels:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97250
Update GNU_PROPERTY_X86_ISA_1_XXX macros:
https://gitlab.com/x86-psABIs/x86-64-ABI/-/merge_requests/13
in x86 ELF binaries to indicate that micro-architecture ISA levels
required to execute the binary:
#define GNU_PROPERTY_X86_ISA_1_NEEDED (GNU_PROPERTY_X86_UINT32_OR_LO + 2)
#define GNU_PROPERTY_X86_ISA_1_USED (GNU_PROPERTY_X86_UINT32_OR_AND_LO + 2)
#define GNU_PROPERTY_X86_ISA_1_V2 (1U << 0)
#define GNU_PROPERTY_X86_ISA_1_V3 (1U << 1)
#define GNU_PROPERTY_X86_ISA_1_V4 (1U << 2)
The previous GNU_PROPERTY_X86_ISA_1_XXX macros are deprecated and renamed
to GNU_PROPERTY_X86_COMPAT_2_ISA_1_XXX.
In addition to EM_X86_64, GNU_PROPERTY_X86_ISA_1_V[234] marker can be used
by ld.so to detect the x86-64-v4 shared library placed in an x86-64-v2
directory by mistake on an x86-64-v2 machine to avoid crashes on x86-64-v4
instructions.
Add -z x86-64-v[234] linker command line option to mark x86-64-v[234]
ISA level as needed.
Also add
#define GNU_PROPERTY_X86_FEATURE_2_MASK (1U << 11)
for mask registers.
bfd/
PR gas/26703
* elf-linker-x86.h (elf_linker_x86_params): Add isa_level.
* elfxx-x86.c (_bfd_x86_elf_merge_gnu_properties): Merge
GNU_PROPERTY_X86_ISA_1_V[234].
(_bfd_x86_elf_link_setup_gnu_properties): Generate
GNU_PROPERTY_X86_ISA_1_V[234] for -z x86-64-v[234].
binutils/
PR gas/26703
* readelf.c (decode_x86_compat_2_isa): New function.
(decode_x86_isa): Updated for new X86_ISA_1_XXX bits.
(decode_x86_feature_1): Handle GNU_PROPERTY_X86_FEATURE_2_MASK.
(print_gnu_property_note): Handle X86_COMPAT_2_ISA_1_USED,
and X86_COMPAT_2_ISA_1_NEEDED.
* testsuite/binutils-all/i386/pr21231b.s: Updated to the current
GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_ISA_1_NEEDED
values.
* testsuite/binutils-all/x86-64/pr21231b.s: Likewise.
* testsuite/binutils-all/x86-64/pr23494a.s: Likewise.
* testsuite/binutils-all/x86-64/pr23494b.s: Likewise.
* testsuite/binutils-all/x86-64/pr23494c.s: Likewise.
* testsuite/binutils-all/i386/empty.d: Updated.
* testsuite/binutils-all/i386/ibt.d: Likewise.
* testsuite/binutils-all/i386/pr21231a.d: Likewise.
* testsuite/binutils-all/i386/pr21231b.d: Likewise.
* testsuite/binutils-all/i386/shstk.d: Likewise.
* testsuite/binutils-all/x86-64/empty-x32.d: Likewise.
* testsuite/binutils-all/x86-64/empty.d: Likewise.
* testsuite/binutils-all/x86-64/ibt-x32.d: Likewise.
* testsuite/binutils-all/x86-64/ibt.d: Likewise.
* testsuite/binutils-all/x86-64/pr21231a.d: Likewise.
* testsuite/binutils-all/x86-64/pr21231b.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494a-x32.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494a.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494c-x32.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494c.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494d-x32.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494d.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494e-x32.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494e.d: Likewise.
* testsuite/binutils-all/x86-64/shstk-x32.d: Likewise.
* testsuite/binutils-all/x86-64/shstk.d: Likewise.
gas/
PR gas/26703
* config/tc-i386.c (xstate): Add xstate_mask.
(md_assemble): Check i.types[j], instead of i.tm.operand_types[j],
for xstate. Set xstate_mask, instead of xstate_zmm, for RegMask.
(output_insn): Update for GNU_PROPERTY_X86_ISA_1_V[234]. Update
xstate for mask register and VSIB.
* testsuite/gas/i386/i386.exp: Run more GNU_PROPERTY tests.
* testsuite/gas/i386/property-1.s: Updated to the current
GNU_PROPERTY_X86_ISA_1_USED value.
* testsuite/gas/i386/property-2.s: Only keep cmove.
* testsuite/gas/i386/property-3.s: Changed to addsubpd.
* testsuite/gas/i386/property-1.d: Updated.
* testsuite/gas/i386/property-2.d: Likewise.
* testsuite/gas/i386/property-3.d: Likewise.
* testsuite/gas/i386/property-4.d: Likewise.
* testsuite/gas/i386/property-5.d: Likewise.
* testsuite/gas/i386/property-6.d: Likewise.
* testsuite/gas/i386/x86-64-property-1.d: Likewise.
* testsuite/gas/i386/x86-64-property-2.d: Likewise.
* testsuite/gas/i386/x86-64-property-3.d: Likewise.
* testsuite/gas/i386/x86-64-property-4.d: Likewise.
* testsuite/gas/i386/x86-64-property-5.d: Likewise.
* testsuite/gas/i386/x86-64-property-6.d: Likewise.
* testsuite/gas/i386/x86-64-property-7.d: Likewise.
* testsuite/gas/i386/x86-64-property-8.d: Likewise.
* testsuite/gas/i386/x86-64-property-9.d: Likewise.
* testsuite/gas/i386/property-11.d: New file.
* testsuite/gas/i386/property-11.s: Likewise.
* testsuite/gas/i386/property-12.d: Likewise.
* testsuite/gas/i386/property-12.s: Likewise.
* testsuite/gas/i386/property-13.d: Likewise.
* testsuite/gas/i386/property-13.s: Likewise.
* testsuite/gas/i386/x86-64-property-11.d: Likewise.
* testsuite/gas/i386/x86-64-property-12.d: Likewise.
* testsuite/gas/i386/x86-64-property-13.d: Likewise.
* testsuite/gas/i386/x86-64-property-14.d: Likewise.
* testsuite/gas/i386/x86-64-property-14.s: Likewise.
include/
PR gas/26703
* elf/common.h (GNU_PROPERTY_X86_ISA_1_USED): Renamed to ...
(GNU_PROPERTY_X86_COMPAT_2_ISA_1_USED): This.
(GNU_PROPERTY_X86_ISA_1_NEEDED): Renamed to ...
(GNU_PROPERTY_X86_COMPAT_2_ISA_1_NEEDED): This.
(GNU_PROPERTY_X86_ISA_1_XXX): Renamed to ...
(GNU_PROPERTY_X86_COMPAT_2_ISA_1_XXX): This.
(GNU_PROPERTY_X86_ISA_1_NEEDED): New.
(GNU_PROPERTY_X86_ISA_1_USED): Likewise.
(GNU_PROPERTY_X86_ISA_1_V2): Likewise.
(GNU_PROPERTY_X86_ISA_1_V3): Likewise.
(GNU_PROPERTY_X86_ISA_1_V4): Likewise.
(GNU_PROPERTY_X86_FEATURE_2_MASK): Likewise.
ld/
PR gas/26703
* NEWS: Mention -z x86-64-v[234].
* ld.texi: Document -z x86-64-v[234].
* emulparams/elf32_x86_64.sh: Use x86-64-level.sh.
* emulparams/elf_i386.sh: Likewise.
* emulparams/elf_x86_64.sh: Likewise.
* emulparams/x86-64-level.sh: New file.
* testsuite/ld-elf/x86-feature-1a.rd: Update.
* testsuite/ld-elf/x86-feature-1b.rd: Likewise.
* testsuite/ld-elf/x86-feature-1c.rd: Likewise.
* testsuite/ld-elf/x86-feature-1d.rd: Likewise.
* testsuite/ld-elf/x86-feature-1e.rd: Likewise.
* testsuite/ld-i386/pr23372c.d: Likewise.
* testsuite/ld-i386/pr23486c.d: Likewise.
* testsuite/ld-i386/pr23486d.d: Likewise.
* testsuite/ld-i386/pr24322a.d: Likewise.
* testsuite/ld-i386/pr24322b.d: Likewise.
* testsuite/ld-i386/property-1a.r: Likewise.
* testsuite/ld-i386/property-2a.r: Likewise.
* testsuite/ld-i386/property-3.r: Likewise.
* testsuite/ld-i386/property-3a.r: Likewise.
* testsuite/ld-i386/property-4.r: Likewise.
* testsuite/ld-i386/property-4a.r: Likewise.
* testsuite/ld-i386/property-5.r: Likewise.
* testsuite/ld-i386/property-5a.r: Likewise.
* testsuite/ld-i386/property-7a.r: Likewise.
* testsuite/ld-i386/property-x86-3.d: Likewise.
* testsuite/ld-i386/property-x86-4a.d: Likewise.
* testsuite/ld-i386/property-x86-5.d: Likewise.
* testsuite/ld-i386/property-x86-cet1.d: Likewise.
* testsuite/ld-i386/property-x86-cet2a.d: Likewise.
* testsuite/ld-i386/property-x86-cet5a.d: Likewise.
* testsuite/ld-i386/property-x86-cet5b.d: Likewise.
* testsuite/ld-i386/property-x86-ibt1a.d: Likewise.
* testsuite/ld-i386/property-x86-ibt1b.d: Likewise.
* testsuite/ld-i386/property-x86-ibt2.d: Likewise.
* testsuite/ld-i386/property-x86-ibt3a.d: Likewise.
* testsuite/ld-i386/property-x86-ibt3b.d: Likewise.
* testsuite/ld-i386/property-x86-ibt4.d: Likewise.
* testsuite/ld-i386/property-x86-ibt5.d: Likewise.
* testsuite/ld-i386/property-x86-shstk1a.d: Likewise.
* testsuite/ld-i386/property-x86-shstk1b.d: Likewise.
* testsuite/ld-i386/property-x86-shstk2.d: Likewise.
* testsuite/ld-i386/property-x86-shstk3a.d: Likewise.
* testsuite/ld-i386/property-x86-shstk3b.d: Likewise.
* testsuite/ld-i386/property-x86-shstk4.d: Likewise.
* testsuite/ld-i386/property-x86-shstk5.d: Likewise.
* testsuite/ld-x86-64/pr23372c-x32.d: Likewise.
* testsuite/ld-x86-64/pr23372c.d: Likewise.
* testsuite/ld-x86-64/pr23486c.d: Likewise.
* testsuite/ld-x86-64/pr23486d-x32.d: Likewise.
* testsuite/ld-x86-64/pr23486d.d: Likewise.
* testsuite/ld-x86-64/pr24322a-x32.d: Likewise.
* testsuite/ld-x86-64/pr24322a.d: Likewise.
* testsuite/ld-x86-64/pr24322b-x32.d: Likewise.
* testsuite/ld-x86-64/pr24322b.d: Likewise.
* testsuite/ld-x86-64/pr24458a-x32.d: Likewise.
* testsuite/ld-x86-64/pr24458a.d: Likewise.
* testsuite/ld-x86-64/pr24458b-x32.d: Likewise.
* testsuite/ld-x86-64/pr24458b.d: Likewise.
* testsuite/ld-x86-64/pr24458c-x32.d: Likewise.
* testsuite/ld-x86-64/pr24458c.d: Likewise.
* testsuite/ld-x86-64/property-1a.r: Likewise.
* testsuite/ld-x86-64/property-2a.r: Likewise.
* testsuite/ld-x86-64/property-3.r: Likewise.
* testsuite/ld-x86-64/property-3a.r: Likewise.
* testsuite/ld-x86-64/property-4.r: Likewise.
* testsuite/ld-x86-64/property-4a.r: Likewise.
* testsuite/ld-x86-64/property-5.r: Likewise.
* testsuite/ld-x86-64/property-5a.r: Likewise.
* testsuite/ld-x86-64/property-7a.r: Likewise.
* testsuite/ld-x86-64/property-x86-3-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-3.d: Likewise.
* testsuite/ld-x86-64/property-x86-4a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-4a.d: Likewise.
* testsuite/ld-x86-64/property-x86-5-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-5.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet1-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet1.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet2a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet2a.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet5a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet5a.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet5b-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet5b.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt1a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt1a.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt1b-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt1b.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt2-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt2.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt3a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt3a.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt3b-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt3b.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt4-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt4.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt5-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt5.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk1a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk1a.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk1b-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk1b.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk2-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk2.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk3a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk3a.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk3b-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk3b.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk4-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk4.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk5-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk5.d: Likewise.
* testsuite/ld-i386/i386.exp: Run property-x86-6,
property-x86-isa1, property-x86-isa2 and property-x86-isa3.
* testsuite/ld-i386/property-x86-1.S: Updated to the current
GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_ISA_1_NEEDED
values.
* testsuite/ld-i386/property-x86-2.S: Likewise.
* testsuite/ld-i386/property-x86-3.s: Likewise.
* testsuite/ld-x86-64/pr23372d.s: Likewise.
* testsuite/ld-x86-64/pr23372e.s: Likewise.
* testsuite/ld-x86-64/pr23372f.s: Likewise.
* testsuite/ld-x86-64/pr23486c.s: Likewise.
* testsuite/ld-x86-64/pr23486d.s: Likewise.
* testsuite/ld-x86-64/property-x86-1.S: Likewise.
* testsuite/ld-x86-64/property-x86-2.S: Likewise.
* testsuite/ld-x86-64/property-x86-3.s: Likewise.
* testsuite/ld-x86-64/property-x86-5a.s: Likewise.
* testsuite/ld-x86-64/property-x86-5b.s: Likewise.
* testsuite/ld-i386/property-x86-6.d: New file.
* testsuite/ld-i386/property-x86-isa1.d: Likewise.
* testsuite/ld-i386/property-x86-isa2.d: Likewise.
* testsuite/ld-i386/property-x86-isa3.d: Likewise.
* testsuite/ld-x86-64/property-x86-6-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-6.d: Likewise.
* testsuite/ld-x86-64/property-x86-6.s: Likewise.
* testsuite/ld-x86-64/property-x86-isa1-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-isa1.d: Likewise.
* testsuite/ld-x86-64/property-x86-isa1.s: Likewise.
* testsuite/ld-x86-64/property-x86-isa2-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-isa2.d: Likewise.
* testsuite/ld-x86-64/property-x86-isa3-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-isa3.d: Likewise.
* testsuite/ld-x86-64/simple.s: Likewise.
* ld/testsuite/ld-x86-64/x86-64.exp: Run property-x86-6,
property-x86-6-x32, property-x86-isa1, property-x86-isa1-x32,
property-x86-isa2, property-x86-isa2-x32, property-x86-isa3-x32
and property-x86-isa3.
|
|
Define NT_X86_CET which is the proposed note for x86 CET state to support
Intel CET in Linux kernel. Double check it after Intel CET patches have
been merged into Linux kernel.
binutils/
* readelf.c (get_note_type): Support NT_X86_CET.
include/
* elf/common.h (NT_X86_CET): New.
|
|
Link-time relaxations of branches are common for MSP430, given that GCC
can generate pessimal branch instructions, and the
-mcode-region=either/-mdata-region=either options to shuffle sections
can further change the type of branch instruction required.
These relaxations can result in invalid code when .uleb128
directives, used in the .gcc_except_table section, are used to calculate
the distance between two labels. A value for the .uleb128 directive is
calculated at assembly-time, and can't be updated at link-time, even if
relaxation causes the distance between the labels to change.
This patch adds relocations for subtract expressions in .uleb128
directives, to allow the linker to re-calculate the value of these
expressions after relaxation has been performed.
bfd/ChangeLog:
* bfd-in2.h (bfd_reloc_code_real): Add
BFD_RELOC_MSP430_{SET,SUB}_ULEB128.
* elf32-msp430.c (msp430_elf_ignore_reloc): New.
(elf_msp430_howto_table): Add R_MSP430{,X}_GNU_{SET,SUB}_ULEB128.
(msp430_reloc_map): Add R_MSP430_GNU_{SET,SUB}_ULEB128.
(msp430x_reloc_map): Add R_MSP430X_GNU_{SET,SUB}_ULEB128.
(write_uleb128): New.
(msp430_final_link_relocate): Handle R_MSP430{,X}_GNU_{SET,SUB}_ULEB128.
* libbfd.c (_bfd_write_unsigned_leb128): New.
* libbfd.h (_bfd_write_unsigned_leb128): New prototype.
Add BFD_RELOC_MSP430_{SET,SUB}_ULEB128.
* reloc.c: Document BFD_RELOC_MSP430_{SET,SUB}_ULEB128.
binutils/ChangeLog:
* readelf.c (target_specific_reloc_handling): Handle
R_MSP430{,X}_GNU_{SET,SUB}_ULEB128.
gas/ChangeLog:
* config/tc-msp430.c (msp430_insert_uleb128_fixes): New.
(msp430_md_end): Call msp430_insert_uleb128_fixes.
include/ChangeLog:
* elf/msp430.h (elf_msp430_reloc_type): Add
R_MSP430_GNU_{SET,SUB}_ULEB128.
(elf_msp430x_reloc_type): Add R_MSP430X_GNU_{SET,SUB}_ULEB128.
ld/ChangeLog:
* testsuite/ld-msp430-elf/msp430-elf.exp: Run new tests.
* testsuite/ld-msp430-elf/uleb128.s: New test.
* testsuite/ld-msp430-elf/uleb128_430.d: New test.
* testsuite/ld-msp430-elf/uleb128_430x.d: New test.
|
|
bfd
* elf32-csky.c (csky_archs): Fix arch names.
(csky_find_arch_with_name): New.
(elf32_csky_merge_attributes): New.
(csky_elf_merge_private_bfd_data): Add process of merge
attribute section.
(elf32_csky_obj_attrs_arg_type): New.
(elf32_csky_obj_attrs_handle_unknown): New.
(elf_backend_obj_attrs_vendor): Define.
(elf_backend_obj_attrs_section): Define.
(elf_backend_obj_attrs_arg_type): Define.
(elf_backend_obj_attrs_section_type): Define.
binutils/
* readelf.c (get_csky_section_type_name): New.
(get_section_type_name): Add handler for CSKY.
(display_csky_attribute): New.
(process_arch_specific): Add handler for CSKY.
* testsuite/binutils-all/strip-3.d: Remove .csky.attributes
section.
elfcpp/
* elfcpp.h (enum SHT): New enum SHT_CSKY_ATTRIBUTES.
gas/
* gas/config/tc-csky.c (md_begin): Set attributes.
(isa_flag): Change type to unsigned 64 bits.
(struct csky_cpu_info): Likewise.
(struct csky_macro_info): Likewise.
(set_csky_attribute): New.
* testsuite/gas/csky/802j.d: Ignore .csky.attributes section.
* testsuite/gas/csky/all.d: Likewise.
* testsuite/gas/csky/bsr1.d: Likewise.
* testsuite/gas/csky/csky_vdsp.d: Likewise.
* testsuite/gas/csky/cskyv2_all.d: Likewise.
* testsuite/gas/csky/cskyv2_ck803r2.d: Likewise.
* testsuite/gas/csky/cskyv2_ck860.d: Likewise.
* testsuite/gas/csky/cskyv2_dsp.d: Likewise.
* testsuite/gas/csky/cskyv2_elrw.d: Likewise.
* testsuite/gas/csky/cskyv2_float.d: Likewise.
* testsuite/gas/csky/enhance_dsp.d: Likewise.
* testsuite/gas/csky/java.d: Likewise.
* testsuite/gas/csky/v1_float.d: Likewise.
* testsuite/gas/csky/v2_float_part1.d: Likewise.
* testsuite/gas/csky/v2_float_part2.d: Likewise.
* testsuite/gas/csky/v2_tls_gd.d: Likewise.
* testsuite/gas/csky/v2_tls_ie.d: Likewise.
* testsuite/gas/csky/v2_tls_ld.d: Likewise.
* testsuite/gas/csky/v2_tls_le.d: Likewise.
* testsuite/gas/elf/elf.exp: Add handler for CSKY.
* testsuite/gas/elf/section2.e-csky: New.
include/
* elf/csky.h (SHT_CSKY_ATTRIBUTES): Define.
(Tag_CSKY_ARCH_NAME): New enum constant.
(Tag_CSKY_CPU_NAME): Likewise.
(Tag_CSKY_ISA_FLAGS): Likewise.
(Tag_CSKY_DSP_VERSION): Likewise.
(Tag_CSKY_VDSP_VERSION): Likewise.
(Tag_CSKY_FPU_VERSION): Likewise.
(Tag_CSKY_FPU_ABI): Likewise.
(Tag_CSKY_FPU_ROUNDING): Likewise.
(Tag_CSKY_FPU_DENORMAL): Likewise.
(Tag_CSKY_FPU_Exception): Likewise.
(Tag_CSKY_FPU_NUMBER_MODULE): Likewise.
(Tag_CSKY_FPU_HARDFP): Likewise.
(Tag_CSKY_MAX): Likewise.
(VAL_CSKY_DSP_VERSION_EXTENSION): Likewise.
(VAL_CSKY_DSP_VERSION_2): Likewise.
(VAL_CSKY_VDSP_VERSION_1): Likewise.
(VAL_CSKY_VDSP_VERSION_2): Likewise.
(VAL_CSKY_FPU_ABI_SOFT): Likewise.
(VAL_CSKY_FPU_ABI_SOFTFP): Likewise.
(VAL_CSKY_FPU_ABI_HARD): Likewise.
(VAL_CSKY_FPU_HARDFP_HALF): Likewise.
(VAL_CSKY_FPU_HARDFP_SINGLE): Likewise.
(VAL_CSKY_FPU_HARDFP_DOUBLE): Likewise.
* opcode/csky.h (CSKY_ISA_VDSP_V2): Define.
CSKYV1_ISA_E1: Change to long constant type.
CSKYV2_ISA_E1: Likewise.
CSKYV2_ISA_1E2: Likewise.
CSKYV2_ISA_2E3: Likewise.
CSKYV2_ISA_3E7: Likewise.
CSKYV2_ISA_7E10: Likewise.
CSKYV2_ISA_3E3R1: Likewise.
CSKYV2_ISA_3E3R2: Likewise.
CSKYV2_ISA_10E60: Likewise.
CSKY_ISA_TRUST: Likewise.
CSKY_ISA_CACHE: Likewise.
CSKY_ISA_NVIC: Likewise.
CSKY_ISA_CP: Likewise.
CSKY_ISA_MP: Likewise.
CSKY_ISA_MP_1E2: Likewise.
CSKY_ISA_JAVA: Likewise.
CSKY_ISA_MAC: Likewise.
CSKY_ISA_MAC_DSP: Likewise.
CSKY_ISA_DSP: Likewise.
CSKY_ISA_DSP_1E2: Likewise.
CSKY_ISA_DSP_ENHANCE: Likewise.
CSKY_ISA_FLOAT_E1: Likewise.
CSKY_ISA_FLOAT_1E2: Likewise.
CSKY_ISA_FLOAT_1E3: Likewise.
CSKY_ISA_FLOAT_3E4: Likewise.
CSKY_ISA_VDSP: Likewise.
ld/
* emulparams/cskyelf.sh: Support attribute section.
* testsuite/ld-csky/tls-le-v1.d: Match .csky.attributes section.
* ld/testsuite/ld-csky/tls-le.d: Likewise.
* testsuite/ld-elf/non-contiguous.ld: Ignore .csky.attributes
section.
opcodes/
* csky-dis.c (CSKY_DEFAULT_ISA): Define.
(csky_dis_info): Add member isa.
(csky_find_inst_info): Skip instructions that do not belong to
current CPU.
(csky_get_disassembler): Get infomation from attribute section.
(print_insn_csky): Set defualt ISA flag.
* csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
* csky-opc.h (struct csky_opcode): Change isa_flag16 and
isa_flag32'type to unsigned 64 bits.
|
|
PR 26405
binutils* readelf.c (get_segment_type): Handle OpenBSD segment types.
include * elf/common.h (PT_OPENBSD_BOOTDATA): Define.
(PT_OPENBSD_RANDOMIZE): Define.
(PT_OPENBSD_WXNEEDED): Define.
|
|
Happens when poking symbol index -2 into r_info. (The index is
updated before writing out to file.)
PR 26458
* elf/common.h (ELF32_R_INFO): Cast symbol index to unsigned.
|
|
Support GNU_PROPERTY_X86_FEATURE_2_TMM in
https://gitlab.com/x86-psABIs/x86-64-ABI/-/merge_requests/1
#define GNU_PROPERTY_X86_FEATURE_2_TMM (1U << 10)
binutils/
* readelf.c (decode_x86_feature_2): Handle
GNU_PROPERTY_X86_FEATURE_2_TMM.
gas/
* config/tc-i386.c (output_insn): Check i.xstate to set
GNU_PROPERTY_X86_FEATURE_2_TMM.
* testsuite/gas/i386/i386.exp: Run x86-64-property-7,
x86-64-property-8 and x86-64-property-9.
* testsuite/gas/i386/x86-64-property-7.d: New file.
* testsuite/gas/i386/x86-64-property-7.s: Likewise.
* testsuite/gas/i386/x86-64-property-8.d: Likewise.
* testsuite/gas/i386/x86-64-property-8.s: Likewise.
* testsuite/gas/i386/x86-64-property-9.d: Likewise.
* testsuite/gas/i386/x86-64-property-9.s: Likewise.
include/
* elf/common.h (GNU_PROPERTY_X86_FEATURE_2_TMM): New.
|
|
FreeBSD's kernel recently added several ELF auxiliary vector entries
to describe the arguments passed to new executable images during
exec(). The AT_FREEBSD_ARGC and AT_FREEBSD_ARGV entries give the
length and address of the process argument array. AT_FREEBSD_ENVC and
AT_FREEBSD_ENVV entries give the length and address of the initial
process environment. AT_FREEBSD_PS_STRINGS gives the address of the
'struct ps_strings' object.
include/ChangeLog:
* elf/common.h (AT_FREEBSD_ARGC, AT_FREEBSD_ARGV, AT_FREEBSD_ENVC)
(AT_FREEBSD_ENVV, AT_FREEBSD_PS_STRINGS): Define.
gdb/ChangeLog:
* fbsd-tdep.c (fbsd_print_auxv_entry): Handle AT_FREEBSD_ARGC,
AT_FREEBSD_ARGV, AT_FREEBSD_ENVC, AT_FREEBSD_ENVV,
AT_FREEBSD_PS_STRINGS.
|
|
binutils isn't c99 (yet). This replaces or removes some C++ style
comments.
bfd/
* arc-got.h: Use C style comments.
* coff-z80.c: Likewise.
* elf32-csky.c: Likewise.
* peXXigen.c: Likewise.
* elf32-m32c.c (m32c_elf_relax_delete_bytes): Remove commented out
code.
binutils/
* dwarf.c: Use C style comments.
* resrc.c: Likewise.
gas/
* config/tc-s12z.c: Use C style comments.
* config/tc-z80.c: Likewise.
* config/tc-xtensa.c (emit_ld_r_n): Remove commented out code.
include/
* coff/internal.h: Use C style comments.
* coff/pe.h: Likewise.
* elf/ppc64.h: Likewise.
opcodes/
* arm-dis.c: Use C style comments.
* cr16-opc.c: Likewise.
* ft32-dis.c: Likewise.
* moxie-opc.c: Likewise.
* tic54x-dis.c: Likewise.
* s12z-opc.c: Remove useless comment.
* xgate-dis.c: Likewise.
|
|
This patch adds GNU attribute support to m68k and utilises it to tag the
floating-point calling convention used (hard-float or soft-float). It enables
the linker to ensure linked objects use a consistent floating-point ABI and
allows tools like GDB to infer the ABI used from the ELF file. It is based on
similar work done for PowerPC.
bfd/
* elf32-m68k.c (m68k_elf_merge_obj_attributes): New function.
(elf32_m68k_merge_private_bfd_data): Merge GNU attributes.
binutils/
* readelf.c (display_m68k_gnu_attribute): New function.
(process_arch_specific): Call display_m68k_gnu_attribute for EM_68K.
gas/
* config/tc-m68k.c (m68k_elf_gnu_attribute): New function.
(md_pseudo_table): Handle "gnu_attribute".
* doc/as.texi: Document GNU attribute for M68K.
include/
* elf/m68k.h: Add enum for GNU object attribute with floating point
tag name and values.
ld/
* testsuite/ld-m68k/attr-gnu-4-0.s: New file.
* testsuite/ld-m68k/attr-gnu-4-1.s: Likewise.
* testsuite/ld-m68k/attr-gnu-4-2.s: Likewise.
* testsuite/ld-m68k/attr-gnu-4-00.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-01.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-02.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-10.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-11.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-12.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-20.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-21.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-22.d: Likewise.
* testsuite/ld-m68k/m68k.exp: Run the new tests.
|
|
2020-06-15 Max Filippov <jcmvbkbc@gmail.com>
bfd/
* elf32-xtensa.c (XSHAL_ABI, XTHAL_ABI_UNDEFINED)
(XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New macros.
(elf32xtensa_abi): New global variable.
(xtensa_abi_choice): New function.
(elf_xtensa_create_plt_entry): Use xtensa_abi_choice instead of
XSHAL_ABI to select PLT code.
gas/
* config/tc-xtensa.c (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New
macros.
(elf32xtensa_abi): New declaration.
(option_abi_windowed, option_abi_call0): New enum constants.
(md_longopts): Add entries for --abi-windowed and --abi-call0.
(md_parse_option): Add handlers for --abi-windowed and
--abi-call0.
(xtensa_add_config_info): Use xtensa_abi_choice instead of
XSHAL_ABI to format ABI tag.
* doc/as.texi (Target Xtensa options): Add --abi-windowed and
--abi-call0 to the list of options.
* doc/c-xtensa.texi: Add description for options --abi-windowed
and --abi-call0.
* testsuite/gas/xtensa/abi-call0.d: New test definition.
* testsuite/gas/xtensa/abi-windowed.d: New test definition.
* testsuite/gas/xtensa/abi.s: New test source.
include/
* elf/xtensa.h (xtensa_abi_choice): New declaration.
ld/
* emultempl/xtensaelf.em (XSHAL_ABI): Remove macro definition.
(XTHAL_ABI_UNDEFINED, XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New
macros.
(elf32xtensa_abi): New declaration.
(xt_config_info_unpack_and_check): Set elf32xtensa_abi if it is
undefined. Use xtensa_abi_choice instead of XSHAL_ABI to test
ABI tag consistency.
(xtensa_add_config_info): Use xtensa_abi_choice instead of
XSHAL_ABI to format ABI tag.
(PARSE_AND_LIST_PROLOGUE): Define OPTION_ABI_WINDOWED,
OPTION_ABI_CALL0 and declare elf32xtensa_abi.
(PARSE_AND_LIST_LONGOPTS): Add entries for --abi-windowed and
--abi-call0.
(PARSE_AND_LIST_OPTIONS): Add help text for --abi-windowed and
--abi-call0.
(PARSE_AND_LIST_ARGS_CASES): Add handlers for --abi-windowed and
--abi-call0.
* ld.texi: Add description for options --abi-windowed and
--abi-call0.
|
|
DT_MIPS_OPTIONS is not a regular array as assumed by readelf. This
patch corrects that assumption, and to do so easily, makes various
internal (host byte order) structs the same size as external (target
byte order) structs.
include/
* elf/mips.h (Elf32_RegInfo): Use fixed width integer types.
(Elf64_Internal_RegInfo, Elf_Internal_Options): Likewise.
binutils/
* readelf.c (process_mips_specific): Assert size of internal
types match size of external types, and simplify allocation of
internal buffer. Catch possible integer overflow when sanity
checking option size. Don't assume options are a regular array.
Sanity check reginfo option against option size. Use PRI macros
when printing.
|
|
These relocations should have had REL in their names, to reflect the
fact that they are pc-relative. Fix that now by adding _PCREL.
I've added some back-compatibility code to support anyone using
.reloc with the old relocations.
include/
* elf/ppc64.h (elf_ppc64_reloc_type): Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
bfd/
* reloc.c: Rename
BFD_RELOC_PPC64_GOT_TLSGD34 to BFD_RELOC_PPC64_GOT_TLSGD_PCREL34,
BFD_RELOC_PPC64_GOT_TLSLD34 to BFD_RELOC_PPC64_GOT_TLSLD_PCREL34,
BFD_RELOC_PPC64_GOT_TPREL34 to BFD_RELOC_PPC64_GOT_TPREL_PCREL34,
BFD_RELOC_PPC64_GOT_DTPREL34 to BFD_RELOC_PPC64_GOT_DTPREL_PCREL34.
* elf64-ppc.c: Update throughout for reloc renaming.
(ppc64_elf_reloc_name_lookup): Handle old reloc names.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c: Update throughout for reloc renaming.
elfcpp/
* powerpc.h: Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
gold/
* powerpc.cc: Update throughout for reloc renaming.
|
|
include/elf/common.h has
#define ET_EXEC 2 /* Executable file */
#define ET_DYN 3 /* Shared object file */
These predate PIE:
https://groups.google.com/forum/#!topic/generic-abi/mBKlSNldFW4
Updated comments to
#define ET_EXEC 2 /* Position-dependent executable file */
#define ET_DYN 3 /* Position-independent executable or
shared object file */
* elf/common.h: Update comments for ET_EXEC and ET_DYN.
|
|
Now that ISA3.1 is out we can finish with the powerxx silliness.
bfd/
* elf64-ppc.c: Rename powerxx to power10 throughout.
gas/
* config/tc-ppc.c (md_assemble): Update for PPC_OPCODE_POWER10
renaming.
* testsuite/gas/ppc/prefix-align.d: Use -mpower10/-Mpower10 in
place of -mfuture/-Mfuture.
* testsuite/gas/ppc/prefix-pcrel.d: Likewise.
* testsuite/gas/ppc/prefix-reloc.d: Likewise.
gold/
* powerpc.cc: Rename powerxx to power10 throughout.
include/
* elf/ppc64.h: Update comment.
* opcode/ppc.h (PPC_OPCODE_POWER10): Rename from PPC_OPCODE_POWERXX.
ld/
* testsuite/ld-powerpc/callstub-1.d: Use -mpower10/-Mpower10 in
place of -mfuture/-Mfuture.
* testsuite/ld-powerpc/notoc2.d: Likewise.
* testsuite/ld-powerpc/powerpc.exp: Likewise.
* testsuite/ld-powerpc/tlsgd.d: Likewise.
* testsuite/ld-powerpc/tlsie.d: Likewise.
* testsuite/ld-powerpc/tlsld.d: Likewise.
opcodes/
* ppc-dis.c (ppc_opts): Add "power10" entry.
(print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
* ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
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When a coredump is generated, there are a few registers in
ARC HS that are put under a special section, namely ".reg-v2".
It is for backward compatibility reasons with older tools that
we have decided not to extend the generic ".reg" section.
This patch makes it possible to display the information better
regarding that section. Compare the output of "readelf" without
and with these changes:
$ readelf -n core # without the patch
...
LINUX 0x0000000c Unknown note type: (0x00000600)
description data: 78 08 00 00 2f 6c 64 2d 75 43 6c 69
$ readelf -n core # with the patch
...
LINUX 0x0000000c NT_ARC_V2 (ARC HS accumulator/extra registers)
description data: 78 08 00 00 2f 6c 64 2d 75 43 6c 69
In another commit (soon to be submitted), GDB will makes use of these
changes to parse the extra section and its registers.
bfd/ChangeLog
2020-03-26 Anton Kolesov <anton.kolesov@synopsys.com>
* elf-bfd.h (elfcore_write_arc_v2): Add prototype.
* elf.c (elfcore_grok_arc_v2): New function.
(elfcore_grok_note): Call the new function to handle the corresponding
note.
(elfcore_write_arc_v2): New function.
(elfcore_write_register_note): Call the new function to handle the
corresponding pseudo-sections.
binutils/ChangeLog
2020-03-26 Anton Kolesov <anton.kolesov@synopsys.com>
* readelf.c (get_note_type): Handle NT_ARC_V2.
include/elf/ChangeLog
2020-03-26 Anton Kolesov <anton.kolesov@synopsys.com>
* common.h (NT_ARC_V2): New macro definitions.
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Introduce new relaxations XTENSA_PDIFF{8,16,32} for positive differences
(subtracted symbol precedes diminished symbol) and XTENSA_NDIFF{8,16,32}
for negative differences (subtracted symbol follows diminished symbol).
Don't generate XTENSA_DIFF relocations in the assembler, generate
XTENSA_PDIFF or XTENSA_NDIFF based on relative symbol position.
Handle XTENSA_DIFF in BFD for compatibility with old object files.
Handle XTENSA_PDIFF and XTENSA_NDIFF in BFD, treating difference value
as unsigned.
2020-04-22 Max Filippov <jcmvbkbc@gmail.com>
bfd/
* bfd-in2.h: Regenerated.
* elf32-xtensa.c (elf_howto_table): New entries for
R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}.
(elf_xtensa_reloc_type_lookup, elf_xtensa_do_reloc)
(relax_section): Add cases for R_XTENSA_PDIFF{8,16,32} and
R_XTENSA_NDIFF{8,16,32}.
* libbfd.h (bfd_reloc_code_real_names): Add names for
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32}.
* reloc.c: Add documentation for BFD_RELOC_XTENSA_PDIFF{8,16,32}
and BFD_RELOC_XTENSA_NDIFF{8,16,32}.
binutils/
* readelf.c (is_none_reloc): Recognize
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32}.
gas/
* config/tc-xtensa.c (md_apply_fix): Replace
BFD_RELOC_XTENSA_DIFF{8,16,32} generation with
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32} generation.
* testsuite/gas/xtensa/loc.d: Replace BFD_RELOC_XTENSA_DIFF16
with BFD_RELOC_XTENSA_PDIFF16 in the expected output.
include/
* elf/xtensa.h (elf_xtensa_reloc_type): New entries for
R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}.
ld/
* testsuite/ld-xtensa/relax-loc.d: New test definition.
* testsuite/ld-xtensa/relax-loc.s: New test source.
* testsuite/ld-xtensa/xtensa.exp (relax-loc): New test.
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git commit 211dc24b87 removed most sh5 and sh64 SuperH support, after
they were obsoleted by git commit 2b213129c5. This patch removes a
few remaining pieces that should have gone with 211dc24b87.
include/
* elf/sh.h (STO_SH5_ISA32, SHF_SH5_ISA32, SHF_SH5_ISA32_MIXED),
(SHT_SH5_CR_SORTED, STT_DATALABEL): Delete.
bfd/
* elf32-sh.c (sh_elf_relocate_section): Remove STO_SH5_ISA32
processing.
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FreeBSD's kernel recently added a new ELF auxiliary vector entry
holding a mask of software features provided by the kernel. This
change fixes 'info auxv' to report the name and description for this
vector entry instead of '???'.
include/ChangeLog:
* elf/common.h (AT_FREEBSD_BSDFLAGS): Define.
gdb/ChangeLog:
* fbsd-tdep.c (fbsd_print_auxv_entry): Handle AT_FREEBSD_BSDFLAGS.
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|
bfd/ChangeLog:
* elf.c (elfcore_grok_netbsd_note): Add support for
NT_NETBSDCORE_LWPSTATUS notes.
binutils/ChangeLog:
* readelf.c (get_netbsd_elfcore_note_type): Add support for
NT_NETBSDCORE_LWPSTATUS notes.
include/ChangeLog:
* elf/common.h (NT_NETBSDCORE_LWPSTATUS): New define.
|
|
* elf/common.h (NT_NETBSDCORE_AUXV): New define.
|
|
Fixes additional locations not handled in the first patch.
When converting between addresses in ELF headers [octets] and bfd
LMA/VMA [bytes], the number of octets per byte needs to be incorporated.
include/
* bfdlink.h (struct bfd_link_order): Add unit (bytes/octets) to
offset and size members.
* elf/internal.h (struct elf_internal_phdr): Likewise for
p_align member.
(struct elf_segment_map): Likewise for p_paddr and p_size
members
bfd/
* bfd.c (bfd_record_phdr): New local "opb". Fix assignment of
"p_paddr" from "at".
* elfcode.h (bfd_from_remote_memory): Add units to several
parameters. New local "opb". Fix usage of p_align. Fix
calculation of "localbase" from "ehdr_vma" and "p_vaddr". Fix
call of target_read_memory.
* elflink.c (elf_fixup_link_order): Fix scope of "s" local. Fix
calculation of "offset" and "output_offset".
(bfd_elf_final_link): New local "opb". Fix calculation of "size"
from "offset" and fix calculation of "end" from "vma+size". Fix
comparison between "sh_addr" and "vma"/"output_offset".
(bfd_elf_discard_info): Fix calculation of "eh_alignment".
* elf-bfd.h (struct elf_link_hash_table): Add unit to tls_size
member.
* elf.c (_bfd_elf_map_sections_to_segments): Add unit (bytes/
octets) to "wrap_to2 and "phdr_size" locals. Fix calculation of
"wrap_to" value. Add unit (bytes) to phdr_lma variable. Fix
assignment of p_paddr from phdr_lma. Fix comparison between
"lma+size" and "next->lma".
(elf_sort_segments): Fix assignment from p_paddr to lma.
(assign_file_positions_for_load_sections): Add unit (bytes) to
local "align". Fix calculation of local "off_adjust". Fix
calculation of local "filehdr_vaddr".
(assign_file_positions_for_non_load_sections): New local "opb".
Fix calculation of "end" from "p_size". Fix comparison between
"vma+SECTION_SIZE" and "start". Fix calculation of "p_memsz"
from "end" and "p_vaddr".
(rewrite_elf_program_header): Fix comparison between p_vaddr and
vma. Fix assignment to p_paddr from lma. Fix comparison between
p_paddr and lma. Fix assignment to p_paddr from lma.
* merge.c (sec_merge_emit): New local "opb". Convert
"alignment_power" to octets.
(_bfd_add_merge_section): New locals "alignment_power" and
"opb". Fix comparison between "alignment_power" and
"sizeof(align)".
(_bfd_merge_sections): New local "opb". Divide size by opb
before checking align mask.
|
|
When converting between addresses in ELF headers [octets] and bfd
LMA/VMA [bytes], the number of octets per byte needs to be
incorporated.
In ld, the SIZEOF_HEADERS linker script statement must be resolved to
bytes instead of octets.
include/
* elf/internal.h (struct elf_internal_phdr): Add unit (octets)
to several member field comments.
(Elf_Internal_Shdr): likewise.
bfd/
* elf.c (_bfd_elf_make_section_from_shdr): Introduce new temp
opb. Divide Elf_Internal_Shdr::sh_addr by opb when setting
section LMA/VMA.
(_bfd_elf_make_section_from_phdr): Similarly.
(elf_fake_sections): Fix calculation of
Elf_Internal_shdr::sh_addr from section VMA.
(_bfd_elf_map_sections_to_segments): Fix mixup between octets
and bytes.
(assign_file_positions_for_load_sections): Fix calculations of
Elf_Internal_shdr::p_vaddr and p_paddr from section LMA/VMA. Fix
comparison between program header address and section LMA.
(assign_file_positions_for_non_load_sections): Likewise.
(rewrite_elf_program_header): Likewise. Introduce new temp opb.
(IS_CONTAINED_BY_VMA): Add parameter opb.
(IS_CONTAINED_BY_LMA,IS_SECTION_IN_INPUT_SEGMENT,
INCLUDE_SECTION_IN_SEGMENT): Likewise.
(copy_elf_program_header): Update call to ELF_SECTION_IN_SEGMENT.
Fix calculations of p_addr_valid and p_vaddr_offset.
* elflink.c (elf_link_add_object_symbols): Multiply section VMA
with octets per byte when comparing against p_vaddr.
ld/
* ldexp.c (fold_name): Return SIZEOF_HEADERS in bytes.
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|
* elf/common.h (AT_L1I_CACHESIZE, AT_L1I_CACHEGEOMETRY)
(AT_L1D_CACHESIZE, AT_L1D_CACHEGEOMETRY, AT_L2_CACHESIZE)
(AT_L2_CACHEGEOMETRY, AT_L3_CACHESIZE, AT_L3_CACHEGEOMETRY)
(AT_MINSIGSTKSZ): New defines, imported from glibc.
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|
DWARF debug info support to the Z80 assembler.
PR 25469
bfd * archures.c: Add GBZ80 and Z80N machine values.
* reloc.c: Add BFD_RELOC_Z80_16_BE.
* coff-z80.c: Add support for new reloc.
* coffcode.h: Add support for new machine values.
* cpu-z80.c: Add support for new machine names.
* elf32-z80.c: Add support for new reloc.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
binutils* readelf.c (get_machine_flags): Add support for Z80N machine
number.
gas * config/tc-z80.c: Add -gbz80 command line option to generate code
for the GameBoy Z80. Add support for generating DWARF.
* config/tc-z80.h: Add support for DWARF debug information
generation.
* doc/c-z80.texi: Document new command line option.
* testsuite/gas/z80/gbz80_all.d: New file.
* testsuite/gas/z80/gbz80_all.s: New file.
* testsuite/gas/z80/z80.exp: Run the new tests.
* testsuite/gas/z80/z80n_all.d: New file.
* testsuite/gas/z80/z80n_all.s: New file.
* testsuite/gas/z80/z80n_reloc.d: New file.
include * coff/internal.h (R_IMM16BE): Define.
* elf/z80.h (EF_Z80_MACH_Z80N): Define.
(R_Z80_16_BE): New reloc.
ld * emulparams/elf32z80.sh: Use z80 emulation.
* emultempl/z80.em: Make generic to both COFF and ELF Z80 emulations.
* emultempl/z80elf.em: Delete.
* testsuite/ld-elf/pr22450.d: Expect to fail for the Z80.
* testsuite/ld-elf/sec64k.exp: Fix Z80 assembly.
* testsuite/ld-unique/pr21529.s: Avoid register name conflict.
* testsuite/ld-unique/unique.s: Likewise.
* testsuite/ld-unique/unique_empty.s: Likewise.
* testsuite/ld-unique/unique_shared.s: Likewise.
* testsuite/ld-unique/unique.d: Updated expected output.
* testsuite/ld-z80/arch_z80n.d: New file.
* testsuite/ld-z80/comb_arch_z80_z80n.d: New file.
* testsuite/ld-z80/labels.s: Add more labels.
* testsuite/ld-z80/relocs.s: Add more reloc tests.
* testsuite/ld-z80/relocs_f_z80n.d: New file
opcodes * z80-dis.c: Add support for GBZ80 opcodes.
|
|
include/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* elf/arc-cpu.def: Update ARC cpu list.
|
|
Add an ELF based target for these as well.
PR 25224
bfd * Makefile.am: Add z80-elf target support.
* configure.ac: Likewise.
* targets.c: Likewise.
* config.bfd: Add z80-elf target support and new arches: ez80 and z180.
* elf32-z80.c: New file.
* archures.c: Add new z80 architectures: eZ80 and Z180.
* coffcode.h: Likewise.
* cpu-z80.c: Likewise.
* bfd-in2.h: Likewise plus additional Z80 relocations.
* coff-z80.c: Add new relocations for Z80 target and local label check.
gas * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support
for assembler code generated by SDCC. Add new relocation types. Add
z80-elf target support.
* config/tc-z80.h: Add z80-elf target support. Enable dollar local
labels. Local labels starts from ".L".
* testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict.
* testsuite/gas/all/fwdexp.s: Likewise.
* testsuite/gas/z80/suffix.d: Fix failure on ELF target.
* testsuite/gas/z80/z80.exp: Add new tests
* testsuite/gas/z80/dollar.d: New file.
* testsuite/gas/z80/dollar.s: New file.
* testsuite/gas/z80/ez80_adl_all.d: New file.
* testsuite/gas/z80/ez80_adl_all.s: New file.
* testsuite/gas/z80/ez80_adl_suf.d: New file.
* testsuite/gas/z80/ez80_isuf.s: New file.
* testsuite/gas/z80/ez80_z80_all.d: New file.
* testsuite/gas/z80/ez80_z80_all.s: New file.
* testsuite/gas/z80/ez80_z80_suf.d: New file.
* testsuite/gas/z80/r800_extra.d: New file.
* testsuite/gas/z80/r800_extra.s: New file.
* testsuite/gas/z80/r800_ii8.d: New file.
* testsuite/gas/z80/r800_z80_doc.d: New file.
* testsuite/gas/z80/z180.d: New file.
* testsuite/gas/z80/z180.s: New file.
* testsuite/gas/z80/z180_z80_doc.d: New file.
* testsuite/gas/z80/z80_doc.d: New file.
* testsuite/gas/z80/z80_doc.s: New file.
* testsuite/gas/z80/z80_ii8.d: New file.
* testsuite/gas/z80/z80_ii8.s: New file.
* testsuite/gas/z80/z80_in_f_c.d: New file.
* testsuite/gas/z80/z80_in_f_c.s: New file.
* testsuite/gas/z80/z80_op_ii_ld.d: New file.
* testsuite/gas/z80/z80_op_ii_ld.s: New file.
* testsuite/gas/z80/z80_out_c_0.d: New file.
* testsuite/gas/z80/z80_out_c_0.s: New file.
* testsuite/gas/z80/z80_reloc.d: New file.
* testsuite/gas/z80/z80_reloc.s: New file.
* testsuite/gas/z80/z80_sli.d: New file.
* testsuite/gas/z80/z80_sli.s: New file.
ld * Makefile.am: Add new target z80-elf
* configure.tgt: Likewise.
* emultempl/z80.em: Add support for eZ80 and Z180 architectures.
* emulparams/elf32z80.sh: New file.
* emultempl/z80elf.em: Likewise.
* testsuite/ld-z80/arch_ez80_adl.d: Likewise.
* testsuite/ld-z80/arch_ez80_z80.d: Likewise.
* testsuite/ld-z80/arch_r800.d: Likewise.
* testsuite/ld-z80/arch_z180.d: Likewise.
* testsuite/ld-z80/arch_z80.d: Likewise.
* testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise.
* testsuite/ld-z80/comb_arch_z180.d: Likewise.
* testsuite/ld-z80/labels.s: Likewise.
* testsuite/ld-z80/relocs.s: Likewise.
* testsuite/ld-z80/relocs_b_ez80.d: Likewise.
* testsuite/ld-z80/relocs_b_z80.d: Likewise.
* testsuite/ld-z80/relocs_f_z80.d: Likewise.
* testsuite/ld-z80/z80.exp: Likewise.
opcodes * z80-dis.c: Add support for eZ80 and Z80 instructions.
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|
I think it is past time to remove CR16C support. CR16C was added in
2004, and only for ld. gas and binutils support is lacking, and there
have been no commits to bfd/elf32-cr16c.c other than warning fixes or
global maintainers making changes to all targets. I see no maintainer
listed for CR16C, and no commits from anyone at NSC supporting the
target. Furthermore, at the time the CR16 support was added in 2007,
config.sub was changed upstream to no longer recognise cr16c as a
valid cpu. That means the CR16C ld support is only available as a
secondary target by configuring with, for example,
--enable-targets=all or --enable-targets=cr16c-unknown-elf. No
testing of the CR16C target is possible.
include/
* elf/cr16c.h: Delete.
bfd/
* cpu-cr16c.c: Delete.
* elf32-cr16c.c: Delete.
* Makefile.am,
* archures.c,
* config.bfd,
* configure.ac,
* reloc.c,
* targets.c: Remove cr16c support.
* Makefile.in,
* bfd-in2.h,
* configure,
* libbfd.h,
* po/SRC-POTFILES.in: Regenerate.
ld/
* emulparams/elf32cr16c.sh: Delete.
* scripttempl/elf32cr16c.sc: Delete.
* Makefile.am,
* configure.tgt: Remove cr16c support.
* NEWS: Mention removal of cr16c.
* Makefile.in,
* po/BLD-POTFILES.in: Regenerate.
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This rewrites much of assign_file_positions_for_non_load_sections to
allow objcopy and strip to handle cases like that in PR4499 where
program headers were not in their usual position immediately after the
ELF file header, and PT_LOAD headers were not sorted by paddr.
PR 4499
include/
* elf/internal.h (struct elf_segment_map): Delete header_size.
Add no_sort_lma and idx.
bfd/
* elf-nacl.c (nacl_modify_segment_map): Set no_sort_lma for all
PT_LOAD segments.
* elf32-spu.c (spu_elf_modify_segment_map): Likewise on overlay
PT_LOAD segments.
* elf.c (elf_sort_segments): New function.
(assign_file_positions_except_relocs): Use shortcuts to elfheader
and elf_tdata. Seek to e_phoff not sizeof_ehdr to write program
headers. Move PT_PHDR check..
(assign_file_positions_for_non_load_sections): ..and code setting
PT_PHDR p_vaddr and p_paddr, and code setting __ehdr_start value..
(assign_file_positions_for_load_sections): ..to here. Sort
PT_LOAD headers. Delete header_pad code. Use actual number of
headers rather than allocated in calculating size for program
headers. Don't assume program headers follow ELF file header.
Simplify pt_load_count code. Only set "off" for PT_LOAD or
PT_NOTE in cores.
(rewrite_elf_program_header): Set p_vaddr_offset for segments
that include file and program headers.
(copy_elf_program_header): Likewise, replacing header_size code.
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This functionality will generate a new GNU object attribute for the "data region"
has been added. This object attribute is used
mark whether the compiler has generated code assuming that data could be in the
upper or lower memory regions.
Code which assumes data is always in the lower memory region is incompatible
with code which uses the full memory range for data.
The patch also adds a new assembler directive ".mspabi_attribute" to handle the
existing MSPABI object attributes. GCC will now emit both .gnu_attribute and
.mspabi_attribute directives to indicate what options the source file was
compiled with.
The assembler will now check the values set in these directives against the
options that the it has been invoked with. If there is a discrepancy, the
assembler will exit with an error.
bfd * elf32-msp430.c (elf32_msp430_merge_mspabi_attributes): Rename to..
(elf32_msp430_merge_msp430_attributes): Add support for merging the GNU
object attribute for data region.
binutils* readelf.c (display_msp430_gnu_attribute): New.
(process_arch_specific): Use msp430 specific handler for GNU
attributes.
gas * config/tc-msp430.c (md_parse_option): Set lower_data_region_only to
FALSE if the data region is set to "upper", "either" or "none".
(msp430_object_attribute): New.
(md_pseudo_table): Handle .mspabi_attribute and .gnu_attribute.
(msp430_md_end): Replace hard-coded attribute values with enums.
Handle data region object attribute.
* doc/as.texi: Document MSP430 Data Region object attribute.
* doc/c-msp430.texi: Document the .mspabi_attribute directive.
* testsuite/gas/msp430/attr-430-small-bad.d: New test.
* testsuite/gas/msp430/attr-430-small-bad.l: New test.
* testsuite/gas/msp430/attr-430-small-good.d: New test.
* testsuite/gas/msp430/attr-430-small.s: New test.
* testsuite/gas/msp430/attr-430x-large-any-bad.d: New test.
* testsuite/gas/msp430/attr-430x-large-any-bad.l: New test.
* testsuite/gas/msp430/attr-430x-large-any-good.d: New test.
* testsuite/gas/msp430/attr-430x-large-any.s: New test.
* testsuite/gas/msp430/attr-430x-large-lower-bad.d: New test.
* testsuite/gas/msp430/attr-430x-large-lower-bad.l: New test.
* testsuite/gas/msp430/attr-430x-large-lower-good.d: New test.
* testsuite/gas/msp430/attr-430x-large-lower.s: New test.
* testsuite/gas/msp430/msp430.exp: Run new tests.
include * elf/msp430.h: Add enums for MSPABI and GNU object attribute tag names
and values.
ld * testsuite/ld-msp430-elf/attr-gnu-main.s: New test.
* testsuite/ld-msp430-elf/attr-gnu-obj.s: New test.
* testsuite/ld-msp430-elf/attr-gnu-region-lower-upper.d: New test.
* testsuite/ld-msp430-elf/attr-gnu-region-lower.d: New test.
* testsuite/ld-msp430-elf/attr-gnu-region-upper.d: New test.
* testsuite/ld-msp430-elf/msp430-elf.exp: Run new tests.
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This patch removes use of st_target_internal to cache the result of
comparing symbol names against CMSE_PREFIX. The problem with setting
a bit in st_target_internal in swap_symbol_in is that calling
bfd_elf_sym_name from swap_symbol_in requires symtab_hdr, and you
don't know for sure whether swap_symbol_in is operating on dynsyms
(and thus elf_tdata (abfd)->dynsymtab_hdr should be used) or on the
normal symtab (thus elf_tdata (abfd)->symtab_hdr). You can make an
educated guess based on abfd->flags & DYNAMIC but that relies on
knowing a lot about calls to bfd_elf_get_elf_syms, and is fragile in
the face of possible future changes.
include/
* elf/arm.h (ARM_GET_SYM_CMSE_SPCL, ARM_SET_SYM_CMSE_SPCL): Delete.
bfd/
* elf32-arm.c (cmse_scan): Don't use ARM_GET_SYM_CMSE_SPCL,
instead recognize CMSE_PREFIX in symbol name.
(elf32_arm_gc_mark_extra_sections): Likewise.
(elf32_arm_filter_cmse_symbols): Don't test ARM_GET_SYM_CMSE_SPCL.
(elf32_arm_swap_symbol_in): Don't invoke ARM_SET_SYM_CMSE_SPCL.
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This patch is a reimplementation of [1] which was submitted in 2015 by
Neil Schellenberger. Copyright issue was sorted out [2] last year.
It proposed a new section (.gnu.xhash) and related dynamic tag
(DT_GNU_XHASH). The new section would be virtually identical to the
existing .gnu.hash except for the translation table (xlat) which would
contain correct MIPS .dynsym indexes corresponding to the hashvals in
chains. This is because MIPS ABI imposes a different ordering on the
dynsyms than the one expected by the .gnu.hash section. Another addition
would be a leading word (ngnusyms) which would contain the number of
entries in the translation table.
In this patch, the new section name and dynamic tag are changed to
reflect the fact that the section should be treated as MIPS-specific
(.MIPS.xhash and DT_MIPS_XHASH).
This patch addresses the alignment issue as reported in [3], which is
caused by the leading word added to the .MIPS.xhash section. Leading word
is removed in this patch, and the number of entries in the translation
table is now calculated using DT_MIPS_SYMTABNO dynamic tag (this is
addressed by the corresponding glibc patch).
Suggestions on coding style in [4] were taken into account. Existing
GNU hash testcase was covered, and another one was added in the MIPS
part of the testsuite.
The other major change is reserving MIPS ABI version 5 for .MIPS.xhash,
marking the need of support for .MIPS.xhash in the dynamic linker (again,
addressed in the corresponding glibc patch). This is something which I
am not sure of, especially after reading [5]. I am confused on whether
this ABI version is reserved for IFUNC, or it can be used for this
purpose.
Already mentioned glibc patch is submitted at:
https://sourceware.org/ml/libc-alpha/2019-06/msg00456.html
[1] https://sourceware.org/ml/binutils/2015-10/msg00057.html
[2] https://sourceware.org/ml/binutils/2018-03/msg00025.html
[3] https://sourceware.org/ml/binutils/2016-01/msg00006.html
[4] https://sourceware.org/ml/binutils/2016-02/msg00097.html
[5] https://sourceware.org/ml/libc-alpha/2016-12/msg00853.html
ld * emulparams/elf32bmip.sh: Add .MIPS.xhash section.
* emulparams/elf32bmipn32-defs.sh: Add .MIPS.xhash section.
* emulparams/elf64bmip-defs.sh: Add .MIPS.xhash section.
* emultempl/mipself.em: Remove mips_after_parse function.
* testsuite/ld-elf/hash.d: Update comment.
* testsuite/ld-mips-elf/hash1.d: New test.
* testsuite/ld-mips-elf/hash1.s: Ditto.
* testsuite/ld-mips-elf/hash1a.d: Remove.
* testsuite/ld-mips-elf/hash1b.d: Ditto.
* testsuite/ld-mips-elf/hash1c.d: Ditto
* testsuite/ld-mips-elf/hash2.d: New test.
* testsuite/ld-mips-elf/mips-elf.exp: New tests.
* testsuite/ld-mips-elf/start.s: New test.
bfd * elf-bfd.h (struct elf_backend_data): New members.
* elflink.c (_bfd_elf_link_create_dynamic_sections): Create
.gnu.hash section if necessary.
(struct collect_gnu_hash_codes): New member.
(elf_gnu_hash_process_symidx): New function name.
(elf_renumber_gnu_hash_syms): Ignore local and undefined
symbols. Record xlat location for every symbol which should have
a .MIPS.xhash entry.
(bfd_elf_size_dynamic_sections): Add DT_GNU_HASH dynamic tag to
dynamic section if necessary.
(GNU_HASH_SECTION_NAME): New define.
(bfd_elf_size_dynsym_hash_dynstr): Get .MIPS.xhash section.
Update the section size info.
* elfxx-mips.c (struct mips_elf_hash_sort_data): New members.
(struct mips_elf_link_hash_entry): New member.
(mips_elf_link_hash_newfunc): Initialize .MIPS.xhash translation
table location.
(mips_elf_sort_hash_table): Initialize the pointer to the
.MIPS.xhash section.
(mips_elf_sort_hash_table_f): Populate the .MIPS.xhash
translation table entry with the symbol dynindx.
(_bfd_mips_elf_section_from_shdr): Add SHT_MIPS_XHASH.
(_bfd_mips_elf_fake_sections): Initialize .MIPS.xhash section
info.
(_bfd_mips_elf_create_dynamic_sections): Create .MIPS.xhash
section.
(_bfd_mips_elf_size_dynamic_sections): Add DT_MIPS_XHASH tag to
dynamic section.
(_bfd_mips_elf_finish_synamic_sections): Add DT_MIPS_XHASH.
(_bfd_mips_elf_final_write_processing): Set .MIPS.xhash section
sh_link info.
(_bfd_mips_elf_get_target_dtag): Get DT_MIPS_XHASH tag.
(MIPS_LIBC_ABI_XHASH): New ABI version enum value.
(_bfd_mips_post_process_headers): Mark the ABI version as
MIPS_LIBC_ABI_XHASH if there exists a .MIPS.xhash section,
but not a .hash section.
(_bfd_mips_elf_record_xhash_symbol): New function. Record a
position in the translation table, associated with the hash
entry.
* elfxx-mips.h (literal_reloc_p): Define
elf_backend_record_xhash_symbol backend hook.
* elfxx-target.h: Initialize elf_backend_record_xhash_symbol
backend hook.
include * elf/mips.h (SHT_GNU_XHASH): New define.
(DT_GNU_XHASH): New define.
binutils * readelf.c (get_mips_dynamic_type): Return MIPS_XHASH dynamic type.
(get_mips_section_type_name): Return MI{S_XHASH name string.
(dynamic_section_mips_val): Initialize the .MIPS.xhash dynamic
info.
(process_symbol_table): Initialize the .MIPS.xhash section
pointer. Adjust the readelf output to support the new section.
(process_object): Set the .MIPS.xhash dynamic info to zero.
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* elf/internal.h (ELF_SECTION_IN_SEGMENT_1): Exclude non-alloc
sections in GNU_MBIND segments.
|
|
This patch supports using pcrel instructions in TLS code sequences. A
number of new relocations are needed, gas operand modifiers to
generate those relocations, and new TLS optimisation. For
optimisation it turns out that the new pcrel GD and LD sequences can
be distinguished from the non-pcrel GD and LD sequences by there being
different relocations on the new sequence. The final "add ra,rb,13"
on IE sequences similarly needs a new relocation, or as I chose, a
modification of R_PPC64_TLS. On pcrel IE code, the R_PPC64_TLS points
one byte into the "add" instruction rather than being on the
instruction boundary.
GD:
pla 3,z@got@tlsgd@pcrel # R_PPC64_GOT_TLSGD34
bl __tls_get_addr@notoc(z@tlsgd) # R_PPC64_TLSGD and R_PPC64_REL24_NOTOC
edited to IE
pld 3,z@got@tprel@pcrel
add 3,3,13
edited to LE
paddi 3,13,z@tprel
nop
LD:
pla 3,z@got@tlsld@pcrel # R_PPC64_GOT_TLSLD34
bl __tls_get_addr@notoc(z@tlsld) # R_PPC64_TLSLD and R_PPC64_REL24_NOTOC
..
paddi 9,3,z2@dtprel
pld 10,z3@got@dtprel@pcrel
add 10,10,3
edited to LE
paddi 3,13,0x1000
nop
IE:
pld 9,z@got@tprel@pcrel # R_PPC64_GOT_TPREL34
add 3,9,z@tls@pcrel # R_PPC64_TLS at insn+1
ldx 4,9,z@tls@pcrel
lwax 5,9,z@tls@pcrel
stdx 5,9,z@tls@pcrel
edited to LE
paddi 9,13,z@tprel
nop
ld 4,0(9)
lwa 5,0(9)
std 5,0(9)
LE:
paddi 10,13,z@tprel
include/
* elf/ppc64.h (R_PPC64_TPREL34, R_PPC64_DTPREL34),
(R_PPC64_GOT_TLSGD34, R_PPC64_GOT_TLSLD34),
(R_PPC64_GOT_TPREL34, R_PPC64_GOT_DTPREL34): Define.
(IS_PPC64_TLS_RELOC): Include new tls relocs.
bfd/
* reloc.c (BFD_RELOC_PPC64_TPREL34, BFD_RELOC_PPC64_DTPREL34),
(BFD_RELOC_PPC64_GOT_TLSGD34, BFD_RELOC_PPC64_GOT_TLSLD34),
(BFD_RELOC_PPC64_GOT_TPREL34, BFD_RELOC_PPC64_GOT_DTPREL34),
(BFD_RELOC_PPC64_TLS_PCREL): New pcrel tls relocs.
* elf64-ppc.c (ppc64_elf_howto_raw): Add howtos for pcrel tls relocs.
(ppc64_elf_reloc_type_lookup): Translate pcrel tls relocs.
(must_be_dyn_reloc, dec_dynrel_count): Add R_PPC64_TPREL64.
(ppc64_elf_check_relocs): Support pcrel tls relocs.
(ppc64_elf_tls_optimize, ppc64_elf_relocate_section): Likewise.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): Map "tls@pcrel", "got@tlsgd@pcrel",
"got@tlsld@pcrel", "got@tprel@pcrel", and "got@dtprel@pcrel".
(fixup_size, md_assemble): Handle pcrel tls relocs.
(ppc_force_relocation, ppc_fix_adjustable): Likewise.
(md_apply_fix, tc_gen_reloc): Likewise.
ld/
* testsuite/ld-powerpc/tlsgd.d,
* testsuite/ld-powerpc/tlsgd.s,
* testsuite/ld-powerpc/tlsie.d,
* testsuite/ld-powerpc/tlsie.s,
* testsuite/ld-powerpc/tlsld.d,
* testsuite/ld-powerpc/tlsld.s: New tests.
* testsuite/ld-powerpc/powerpc.exp: Run them.
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|
These ilp32 relocations were missing for some reason.
bfd/ChangeLog:
* elfnn-aarch64.c: Enable MOVW_PREL relocs for ELF32.
include/ChangeLog:
* elf/aarch64.h (R_AARCH64_P32_MOVW_PREL_G0): Define.
(R_AARCH64_P32_MOVW_PREL_G0_NC): Define.
(R_AARCH64_P32_MOVW_PREL_G1): Define.
ld/ChangeLog:
* testsuite/ld-aarch64/aarch64-elf.exp: Add emit-relocs-22 and -23.
* testsuite/ld-aarch64/emit-relocs-22.d: New test.
* testsuite/ld-aarch64/emit-relocs-22.s: New test.
* testsuite/ld-aarch64/emit-relocs-23.d: New test.
* testsuite/ld-aarch64/emit-relocs-23.s: New test.
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|
The bottom 2 bits of st_other are used for visibility, the top 6 bits are
de facto reserved for processor specific use. This patch defines a
bits to mark function symbols that follow a variant procedure call standard
with different register usage convention.
A dynamic tag is also defined that marks modules with R_<CLS>_JUMP_SLOT
relocations referencing symbols marked with STO_AARCH64_VARIANT_PCS.
This can be used by dynamic linkers that support lazy binding to decide
what registers need to be preserved during symbol resolution.
binutils/ChangeLog:
* readelf.c (get_aarch64_dynamic_type): Handle DT_AARCH64_VARIANT_PCS.
(get_aarch64_symbol_other): New, handles STO_AARCH64_VARIANT_PCS.
(get_symbol_other): Call get_aarch64_symbol_other.
include/ChangeLog:
* elf/aarch64.h (DT_AARCH64_VARIANT_PCS): Define.
(STO_AARCH64_VARIANT_PCS): Define.
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|
include/
* elf/ppc64.h (R_PPC64_PLTSEQ_NOTOC, R_PPC64_PLTCALL_NOTOC),
(R_PPC64_PCREL_OPT, R_PPC64_D34, R_PPC64_D34_LO, R_PPC64_D34_HI30),
(R_PPC64_D34_HA30, R_PPC64_PCREL34, R_PPC64_GOT_PCREL34),
(R_PPC64_PLT_PCREL34, R_PPC64_PLT_PCREL34_NOTOC),
(R_PPC64_ADDR16_HIGHER34, R_PPC64_ADDR16_HIGHERA34),
(R_PPC64_ADDR16_HIGHEST34, R_PPC64_ADDR16_HIGHESTA34),
(R_PPC64_REL16_HIGHER34, R_PPC64_REL16_HIGHERA34),
(R_PPC64_REL16_HIGHEST34, R_PPC64_REL16_HIGHESTA34),
(R_PPC64_D28, R_PPC64_PCREL28): Define.
bfd/
* reloc.c (BFD_RELOC_PPC64_D34, BFD_RELOC_PPC64_D34_LO),
(BFD_RELOC_PPC64_D34_HI30, BFD_RELOC_PPC64_D34_HA30),
(BFD_RELOC_PPC64_PCREL34, BFD_RELOC_PPC64_GOT_PCREL34),
(BFD_RELOC_PPC64_PLT_PCREL34),
(BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34),
(BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34),
(BFD_RELOC_PPC64_REL16_HIGHER34, BFD_RELOC_PPC64_REL16_HIGHERA34),
(BFD_RELOC_PPC64_REL16_HIGHEST34, BFD_RELOC_PPC64_REL16_HIGHESTA34),
(BFD_RELOC_PPC64_D28, BFD_RELOC_PPC64_PCREL28): New reloc enums.
* elf64-ppc.c (PNOP): Define.
(ppc64_elf_howto_raw): Add reloc howtos for new relocations.
(ppc64_elf_reloc_type_lookup): Translate new bfd reloc numbers.
(ppc64_elf_ha_reloc): Adjust addend for highera34 and highesta34
relocs.
(ppc64_elf_prefix_reloc): New function.
(struct ppc_link_hash_table): Add notoc_plt.
(is_branch_reloc): Add R_PPC64_PLTCALL_NOTOC.
(is_plt_seq_reloc): Add R_PPC64_PLT_PCREL34,
R_PPC64_PLT_PCREL34_NOTOC, and R_PPC64_PLTSEQ_NOTOC.
(ppc64_elf_check_relocs): Handle pcrel got and plt relocs. Set
has_pltcall for section on seeing R_PPC64_PLTCALL_NOTOC. Handle
possible need for dynamic relocs on non-pcrel powerxx relocs.
(dec_dynrel_count): Handle non-pcrel powerxx relocs.
(ppc64_elf_inline_plt): Handle R_PPC64_PLTCALL_NOTOC.
(toc_adjusting_stub_needed): Likewise.
(ppc64_elf_tls_optimize): Handle R_PPC64_PLTSEQ_NOTOC.
(ppc64_elf_relocate_section): Handle new powerxx relocs.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): Support @pcrel, @got@pcrel,
@plt@pcrel, @higher34, @highera34, @highest34, and @highesta34.
(fixup_size): Handle new powerxx relocs.
(md_assemble): Warn for @pcrel on non-prefix insns.
Accept @l, @h and @ha on prefix insns, and infer reloc without
any @ suffix. Translate powerxx relocs to suit DQ and DS field
instructions. Include operand tests as well as opcode test to
translate BFD_RELOC_HI16_S to BFD_RELOC_PPC_16DX_HA.
(ppc_fix_adjustable): Return false for pcrel GOT and PLT relocs.
(md_apply_fix): Handle new powerxx relocs.
* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Accept
BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34,
BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34,
BFD_RELOC_PPC64_D34, and BFD_RELOC_PPC64_D28.
* testsuite/gas/ppc/prefix-reloc.d,
* testsuite/gas/ppc/prefix-reloc.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
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|
This patch adds a header file with BPF-specific ELF definitions. In
particular, the architecture relocations.
include/ChangeLog:
2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
* elf/bpf.h: New file.
|
|
bfd/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Add case for Tag_MVE_arch.
binutils/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* readelf.c (arm_attr_tag_MVE_arch): New array for Tag_MVE_arch values.
(arm_attr_public_tag arm_attr_public_tags): Add case for Tag_MVE_arch.
elfcpp/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* arm.h (Tag_MVE_arch): Define new enum value.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (mve_ext, mve_fp_ext): New features.
(armv8_1m_main_ext_table): Add new extensions.
(aeabi_set_public_attributes): Translate new features to new build attributes.
(arm_convert_symbolic_attribute): Add Tag_MVE_arch.
* doc/c-arm.texi: Document new extensions and new build attribute.
include/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* elf/arm.h (Tag_MVE_arch): Define new enum value.
* opcode/arm.h (FPU_MVE, FPU_MVE_FP): New MACROs for new features.
|
|
R_ARM_THM_BF12
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This adds infrastructure for the BFCSEL instructions which is one of the first
instructions in Arm that have more than one relocations in them.
This adds a new relocation R_ARM_THM_BF12.
The inconsistency between external R_ARM_THM_BF12 and internal
BFD_RELOC_ARM_THUMB_BF13 is because internally we count the static bit-0 of the
immediate and we don't externally.
ChangeLog entries are as follows :
ChangeLog entries are as follows :
*** bfd/ChnageLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF13): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13
and R_ARM_THM_BF12 together.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13.
*** elfcpp/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF12): New relocation code.
*** gas/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF13.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12.
*** opcodes/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
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|
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This adds infrastructure for the BFL instructions which is one of the first instructions in Arm that have more than one relocations in them.
This adds a new relocation R_ARM_THM_BF18.
The inconsistency between external R_ARM_THM_BF18 and internal
BFD_RELOC_ARM_THUMB_BF19 is because internally we count the static bit-0 of the immediate and we don't externally.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF19): New
* libbfd.h: Regenerated.
* bfd-in2.h: Regenerated.
* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19
and R_ARM_THM_BF18 together.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19.
*** elfcpp/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF18): New relocation code.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF19.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
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R_ARM_THM_BF16
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This adds infrastructure for the BF instructions which is one of the first instructions in Arm that have more than one relocations in them.
This is the third infrastructure patch that adds a new relocation R_ARM_THM_BF16.
The inconsistency between external R_ARM_THM_BF16 and internal
BFD_RELOC_ARM_THUMB_BF17 is because internally we count the static bit-0 of the immediate and we don't externally.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF17): New enum.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF16.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF17
and R_ARM_THM_BF16 together.
(get_value_helper): New reloc helper.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF16.
*** elfcpp/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF16): New relocation code.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF17.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
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|
The patch is straightforward, it does the following:
- support the new Tag_CPU_arch build attribute value, ie.:
+ declare the new value
+ update all the asserts forcing logic to be reviewed for new
architectures
+ create a corresponding bfd_mach_arm_8_1M_MAIN enumerator in bfd and
add mapping from Tag_CPU_arch to it
+ teach readelf about new Tag_CPU_arch value
- declare armv8.1-m.main as a supported architecture value
- define Armv8.1-M Mainline in terms of feature bits available
- tell objdump mapping from bfd_mach_arm_8_1M_MAIN enumerator to feature
bits available
- update architecture-specific logic in gas and bfd guarded by the
asserts mentioned above.
- tests for all the above
ChangeLog entries are as follows:
*** bfd/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* archures.c (bfd_mach_arm_8_1M_MAIN): Define.
* bfd-in2.h: Regenerate.
* cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline.
* elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline
and update assert.
(using_thumb2): Likewise.
(using_thumb2_bl): Update assert.
(arch_has_arm_nop): Likewise.
(bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline.
(tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging.
*** binutils/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* readelf.c (arm_attr_tag_CPU_arch): Add entry for Armv8.1-M Mainline.
*** gas/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline
Tag_CPU_arch build attribute value. Reindent.
(get_aeabi_cpu_arch_from_fset): Update assert.
(aeabi_set_public_attributes): Update assert for Tag_DIV_use logic.
* testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test.
*** include/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro.
(MAX_TAG_CPU_ARCH): Set value to above macro.
* opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro.
(ARM_AEXT_V8_1M_MAIN): Likewise.
(ARM_AEXT2_V8_1M_MAIN): Likewise.
(ARM_ARCH_V8_1M_MAIN): Likewise.
*** ld/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* testsuite/ld-arm/attr-merge-13.attr: New test.
* testsuite/ld-arm/attr-merge-13a.s: New test.
* testsuite/ld-arm/attr-merge-13b.s: New test.
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
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Update assembler and readelf to support
#define GNU_PROPERTY_X86_ISA_1_AVX512_BF16 (1U << 24)
for AVX512_BF16.
binutils/
* readelf.c (decode_x86_isa): Handle
GNU_PROPERTY_X86_ISA_1_AVX512_BF16.
* testsuite/binutils-all/i386/pr21231b.d: Updated.
* testsuite/binutils-all/x86-64/pr21231b.d: Likewise.
gas/
* config/tc-i386.c (output_insn): Support
GNU_PROPERTY_X86_ISA_1_AVX512_BF16.
* testsuite/gas/i386/property-2.s: Add AVX512_BF16 test.
* testsuite/gas/i386/property-2.d: Updated.
* testsuite/gas/i386/x86-64-property-2.d: Likewise.
include/
* elf/common.h (GNU_PROPERTY_X86_ISA_1_AVX512_BF16): New.
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This is part of the patch series to add support for BTI and
PAC in AArch64 linker.
1) This patch adds new definitions of PAC enabled PLTs
and both BTI and PAC enabled PLTs.
2) It also defines the new dynamic tag DT_AARCH64_PAC_PLT
for the PAC enabled PLTs.
3) This patch adds a new ld command line option: --pac-plt.
In the presence of this option, the linker uses the PAC
enabled PLTs and marks with DT_AARCH64_PAC_PLT.
4) In case both BTI and PAC are enabled the linker should
pick PLTs enabled with both and also use dynamic tags for both.
All these are made according to the new AArch64 ELF ABI
https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4
*** bfd/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
* elfnn-aarch64.c (PLT_PAC_ENTRY_SIZE, PLT_PAC_SMALL_ENTRY_SIZE): New.
(PLT_BTI_PAC_ENTRY_SIZE, PLT_BTI_PAC_SMALL_ENTRY_SIZE): New.
(setup_plt_values): Account for PAC or PAC and BTI enabled PLTs.
(elfNN_aarch64_size_dynamic_sections): Add checks for PLT_BTI_PAC
and PLT_PAC_PLT.
(elfNN_aarch64_finish_dynamic_sections): Account for PLT_BTI_PAC.
(get_plt_type): Add case for DT_AARCH64_PAC_PLT.
(elfNN_aarch64_plt_sym_val): Add cases for PLT_BTI_PAC and PLT_PAC.
*** binutils/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
* readelf.c (get_aarch64_dynamic_type): Add case for
DT_AARCH64_PAC_PLT.
(dynamic_section_aarch64_val): Likewise.
*** include/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
* elf/aarch64.h (DT_AARCH64_PAC_PLT): New.
*** ld/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
* NEWS: Document --pac-plt.
* emultempl/aarch64elf.em (OPTION_PAC_PLT): New.
(PARSE_AND_LIST_LONGOPTS, PARSE_AND_LIST_OPTIONS): Add pac-plt.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_PAC_PLT.
* testsuite/ld-aarch64/aarch64-elf.exp: Add the following tests.
* testsuite/ld-aarch64/bti-pac-plt-1.d: New test.
* testsuite/ld-aarch64/bti-pac-plt-2.d: New test.
* testsuite/ld-aarch64/pac-plt-1.d: New test.
* testsuite/ld-aarch64/pac-plt-2.d: New test.
* testsuite/ld-aarch64/bti-plt-1.s: Add .ifndef directive.
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enabled PLTs
This is part of the patch series to add support for BTI and
PAC in AArch64 linker.
1) This patch adds a new ld command line option: --force-bti.
In the presence of this option, the linker enables BTI with the
GNU_PROPERTY_AARCH64_FEATURE_1_BTI feature. This gives out warning
in case of missing gnu notes for BTI in inputs.
2) It also defines a new set of BTI enabled PLTs. These are used either
when all the inputs are marked with GNU_PROPERTY_AARCH64_FEATURE_1_BTI
or when the new --force-bti option is used. This required adding new
fields in elf_aarch64_link_hash_table so that we could make the PLT
related information more generic.
3) It also defines a dynamic tag DT_AARCH64_BTI_PLT. The linker uses
this whenever it picks BTI enabled PLTs.
All these are made according to the new AArch64 ELF ABI
https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4
*** bfd/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
Szabolcs Nagy <szabolcs.nagy@arm.com>
* bfd-in.h (aarch64_plt_type, aarch64_enable_bti_type): New.
(aarch64_bti_pac_info): New.
(bfd_elf64_aarch64_set_options): Add aarch64_bti_pac_info argument.
(bfd_elf32_aarch64_set_options): Likewise.
* bfd-in2.h: Regenerate
* elfnn-aarch64.c (PLT_BTI_ENTRY_SIZE): New.
(PLT_BTI_SMALL_ENTRY_SIZE, PLT_BTI_TLSDESC_ENTRY_SIZE): New.
(elfNN_aarch64_small_plt0_bti_entry): New.
(elfNN_aarch64_small_plt_bti_entry): New.
(elfNN_aarch64_tlsdesc_small_plt_bti_entry): New.
(elf_aarch64_obj_tdata): Add no_bti_warn and plt_type fields.
(elf_aarch64_link_hash_table): Add plt0_entry, plt_entry and
tlsdesc_plt_entry_size fields.
(elfNN_aarch64_link_hash_table_create): Initialise the new fields.
(setup_plt_values): New helper function.
(bfd_elfNN_aarch64_set_options): Use new bp_info to set plt sizes and
bti enable type.
(elfNN_aarch64_allocate_dynrelocs): Use new size members instead of
fixed macros.
(elfNN_aarch64_size_dynamic_sections): Likewise and add checks.
(elfNN_aarch64_create_small_pltn_entry): Use new generic pointers
to plt stubs instead of fixed ones and update filling them according
to the need for bti.
(elfNN_aarch64_init_small_plt0_entry): Likewise.
(elfNN_aarch64_finish_dynamic_sections): Likewise.
(get_plt_type, elfNN_aarch64_get_synthetic_symtab): New.
(elfNN_aarch64_plt_sym_val): Update size accordingly.
(elfNN_aarch64_link_setup_gnu_properties): Set up plts if BTI GNU NOTE
is set.
(bfd_elfNN_get_synthetic_symtab): Define.
(elfNN_aarch64_merge_gnu_properties): Give out warning with --force-bti
and mising BTI NOTE SECTION.
*** binutils/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
Szabolcs Nagy <szabolcs.nagy@arm.com>
* readelf.c (get_aarch64_dynamic_type): New.
(get_dynamic_type): Use above for EM_AARCH64.
(dynamic_section_aarch64_val): New.
(process_dynamic_section): Use above for EM_AARCH64.
*** include/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
Szabolcs Nagy <szabolcs.nagy@arm.com>
* elf/aarch64.h (DT_AARCH64_BTI_PLT): New.
*** ld/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
Szabolcs Nagy <szabolcs.nagy@arm.com>
* NEWS: Document --force-bti.
* emultempl/aarch64elf.em (plt_type, bti_type, OPTION_FORCE_BTI): New.
(PARSE_AND_LIST_SHORTOPTS, PARSE_AND_LIST_OPTIONS): Add force-bti.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_FORCE_BTI.
* testsuite/ld-aarch64/aarch64-elf.exp: Add all the tests below.
* testsuite/ld-aarch64/bti-plt-1.d: New test.
* testsuite/ld-aarch64/bti-plt-1.s: New test.
* testsuite/ld-aarch64/bti-plt-2.s: New test.
* testsuite/ld-aarch64/bti-plt-2.d: New test.
* testsuite/ld-aarch64/bti-plt-3.d: New test.
* testsuite/ld-aarch64/bti-plt-4.d: New test.
* testsuite/ld-aarch64/bti-plt-5.d: New test.
* testsuite/ld-aarch64/bti-plt-6.d: New test.
* testsuite/ld-aarch64/bti-plt-7.d: New test.
* testsuite/ld-aarch64/bti-plt-so.s: New test.
* testsuite/ld-aarch64/bti-plt.ld: New test.
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and PAC
This is part of the patch series to add support for BTI and
PAC in AArch64 linker.
This patch implements the following:
1) This extends in the gnu property support in the linker for
AArch64 by defining backend hooks for elf_backend_setup_gnu_properties,
elf_backend_merge_gnu_properties and elf_backend_parse_gnu_properties.
2) It defines AArch64 specific GNU property
GNU_PROPERTY_AARCH64_FEATURE_1_AND and 2 bit for BTI and PAC in it.
3) It also adds support in readelf.c to read and print these new
GNU properties in AArch64.
All these are made according to the new AArch64 ELF ABI
https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2018q4
*** bfd/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
* elf-properties.c (_bfd_elf_link_setup_gnu_properties): Exclude
linker created inputs from merge.
* elfnn-aarch64.c (struct elf_aarch64_obj_tdata): Add field for
GNU_PROPERTY_AARCH64_FEATURE_1_AND properties.
(elfNN_aarch64_link_setup_gnu_properties): New.
(elfNN_aarch64_merge_gnu_properties): New.
(elf_backend_setup_gnu_properties): Define for AArch64.
(elf_backend_merge_gnu_properties): Likewise.
* elfxx-aarch64.c (_bfd_aarch64_elf_link_setup_gnu_properties): Define.
(_bfd_aarch64_elf_parse_gnu_properties): Define.
(_bfd_aarch64_elf_merge_gnu_properties): Define.
* elfxx-aarch64.h (_bfd_aarch64_elf_link_setup_gnu_properties): Declare.
(_bfd_aarch64_elf_parse_gnu_properties): Declare.
(_bfd_aarch64_elf_merge_gnu_properties): Declare.
(elf_backend_parse_gnu_properties): Define for AArch64.
*** binutils/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
* readelf.c (decode_aarch64_feature_1_and): New.
(print_gnu_property_note): Add case for AArch64 gnu notes.
*** include/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
* elf/common.h (GNU_PROPERTY_AARCH64_FEATURE_1_AND): New.
(GNU_PROPERTY_AARCH64_FEATURE_1_BTI): New.
(GNU_PROPERTY_AARCH64_FEATURE_1_PAC): New.
*** ld/ChangeLog ***
2019-03-13 Sudakshina Das <sudi.das@arm.com>
* NEWS: Document GNU_PROPERTY_AARCH64_FEATURE_1_BTI and
GNU_PROPERTY_AARCH64_FEATURE_1_PAC.
* testsuite/ld-aarch64/aarch64-elf.exp: Add run commands for new tests.
* testsuite/ld-aarch64/property-bti-pac1.d: New test.
* testsuite/ld-aarch64/property-bti-pac1.s: New test.
* testsuite/ld-aarch64/property-bti-pac2.d: New test.
* testsuite/ld-aarch64/property-bti-pac2.s: New test.
* testsuite/ld-aarch64/property-bti-pac3.d: New test.
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Used for the AArch64 pointer authentication code mask registers in Arm v8.3-a.
NT_ARM_PAC_MASK matches the value in Linux include/uapi/linux/elf.h
include/ChangeLog:
* elf/common.h (NT_ARM_PAC_MASK): Add define.
bfd/ChangeLog:
* elf-bfd.h (elfcore_write_aarch_pauth): Add declaration.
* elf.c (elfcore_grok_aarch_pauth): New function.
(elfcore_grok_note): Check for NT_ARM_PAC_MASK.
(elfcore_write_aarch_pauth): New function.
(elfcore_write_register_note): Check for AArch64 pauth section.
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