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2022-07-08Add markers for 2.39 branchNick Clifton1-0/+4
2022-04-20Stubs (added in a later patch) will generate new .loader symbols, once the ↵Cl?ment Chigot1-0/+5
allocations have been done. Thus, the .loader section cannot be layout before that. bfd/ChangeLog: * coff-rs6000.c (_bfd_xcoff_put_ldsymbol_name): Write len in ldinfo->strings instead of directly in the output_bfd. * coff64-rs6000.c (_bfd_xcoff64_put_ldsymbol_name): Likewise. * xcofflink.c (struct xcoff_link_hash_table): Remove ldrel_count field. Add ldinfo field. (xcoff_mark_symbol): Adjust to new ldinfo field. (xcoff_mark): Likewise. (bfd_xcoff_link_count_reloc): Likewise. (xcoff_build_loader_section): Split into two functions: one that build the loader section (this function) and one that only size it... (xcoff_size_loader_section): ... (this function). (bfd_xcoff_size_dynamic_sections): Adapt to new ldinfo field. Move the part where the dynamic sections are build to ... (bfd_xcoff_build_dynamic_sections): ... this function. * xcofflink.h: Add bfd_xcoff_build_dynamic_sections prototype. include/ChangeLog: * coff/xcoff.h (struct xcoff_loader_info): Add ldrel_count and libpath fields. ld/ChangeLog: * emultempl/aix.em (_after_allocation): New function.
2022-04-07Add support for COFF secidx relocationsMark Harmstone1-0/+5
bfd * coff-i386.c (in_reloc_p): Add R_SECTION. (howto_table): Add R_SECTION. (coff_pe_i386_relocation_section): Add support for R_SECTION. (coff_i386_reloc_type_lookup): Add support for BFD_RELOC_16_SECCIDX. * coff-x86_64.c (in_reloc_p): Add R_SECTION. (howto_table): Add R_SECTION. (coff_pe_amd64_relocation_section): Add support for R_SECTION. (coff_amd64_reloc_type_lookup): Add support for BFD_RELOC_16_SECCIDX. * reloc.c: Add BFD_RELOC_16_SECIDX. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas * config/tc-i386.c (pe_directive_secidx): New function. (md_pseudo_table): Add support for secidx. (x86_cons_fix_new): Likewise. (tc_gen_reloc): Likewise. * expr.c (op_rank): Add O_secidx. * expr.h (operatorT): Likewise. * symbols.c (resolve_symbol_value): Add support for O_secidx. * testsuite/gas/i386/secidx.s: New test source file. * testsuite/gas/i386/secidx.d: New test driver file. * testsuite/gas/i386/i386.exp: Run new test. include * coff/i386.h: Define R_SECTION. * coff/x86_64.h: Likewise. ld * testsuite/ld-pe/secidx1.s: New test source file. * testsuite/ld-pe/secidx2.s: New test source file. * testsuite/ld-pe/secidx.d: New test driver file. * testsuite/ld-pe/secidx_64.d: New test driver file. * testsuite/ld-pe/pe.exp: Add new tests.
2022-04-01Recognize FreeBSD core dump note for x86 segment base registers.John Baldwin1-0/+4
This core dump note contains the value of the base address of the %fs and %gs segments for both i386 and amd64 core dumps. It is primarily useful in resolving the address of TLS variables in core dumps. binutils/ChangeLog: * readelf.c (get_freebsd_elfcore_note_type): Handle NT_FREEBSD_X86_SEGBASES. include/ChangeLog: * elf/common.h (NT_FREEBSD_X86_SEGBASES): Define.
2022-03-16binutils/readelf: handle AMDGPU relocation typesSimon Marchi1-0/+4
Make readelf recognize AMDGPU relocation types, as documented here: https://llvm.org/docs/AMDGPUUsage.html#amdgpu-relocation-records The user-visible change looks like: -000000000004 000400000001 unrecognized: 1 0000000000000000 SCRATCH_RSRC_DWORD0 -00000000000c 000500000001 unrecognized: 1 0000000000000000 SCRATCH_RSRC_DWORD1 -000000000014 000600000007 unrecognized: 7 0000000000000000 global_var0 -00000000001c 000700000008 unrecognized: 8 0000000000000000 global_var1 -000000000024 000800000009 unrecognized: 9 0000000000000000 global_var2 -00000000002c 00090000000a unrecognized: a 0000000000000000 global_var3 -000000000034 000a0000000b unrecognized: b 0000000000000000 global_var4 +000000000004 000400000001 R_AMDGPU_ABS32_LO 0000000000000000 SCRATCH_RSRC_DWORD0 +00000000000c 000500000001 R_AMDGPU_ABS32_LO 0000000000000000 SCRATCH_RSRC_DWORD1 +000000000014 000600000007 R_AMDGPU_GOTPCREL 0000000000000000 global_var0 +00000000001c 000700000008 R_AMDGPU_GOTPCREL 0000000000000000 global_var1 +000000000024 000800000009 R_AMDGPU_GOTPCREL 0000000000000000 global_var2 +00000000002c 00090000000a R_AMDGPU_REL32_LO 0000000000000000 global_var3 +000000000034 000a0000000b R_AMDGPU_REL32_HI 0000000000000000 global_var4 binutils/ChangeLog: * readelf.c (dump_relocations): Handle EM_AMDGPU. include/ChangeLog: * elf/amdgpu.h: Add relocation values. Change-Id: I2ed4589f4cd37ea11ad2e0cb38d4b682271e1334
2022-03-16binutils/readelf: handle NT_AMDGPU_METADATA note nameSimon Marchi1-0/+4
Handle the NT_AMDGPU_METADATA note, which is described here: https://llvm.org/docs/AMDGPUUsage.html#code-object-v3-note-records As of this patch, just print out the name, not the contents, which is in the msgpack format. binutils/ChangeLog: * readelf.c (get_amdgpu_elf_note_type): New. (process_note): Handle "AMDGPU" notes. include/ChangeLog: * elf/amdgcn.h (NT_AMDGPU_METADATA): New. Change-Id: Id2dba2e2aeaa55ef7464fb35aee9c7d5f96ddb23
2022-03-16binutils/readelf: decode AMDGPU-specific e_flagsSimon Marchi1-0/+5
Decode and print the AMDGPU-specific fields of e_flags, as documented here: https://llvm.org/docs/AMDGPUUsage.html#header That is: - The specific GPU model - Whether the xnack and sramecc features are enabled The result looks like: - Flags: 0x52f + Flags: 0x52f, gfx906, xnack any, sramecc any The flags for the "HSA" OS ABI are properly versioned and documented on that page. But the NONE, PAL and MESA3D OS ABIs are not well documented nor versioned. Taking a peek at the LLVM source code, we see that they encode their flags the same way as HSA v3. For example, for PAL: https://github.com/llvm/llvm-project/blob/c8b614cd74a92d85936aed5ac7c642af75ffdc29/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp#L601 So for those other OS ABIs, we read them the same as HSA v3. binutils/ChangeLog: * readelf.c: Include elf/amdgcn.h. (decode_AMDGPU_machine_flags): New. (get_machine_flags): Handle flags for EM_AMDGPU machine type. include/ChangeLog: * elf/amdgcn.h: Add EF_AMDGPU_MACH_AMDGCN_* and EF_AMDGPU_FEATURE_* defines. Change-Id: Ib5b94df7cae0719a22cf4e4fd0629330e9485c12
2022-03-16binutils/readelf: handle AMDGPU OS ABIsSimon Marchi1-0/+5
When the machine is EM_AMDGPU, handle the various OS ABIs described here: https://llvm.org/docs/AMDGPUUsage.html#header For a binary with the HSA OS ABI, the change looks like: - OS/ABI: <unknown: 40> + OS/ABI: AMD HSA binutils/ChangeLog: * readelf.c (get_osabi_name): Handle EM_AMDGPU OS ABIs. include/ChangeLog: * elf/common.h (ELFOSABI_AMDGPU_PAL, ELFOSABI_AMDGPU_MESA3D): New. Change-Id: I383590c390f7dc2fe0f902f50038735626d71863
2022-03-16bfd: add AMDGCN architectureSimon Marchi1-0/+5
Add support for the AMDGCN architecture to BFD. This is the bare minimum to get $ ./configure --target=amdgcn-hsa-amdhsa --disable-gas $ make all-binutils working later in this series. The specific AMDGCN models added here are a bit arbitrary, based on what we intend to initially support in GDB. This list will need to be updated in the future anyway. The complete up-to-date list of existing AMDGPU models can be found here: https://llvm.org/docs/AMDGPUUsage.html#processors The ELF format for this architecture is documented here: https://llvm.org/docs/AMDGPUUsage.html#elf-code-object The flags for the "HSA" OS ABI are properly versioned and documented on that page. But the NONE, PAL and MESA3D OS ABIs are not well documented nor versioned. Taking a peek at the LLVM source code, we see that they encode their flags the same way as HSA v3. For example, for PAL: https://github.com/llvm/llvm-project/blob/c8b614cd74a92d85936aed5ac7c642af75ffdc29/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp#L601 So at least, we know that all AMDGPU objects (of which AMDGCN objects are a subset of) at the time of writing encode the specific GPU model in the EF_AMDGPU_MACH field of e_flags. bfd/ChangeLog: * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES): Add cpu-amdgcn.c. (BFD64_BACKENDS): Add elf64-amdgcn.lo. (BFD64_BACKENDS_CFILES): Add elf64-amdgcn.c. * Makefile.in: Re-generate. * cpu-amdgcn.c: New. * elf64-amdgcn.c: New. * archures.c (bfd_architecture): Add bfd_arch_amdgcn and related mach defines. (bfd_amdgcn_arch): New. (bfd_archures_list): Add bfd_amdgcn_arch. * bfd-in2.h: Re-generate. * config.bfd: Handle amdgcn* target. * configure.ac: Handle amdgcn_elf64_le_vec. * configure: Re-generate. * elf-bfd.h (elf_target_id): Add AMDGCN_ELF_DATA. * targets.c (amdgcn_elf64_le_vec): New. (_bfd_target_vector): Add amdgcn_elf64_le_vec. include/ChangeLog: * elf/amdgpu.h: New. * elf/common.h (ELFOSABI_AMDGPU_HSA): Add. Change-Id: I969f7b14960797e88891c308749a6e341eece5b2
2022-03-11gprofng: a new GNU profilerVladimir Mezentsev1-0/+6
top-level * Makefile.def: Add gprofng module. * configure.ac: Add --enable-gprofng option. * src-release.sh: Add gprofng. * Makefile.in: Regenerate. * configure: Regenerate. * gprofng: New directory. binutils * MAINTAINERS: Add gprofng maintainer. * README-how-to-make-a-release: Add gprofng. include. * collectorAPI.h: New file. * libcollector.h: New file. * libfcollector.h: New file.
2022-01-25Fix a probem building the binutils on SPARC/amd64Klaus Ziegler1-0/+5
PR 28816 * elf/common.h (AT_SUN_HWCAP): Make definition conditional.
2022-01-22Add markers for 2.38 branchNick Clifton1-0/+4
2022-01-13Synchronize binutils libiberty sources with gcc version.Nick Clifton1-0/+8
+2021-12-30 Lancelot SIX <lsix@lancelotsix.com> + + * cp-demangle.c (d_clone_suffix): Support digits in clone tag + names. + * testsuite/demangle-expected: Check demangling of clone symbols + with digits in name. + +2021-12-16 H.J. Lu <hjl.tools@gmail.com> + + Revert: + 2021-12-16 H.J. Lu <hjl.tools@gmail.com> + + * Makefile.in (AR): Add @AR_PLUGIN_OPTION@ + (RANLIB): Add @RANLIB_PLUGIN_OPTION@. + (configure_deps): Depend on ../config/gcc-plugin.m4. + * configure.ac: AC_SUBST AR_PLUGIN_OPTION and + RANLIB_PLUGIN_OPTION. + * aclocal.m4: Regenerated. + * configure: Likewise. + +2021-12-15 H.J. Lu <hjl.tools@gmail.com> + + * Makefile.in (AR): Add @AR_PLUGIN_OPTION@ + (RANLIB): Add @RANLIB_PLUGIN_OPTION@. + (configure_deps): Depend on ../config/gcc-plugin.m4. + * configure.ac: AC_SUBST AR_PLUGIN_OPTION and + RANLIB_PLUGIN_OPTION. + * aclocal.m4: Regenerated. + * configure: Likewise. + +2021-11-29 Eric Gallager <egallager@gcc.gnu.org> + + PR other/103021 + * Makefile.in: Use ETAGS variable in TAGS target. + * configure: Regenerate. + * configure.ac: Allow ETAGS variable to be overridden. + +2021-11-29 Andrew Pinski <apinski@marvell.com> + + * make-temp-file.c (try_dir): Check to see if the dir + is actually a directory. + +2021-10-22 Eric Gallager <egallager@gcc.gnu.org> + + PR other/102663 + * Makefile.in: Allow dvi-formatted documentation + to be installed. + +2021-10-17 Lu?s Ferreira <contact@lsferreira.net> + + PR d/102618 + * d-demangle.c (dlang_parse_qualified): Handle anonymous + symbols correctly. + * testsuite/d-demangle-expected: New tests to cover anonymous + symbols. + +2021-10-14 Lu?s Ferreira <contact@lsferreira.net> + + * testsuite/d-demangle-expected: Add test case for function literals. + +2021-10-14 Lu?s Ferreira <contact@lsferreira.net> + + * testsuite/d-demangle-expected: Add test cases for simple special + mangles. + +2021-10-12 Lu?s Ferreira <contact@lsferreira.net> + + * d-demangle.c (dlang_parse_qualified): Remove redudant parenthesis + around lhs and rhs of assignments. + +2021-10-01 Lu?s Ferreira <contact@lsferreira.net> + + * testsuite/d-demangle-expected: Add missing format for new test + +2021-09-23 Lu?s Ferreira <contact@lsferreira.net> + + * d-demangle.c (dlang_Type): Validate MANGLED is nonnull. + * testsuite/d-demangle-expected: New test. + +2021-09-23 Lu?s Ferreira <contact@lsferreira.net> + + * d-demangle.c (dlang_symbol_backref): Ensure strlen of + string is less than length computed by dlang_number. + +2021-09-01 Iain Sandoe <iain@sandoe.co.uk> * configure: Regenerate. + * configure.ac: Do not search for sbrk on Darwin. + * xmalloc.c: Do not declare sbrk unless it has been found + by configure. + +2021-08-29 Iain Buclaw <ibuclaw@gdcproject.org> + + * d-demangle.c (dlang_identifier): Skip over fake parent manglings. + * testsuite/d-demangle-expected: Add tests. + +2021-08-29 Iain Buclaw <ibuclaw@gdcproject.org> + + * d-demangle.c (dlang_parse_arrayliteral): Add 'info' parameter. + (dlang_parse_assocarray): Likewise. + (dlang_parse_structlit): Likewise. + (dlang_value): Likewise. Handle function literal symbols. + (dlang_template_args): Pass 'info' to dlang_value. + * testsuite/d-demangle-expected: Add new test. + +2021-08-29 Iain Buclaw <ibuclaw@gdcproject.org> + + * d-demangle.c (dlang_attributes): Handle typeof(*null). + (dlang_type): Likewise. Demangle 'n' as typeof(null). + * testsuite/d-demangle-expected: Update tests. + +2021-08-23 Iain Sandoe <iain@sandoe.co.uk> + + * simple-object-mach-o.c (simple_object_mach_o_write_segment): + Cast the first argument to set_32 as needed. -2021-07-03 Nick Clifton <nickc@redhat.com> +2021-08-18 Iain Sandoe <iain@sandoe.co.uk> + * simple-object-mach-o.c (simple_object_mach_o_write_segment): + Arrange to swap the LTO index tables where needed. # Please enter the commit message for your changes. Lines starting
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out */po/*.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.
2021-12-07Support AT_FXRNG and AT_KPRELOAD on FreeBSD.John Baldwin1-0/+4
FreeBSD's kernel has recently added two new ELF auxiliary vector entries. AT_FXRNG points to a root seed version for the kernel's PRNG. Userland can use this to reseed a userland PRNG after the kernel's PRNG has reseeded. AT_KPRELOAD is the base address of a kernel-provided vDSO. This change displays the proper name and description of these entries in 'info auxv'. include/ChangeLog: * elf/common.h (AT_FREEBSD_FXRNG, AT_FREEBSD_KPRELOAD): Define.
2021-12-01Fix the fields in the x_n union inside the the x_file structure so that ↵Nick Clifton1-0/+6
pointers can be stored. PR 28630 * coff/internal.h (x_n): Use bfd_hostptr_t for the fields in this structure.
2021-11-26opcodes/riscv: add disassembler options support to libopcodesAndrew Burgess1-0/+5
In preparation for the next commit, which will add GDB support for RISC-V disassembler options, this commit restructures how the disassembler options are managed within libopcodes. The implementation provided here is based on this mailing list patch which was never committed: https://sourceware.org/pipermail/binutils/2021-January/114944.html which in turn took inspiration from the MIPS implementation of the same feature. The biggest changes from the original mailing list post are: 1. The GDB changes have been split into a separate patch, and 2. The `riscv_option_args_privspec` variable, which held the valid priv-spec values is now gone, instead we use the `riscv_priv_specs` array from bfd/cpu-riscv.c instead. Co-authored-by: Simon Cook <simon.cook@embecosm.com> include/ChangeLog: * dis-asm.h (disassembler_options_riscv): Declare. opcodes/ChangeLog: * riscv-dis.c (enum riscv_option_arg_t): New enum typedef. (riscv_options): New static global. (disassembler_options_riscv): New function. (print_riscv_disassembler_options): Rewrite to use disassembler_options_riscv.
2021-11-16readelf: Support SHT_RELR/DT_RELR for -rFangrui Song1-0/+6
The -r output for SHT_RELR looks like: Relocation section '.relr.dyn' at offset 0x530 contains 4 entries: 7 offsets 00000000000028c0 00000000000028c8 0000000000003ad0 0000000000003ad8 0000000000003ae0 0000000000003ae8 0000000000003af0 For --use-dynamic, the header looks like 'RELR' relocation section at offset 0x530 contains 32 bytes: include/ * elf/common.h (DT_ENCODING): Bump to 38. * elf/external.h (Elf32_External_Relr): New. (Elf64_External_Relr): New. binutils/ * readelf.c (enum relocation_type): New. (slurp_relr_relocs): New. (dump_relocations): Change is_rela to rel_type. Dump RELR. (dynamic_relocations): Add DT_RELR. (process_relocs): Check SHT_RELR and DT_RELR. (process_dynamic_section): Store into dynamic_info for DT_RELR/DT_RELRENT/DT_RELRSZ.
2021-09-07Revert: [AArch64] MTE corefile supportLuis Machado1-0/+9
bfd * elf.c (elfcore_make_memtag_note_section): New function. (elfcore_grok_note): Handle NT_MEMTAG note types. binutils* readelf.c (get_note_type): Handle NT_MEMTAG note types. include * elf/common.h (NT_MEMTAG): New constant. (NT_MEMTAG_TYPE_AARCH_MTE): New constant.
2021-07-03Add markers for 2.37 branchNick Clifton1-0/+4
2021-07-03Synchronize libiberty sources (and include/demangle.h) with GCC master versionNick Clifton1-0/+9
2021-07-01opcodes: constify aarch64_opcode_tablesMike Frysinger1-0/+4
This table is huge (~350k), so stop putting it into writable .data since it's only const data.
2021-07-01arm: don't treat XScale features as part of the FPU [PR 28031]Richard Earnshaw1-0/+5
Although the XScale and its iwMMX extensions are implemented in the Arm co-processor space, they are not considered to be part of the FPU specification. In particular, they cannot be enabled or disabled via a .fpu directive. It's therefore incorrect to strip these properties when a new .fpu directive is encountered. Note that the legacy Maverick co-processor is considered to be a FPU and it is possible to control this via the .fpu directive. include: PR gas/28031 * opcode/arm.h (FPU_ANY): Exclude XScale-related features.
2021-06-18elf: Add GNU_PROPERTY_UINT32_AND_XXX/GNU_PROPERTY_UINT32_OR_XXXH.J. Lu1-0/+7
Implement GNU_PROPERTY_UINT32_AND_XXX/GNU_PROPERTY_UINT32_OR_XXX: https://sourceware.org/pipermail/gnu-gabi/2021q1/000467.html 1. GNU_PROPERTY_UINT32_AND_LO..GNU_PROPERTY_UINT32_AND_HI #define GNU_PROPERTY_UINT32_AND_LO 0xb0000000 #define GNU_PROPERTY_UINT32_AND_HI 0xb0007fff A bit in the output pr_data field is set only if it is set in all relocatable input pr_data fields. If all bits in the the output pr_data field are zero, this property should be removed from output. If the bit is 1, all input relocatables have the feature. If the bit is 0 or the property is missing, the info is unknown. 2. GNU_PROPERTY_UINT32_OR_LO..GNU_PROPERTY_UINT32_OR_HI #define GNU_PROPERTY_UINT32_OR_LO 0xb0008000 #define GNU_PROPERTY_UINT32_OR_HI 0xb000ffff A bit in the output pr_data field is set if it is set in any relocatable input pr_data fields. If all bits in the the output pr_data field are zero, this property should be removed from output. If the bit is 1, some input relocatables have the feature. If the bit is 0 or the property is missing, the info is unknown. bfd/ * elf-properties.c (_bfd_elf_parse_gnu_properties): Handle GNU_PROPERTY_UINT32_AND_LO, GNU_PROPERTY_UINT32_AND_HI, GNU_PROPERTY_UINT32_OR_LO and GNU_PROPERTY_UINT32_OR_HI. (elf_merge_gnu_properties): Likewise. binutils/ * readelf.c (print_gnu_property_note): Handle GNU_PROPERTY_UINT32_AND_LO, GNU_PROPERTY_UINT32_AND_HI, GNU_PROPERTY_UINT32_OR_LO and GNU_PROPERTY_UINT32_OR_HI. include/ * elf/common.h (GNU_PROPERTY_UINT32_AND_LO): New. (GNU_PROPERTY_UINT32_AND_HI): Likewise. (GNU_PROPERTY_UINT32_OR_LO): Likewise. (GNU_PROPERTY_UINT32_OR_HI): Likewise. ld/ * testsuite/ld-elf/property-and-1.d: New file. * testsuite/ld-elf/property-and-1.s: Likewise. * testsuite/ld-elf/property-and-2.d: Likewise. * testsuite/ld-elf/property-and-2.s: Likewise. * testsuite/ld-elf/property-and-3.d: Likewise. * testsuite/ld-elf/property-and-3.s: Likewise. * testsuite/ld-elf/property-and-4.d: Likewise. * testsuite/ld-elf/property-and-empty.s: Likewise. * testsuite/ld-elf/property-or-1.d: Likewise. * testsuite/ld-elf/property-or-1.s: Likewise. * testsuite/ld-elf/property-or-2.d: Likewise. * testsuite/ld-elf/property-or-2.s: Likewise. * testsuite/ld-elf/property-or-3.d: Likewise. * testsuite/ld-elf/property-or-3.s: Likewise. * testsuite/ld-elf/property-or-4.d: Likewise. * testsuite/ld-elf/property-or-empty.s: Likewise.
2021-06-15Allow readelf to recognise GO buildid notes.Nick Clifton1-0/+4
binutils * readelf.c (get_note_type): Add support for NT_GO_BUILDID. include * elf/common.h (NT_GO_BUILDID): Define.
2021-06-02arc: Construct disassembler options dynamicallyShahab Vahedi1-0/+4
The idea of this change is simple: Populate a data structure, namely "disasm_option_and_arg_t" from "include/dis-asm.h", to encompass the disassembly options and their possible arguments. This will make it easier to manage or extend those options by adapting entries in a data structure, "arc_options". There will be lesser need to hard-code the options in the code itself. Moreover, ARC GDB will use this population function, "disassembler_options_arc ()", to enable the "set disassembler-option" for ARC targets. The gdb change will be in a separate patch though. The changes in this patch can be divided into: 1) Introduction of "disassembler_options_arc ()" that will return a "disasm_option_and_arg_t" structure representing the disassembly options and their likely arguments. 2) New data type "arc_options_arg_t" and new data "arc_options". These are the internals for keeping track of options and arguments entries that can easily be extended. 3) To print the options, the "print_arc_disassembler_options ()" has been adjusted to use this dynamically built structure instead of having them hard-coded inside. To see this in effect, one can look into the output of: $ ./binutils/objdump --help ... The following ARC specific disassembler options are... ... include/ChangeLog: * dis-asm.h (disassembler_options_arc): New prototype. opcodes/ChangeLog: * arc-dis.c (arc_option_arg_t): New enumeration. (arc_options): New variable. (disassembler_options_arc): New function. (print_arc_disassembler_options): Reimplement in terms of "disassembler_options_arc".
2021-05-29MIPS/opcodes: Properly handle ISA exclusionMaciej W. Rozycki1-0/+6
Remove the hack used for MIPSr6 ISA exclusion from `cpu_is_member' and handle the exclusion for any ISA levels properly in `opcode_is_member'. Flatten the structure of the `if' statements there. No functional change for the existing opcode tables. include/ * opcode/mips.h (cpu_is_member): Remove code for MIPSr6 ISA exclusion. (opcode_is_member): Handle ISA level exclusion.
2021-05-29MIPS/opcodes: Factor out ISA matching against flagsMaciej W. Rozycki1-0/+6
In preparation for the next change factor out code for ISA matching against instruction flags used in MIPS opcode tables, similarly to how CPU matching is already done. No functional change, though for clarity split the single `if' statement into multiple ones and use temporaries rather than repeated expressions. include/ * opcode/mips.h (isa_is_member): New inline function, factored out from... (opcode_is_member): ... here.
2021-05-29MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki1-0/+6
The CP0 control register set has never been defined, however encodings for the CFC0 and CTC0 instructions remained available for implementers up until the MIPS32 ISA declared them invalid and causing the Reserved Instruction exception[1]. Therefore we handle them for both assembly and disassembly, however in the latter case the names of CP0 registers from the regular set are incorrectly printed if named registers are requested. This is because we do not define separate operand classes for coprocessor regular and control registers respectively, which means the disassembler has no way to tell the two cases apart. Consequently nonsensical disassembly is produced like: cfc0 v0,c0_random Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0 instructions[2] although it failed to document them in the relevant opcode table until MIPSr6 only. Correct the issue then by defining a new register class, OP_REG_CONTROL, and corresponding operand codes, `g' and `y' for the two positions in the machine instruction a control register operand can take. Adjust the test cases affected accordingly. While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries with each other so that they come in the alphabetical order. References: [1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of rs Field", p. 242 [2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of Instructions", pp. 195, 216 include/ * opcode/mips.h: Document `g' and `y' operand codes. (mips_reg_operand_type): Add OP_REG_CONTROL enumeration constant. gas/ * tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case. (macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G' operand code. opcodes/ * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register handling code over to... <OP_REG_CONTROL>: ... this new case. * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases. (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2", "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries replacing the `G' operand code with `g'. Update "cftc1" and "cftc2" entries replacing the `E' operand code with `y'. * micromips-opc.c (decode_micromips_operand) <'g'>: New case. (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2" entries replacing the `G' operand code with `g'. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0 operand disassembly. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
2021-05-29MIPS/opcodes: Free up redundant `g' operand codeMaciej W. Rozycki1-0/+5
In the operand handling rewrite made for the MIPS disassembler with commit ab90248154ba ("Add structures to describe MIPS operands"), <https://sourceware.org/ml/binutils/2013-07/msg00135.html>, the `g' operand code has become redundant for the regular MIPS instruction set by duplicating the OP_REG_COPRO semantics of the `G' operand code. Later commit 351cdf24d223 ("Implement O32 FPXX, FP64 and FP64A ABI extensions") converted the CTTC1 instruction from the `g' to the `G' operand code, but still left a few instructions behind. Convert the three remaining instructions still using the `g' code then, namely: CTTC2, MTTC2 and MTTHC2, and remove all traces of the operand code, freeing it up for other use. opcodes/ * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2", and "mtthc2" to using the `G' rather than `g' operand code for the coprocessor control register referred. include/ * opcode/mips.h: Complement change made to opcodes and remove references to the `g' regular MIPS ISA operand code.
2021-05-28x86: Restore PC16 relocation overflow checkH.J. Lu1-0/+5
The x86-64 psABI has --- A program or object file using R_X86_64_8, R_X86_64_16, R_X86_64_PC16 or R_X86_64_PC8 relocations is not conformant to this ABI, these relocations are only added for documentation purposes. --- Since x86 PC16 relocations have been used for 16-bit programs in an ELF32 or ELF64 container, PC16 relocation should wrap-around in 16-bit address space. Revert commit a7664973b24a242cd9ea17deb5eaf503065fc0bd Author: Jan Beulich <jbeulich@suse.com> Date: Mon Apr 26 10:41:35 2021 +0200 x86: correct overflow checking for 16-bit PC-relative relocs and xfail the related tests. Also revert commit 50c95a739c91ae70cf8481936611aa1f5397a384 Author: H.J. Lu <hjl.tools@gmail.com> Date: Wed May 26 12:13:13 2021 -0700 x86: Propery check PC16 reloc overflow in 16-bit mode instructions while keeping PR ld/27905 tests for PC16 relocation in 16-bit programs. bfd/ PR ld/27905 * elf32-i386.c: Don't include "libiberty.h". (elf_howto_table): Revert commits a7664973b24 and 50c95a739c9. (elf_i386_rtype_to_howto): Revert commit 50c95a739c9. (elf_i386_info_to_howto_rel): Likewise. (elf_i386_tls_transition): Likewise. (elf_i386_relocate_section): Likewise. * elf64-x86-64.c (x86_64_elf_howto_table): Revert commits a7664973b24 and 50c95a739c9. (elf_x86_64_rtype_to_howto): Revert commit 50c95a739c9. * elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Likewise. * elfxx-x86.h (elf_x86_obj_tdata): Likewise. (elf_x86_has_code16): Likewise. binutils/ PR ld/27905 * readelf.c (decode_x86_feature_2): Revert commit 50c95a739c9. gas/ PR ld/27905 * config/tc-i386.c (set_code_flag): Revert commit 50c95a739c9. (set_16bit_gcc_code_flag): Likewise. (x86_cleanup): Likewise. * testsuite/gas/i386/code16-2.d: Updated. * testsuite/gas/i386/x86-64-code16-2.d: Likewise. include/ PR ld/27905 * elf/common.h (GNU_PROPERTY_X86_FEATURE_2_CODE16): Removed. ld/ PR ld/27905 * testsuite/ld-i386/pcrel16-2.d: xfail. * testsuite/ld-x86-64/pcrel16-2.d: Likewise.
2021-05-26x86: Propery check PC16 reloc overflow in 16-bit mode instructionsH.J. Lu1-0/+5
commit a7664973b24a242cd9ea17deb5eaf503065fc0bd Author: Jan Beulich <jbeulich@suse.com> Date: Mon Apr 26 10:41:35 2021 +0200 x86: correct overflow checking for 16-bit PC-relative relocs caused linker failure when building 16-bit program in a 32-bit ELF container. Update GNU_PROPERTY_X86_FEATURE_2_USED with #define GNU_PROPERTY_X86_FEATURE_2_CODE16 (1U << 12) to indicate that 16-bit mode instructions are used in the input object: https://groups.google.com/g/x86-64-abi/c/UvvXWeHIGMA to indicate that 16-bit mode instructions are used in the object to allow linker to properly perform relocation overflow check for 16-bit PC-relative relocations in 16-bit mode instructions. 1. Update x86 assembler to always generate the GNU property note with GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF object. 2. Update i386 and x86-64 linkers to use 16-bit PC16 relocations if input object is marked with GNU_PROPERTY_X86_FEATURE_2_CODE16. bfd/ PR ld/27905 * elf32-i386.c: Include "libiberty.h". (elf_howto_table): Add 16-bit R_386_PC16 entry. (elf_i386_rtype_to_howto): Add a BFD argument. Use 16-bit R_386_PC16 if input has 16-bit mode instructions. (elf_i386_info_to_howto_rel): Update elf_i386_rtype_to_howto call. (elf_i386_tls_transition): Likewise. (elf_i386_relocate_section): Likewise. * elf64-x86-64.c (x86_64_elf_howto_table): Add 16-bit R_X86_64_PC16 entry. (elf_x86_64_rtype_to_howto): Use 16-bit R_X86_64_PC16 if input has 16-bit mode instructions. * elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Set elf_x86_has_code16 if relocatable input is marked with GNU_PROPERTY_X86_FEATURE_2_CODE16. * elfxx-x86.h (elf_x86_obj_tdata): Add has_code16. (elf_x86_has_code16): New. binutils/ PR ld/27905 * readelf.c (decode_x86_feature_2): Support GNU_PROPERTY_X86_FEATURE_2_CODE16. gas/ PR ld/27905 * config/tc-i386.c (set_code_flag): Update x86_feature_2_used with GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF object. (set_16bit_gcc_code_flag): Likewise. (x86_cleanup): Always generate the GNU property note if x86_feature_2_used isn't 0. * testsuite/gas/i386/code16-2.d: New file. * testsuite/gas/i386/code16-2.s: Likewise. * testsuite/gas/i386/x86-64-code16-2.d: Likewise. * testsuite/gas/i386/i386.exp: Run code16-2 and x86-64-code16-2. include/ PR ld/27905 * elf/common.h (GNU_PROPERTY_X86_FEATURE_2_CODE16): New. ld/ PR ld/27905 * testsuite/ld-i386/code16.d: New file. * testsuite/ld-i386/code16.t: Likewise. * testsuite/ld-x86-64/code16.d: Likewise. * testsuite/ld-x86-64/code16.t: Likewise. * testsuite/ld-i386/i386.exp: Run code16. * testsuite/ld-x86-64/x86-64.exp: Likewise.
2021-05-23elf: Use official name LoongArch for EM_LOONGARCH.Chenghua Xu1-0/+5
The official name for Loongson Architecture is LoongArch, it is better to use LoongArch instead of Loongson Loongarch for EM_LOONGARCH to avoid confusion and keep consistent with the various of software in the future. The official documentation in Chinese: http://www.loongson.cn/uploadfile/cpu/LoongArch.pdf The translated version in English: https://loongson.github.io/LoongArch-Documentation/ binutils/ * readelf.c (get_machine_name): Change Loongson Loongarch to LoongArch. include/ * elf/common.h (EM_LOONGARCH): Change Loongson Loongarch to LoongArch.
2021-05-21[AArch64] MTE corefile supportLuis Machado1-0/+5
bfd * elf.c (elfcore_make_memtag_note_section): New function. (elfcore_grok_note): Handle NT_MEMTAG note types. binutils* readelf.c (get_note_type): Handle NT_MEMTAG note types. include * elf/common.h (NT_MEMTAG): New constant. (NT_MEMTAG_TYPE_AARCH_MTE): New constant.
2021-05-07Fix .dwsect generation for XCOFF. Handle .function generated with DWARF on ↵Cl?ment Chigot1-0/+6
XCOFF. gas * config/tc-ppc.c (ppc_function): Update comment for fifth argument. (ppc_frob_symbol): Remove ppc_last_function check. Make sure coff_last_function is reset. Correctly set fsize when not provided in .function. * testsuite/gas/ppc/aix.exp: New tests. * testsuite/gas/ppc/xcoff-function-1-32.d: New test. * testsuite/gas/ppc/xcoff-function-1-64.d: New test. * testsuite/gas/ppc/xcoff-function-1.s: New test. bfd * coff-rs6000.c (xcoff_dwsect_names): Add new DWARF sections. * coffgen.c (coff_pointerize_aux): Handle C_DWARF. (coff_print_symbol): Likewise. * libxcoff.h (XCOFF_DWSECT_NBR_NAMES): Update. gas * config/obj-coff.c (coff_frob_symbol): Don't skip C_DWARF. (coff_adjust_section_syms): Use corrext auxent for C_DWARF. (coff_frob_section): Likewise. * config/obj-coff.h (SA_GET_SECT_SCNLEN, SA_GET_SECT_NRELOC, SA_SET_SECT_SCNLEN, SA_SET_SECT_NRELOC) New defines. (SET_SECTION_RELOCS): Adjust for C_DWARF. * config/tc-ppc.c (ppc_frob_symbol): Don't skip C_DWARF. (ppc_adjust_symtab): Reorder C_DWARF symbols. * testsuite/gas/ppc/aix.exp: New tests. * testsuite/gas/ppc/xcoff-dwsect-2-32.d: New test. * testsuite/gas/ppc/xcoff-dwsect-2-64.d: New test. * testsuite/gas/ppc/xcoff-dwsect-2.s: New test. include * coff/internal.h (C_DWARF): New define. * coff/xcoff.h (SSUBTYP_DWLOC, SSUBTYP_DWFRAME, SSUBTYP_DWMAC): New defines.
2021-05-06or1k: Implement relocation R_OR1K_GOT_AHI16 for gotha()Stafford Horne1-0/+5
The gotha() relocation mnemonic will be outputted by OpenRISC GCC when using the -mcmodel=large option. This relocation is used along with got() to generate 32-bit GOT offsets. This increases the previous GOT offset limit from the previous 16-bit (64K) limit. This is needed on large binaries where the GOT grows larger than 64k. bfd/ChangeLog: PR 21464 * bfd-in2.h: Add BFD_RELOC_OR1K_GOT_AHI16 relocation. * elf32-or1k.c (or1k_elf_howto_table, or1k_reloc_map): Likewise. (or1k_final_link_relocate, or1k_elf_relocate_section, or1k_elf_check_relocs): Likewise. * libbfd.h (bfd_reloc_code_real_names): Likewise. * reloc.c: Likewise. cpu/ChangeLog: PR 21464 * or1k.opc (or1k_imm16_relocs, parse_reloc): Define parse logic for gotha() relocation. include/ChangeLog: PR 21464 * elf/or1k.h (elf_or1k_reloc_type): Define R_OR1K_GOT_AHI16 number. opcodes/ChangeLog: PR 21464 * or1k-asm.c: Regenerate. gas/ChangeLog: PR 21464 * testsuite/gas/or1k/reloc-1.s: Add test for new relocation. * testsuite/gas/or1k/reloc-1.d: Add test result for new relocation. Cc: Giulio Benetti <giulio.benetti@benettiengineering.com> fixup reloc, add tests
2021-05-06libctf, include: support an alternative encoding for nonrepresentable typesNick Alcock1-0/+6
Before now, types that could not be encoded in CTF were represented as references to type ID 0, which does not itself appear in the dictionary. This choice is annoying in several ways, principally that it forces generators and consumers of CTF to grow special cases for types that are referenced in valid dicts but don't appear. Allow an alternative representation (which will become the only representation in format v4) whereby nonrepresentable types are encoded as actual types with kind CTF_K_UNKNOWN (an already-existing kind theoretically but not in practice used for padding, with value 0). This is backward-compatible, because CTF_K_UNKNOWN was not used anywhere before now: it was used in old-format function symtypetabs, but these were never emitted by any compiler and the code to handle them in libctf likely never worked and was removed last year, in favour of new-format symtypetabs that contain only type IDs, not type kinds. In order to link this type, we need an API addition to let us add types of unknown kind to the dict: we let them optionally have names so that GCC can emit many different unknown types and those types with identical names will be deduplicated together. There are also small tweaks to the deduplicator to actually dedup such types, to let opening of dicts with unknown types with names work, to return the ECTF_NONREPRESENTABLE error on resolution of such types (like ID 0), and to print their names as something useful but not a valid C identifier, mostly for the sake of the dumper. Tests added in the next commit. include/ChangeLog 2021-05-06 Nick Alcock <nick.alcock@oracle.com> * ctf.h (CTF_K_UNKNOWN): Document that it can be used for nonrepresentable types, not just padding. * ctf-api.h (ctf_add_unknown): New. libctf/ChangeLog 2021-05-06 Nick Alcock <nick.alcock@oracle.com> * ctf-open.c (init_types): Unknown types may have names. * ctf-types.c (ctf_type_resolve): CTF_K_UNKNOWN is as non-representable as type ID 0. (ctf_type_aname): Print unknown types. * ctf-dedup.c (ctf_dedup_hash_type): Do not early-exit for CTF_K_UNKNOWN types: they have real hash values now. (ctf_dedup_rwalk_one_output_mapping): Treat CTF_K_UNKNOWN types like other types with no referents: call the callback and do not skip them. (ctf_dedup_emit_type): Emit via... * ctf-create.c (ctf_add_unknown): ... this new function. * libctf.ver (LIBCTF_1.2): Add it.
2021-04-22Harmonize and improve auxiliary entries support for XCOFFCl?ment Chigot1-0/+9
bfd/ChangeLog: * coff-rs6000.c (_bfd_xcoff_swap_aux_in): Add errors for unsupported storage class or auxialiry entries. Improve and adapt to new aux structures. Add C_DWARF support. (_bfd_xcoff_swap_aux_out): Likewise. * coff64-rs6000.c (_bfd_xcoff64_swap_aux_in): Likewise. (_bfd_xcoff64_swap_aux_out): Likewise. binutils/ChangeLog: * od-xcoff.c (dump_xcoff32_symbols): Adapt to new aux structures. include/ChangeLog: * coff/internal.h (union internal_auxent): Add x_sect structure. * coff/rs6000.h (union external_auxent): Rework to match official documentation. * coff/rs6k64.h (union external_auxent): Likewise. (_AUX_SECT): New define.
2021-04-21Extend the description of PE header flags.Eli Zaretskii1-0/+6
PR 27760 include * coff/pe.h (IMAGE_DLLCHARACTERISTICS_APPCONTAINER): Define. (IMAGE_DLLCHARACTERISTICS_GUARD_CF): Define. bfd * peXXigen.c (_bfd_XX_print_private_bfd_data_common): Add display of IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP, IMAGE_FILE_NET_RUN_FROM_SWAP and IMAGE_FILE_UP_SYSTEM_ONLY flags. Decode the contents of the DllCharacteristics field.
2021-04-16PR27567, Linking PE files adds alignment section flags to executablesAlan Modra1-0/+12
So don't set those flags for an executable. In the patch I also test DYNAMIC even though the PE bfd code doesn't appear to set it for dlls. I figure it doesn't hurt to include that flag too. PR 27567 bfd/ * coffcode.h (styp_to_sec_flags): Use an unsigned long styp_flags. (coff_write_object_contents): Pass bfd to COFF_ENCODE_ALIGNMENT, ignore alignment checks when return is false. Formatting. include/ * coff/internal.h (struct internal_scnhdr): Make s_flags unsigned long. * coff/pe.h (COFF_ENCODE_ALIGNMENT): Don't set align flags for an executable and return false. Do so for a relocatable object and evaluate to true. * coff/ti.h (COFF_ENCODE_ALIGNMENT): Add bfd arg and evaluate to true. (COFF_DECODE_ALIGNMENT): Formatting. * coff/z80.h (COFF_ENCODE_ALIGNMENT): Similarly. (COFF_DECODE_ALIGNMENT): Similarly.
2021-04-09PowerPC disassembly of pcrel referencesAlan Modra1-0/+4
This adds some annotation to Power10 pcrel instructions, displaying the target address (ie. pc + D34 field) plus a symbol if there is one at exactly that target address. pld from the .got or .plt will also look up the entry and display it, symbolically if there is a dynamic relocation on the entry. include/ * dis-asm.h (struct disassemble_info): Add dynrelbuf and dynrelcount. binutils/ * objdump.c (struct objdump_disasm_info): Delete dynrelbuf and dynrelcount. (find_symbol_for_address): Adjust for dynrelbuf and dynrelcount move. (disassemble_section, disassemble_data): Likewise. opcodes/ * ppc-dis.c (struct dis_private): Add "special". (POWERPC_DIALECT): Delete. Replace uses with.. (private_data): ..this. New inline function. (disassemble_init_powerpc): Init "special" names. (skip_optional_operands): Add is_pcrel arg, set when detecting R field of prefix instructions. (bsearch_reloc, print_got_plt): New functions. (print_insn_powerpc): For pcrel instructions, print target address and symbol if known, and decode plt and got loads too. gas/ * testsuite/gas/ppc/prefix-pcrel.d: Update expected output. * testsuite/gas/ppc/prefix-reloc.d: Likewise. * gas/testsuite/gas/ppc/vsx_32byte.d: Likewise. ld/ * testsuite/ld-powerpc/inlinepcrel-1.d: Update expected output. * testsuite/ld-powerpc/inlinepcrel-2.d: Likewise. * testsuite/ld-powerpc/notoc2.d: Likewise. * testsuite/ld-powerpc/notoc3.d: Likewise. * testsuite/ld-powerpc/pcrelopt.d: Likewise. * testsuite/ld-powerpc/startstop.d: Likewise. * testsuite/ld-powerpc/tlsget.d: Likewise. * testsuite/ld-powerpc/tlsget2.d: Likewise. * testsuite/ld-powerpc/tlsld.d: Likewise. * testsuite/ld-powerpc/weak1.d: Likewise. * testsuite/ld-powerpc/weak1so.d: Likewise.
2021-04-06Return symbol from symbol_at_address_funcAlan Modra1-0/+5
include/ * dis-asm.h (struct disassemble_info <symbol_at_address_func>): Return asymbol*. binutils/ * objdump.c (objdump_symbol_at_address): Return asymbol*. opcodes/ * dis-buf.c (generic_symbol_at_address): Return symbol* NULL. * s12z-dis.c (decode_possible_symbol): Use symbol returned from symbol_at_address_func.
2021-04-01Remove strneq macro and use startswith.Martin Liska1-0/+4
bfd/ChangeLog: * ecoff.c (strneq): Remove strneq and use startswith. (_bfd_ecoff_slurp_armap): Likewise. binutils/ChangeLog: * elfcomm.h (strneq): Remove strneq and use startswith. * readelf.c (ia64_process_unwind): Likewise. (process_note): Likewise. gas/ChangeLog: * config/obj-coff.c (strneq): Remove strneq and use startswith. (weak_is_altname): Likewise. (obj_coff_section): Likewise. * config/tc-cr16.c (process_label_constant): Likewise. * config/tc-crx.c (strneq): Likewise. include/ChangeLog: * opcode/cr16.h (strneq): Remove strneq and use startswith. ld/ChangeLog: * ldbuildid.c (strneq): Remove strneq and use startswith. (validate_build_id_style): Likewise. (compute_build_id_size): Likewise. opcodes/ChangeLog: * arm-dis.c (strneq): Remove strneq and use startswith. * cr16-dis.c (print_insn_cr16): Likewise. * score-dis.c (streq): Likewise. (strneq): Likewise. * score7-dis.c (strneq): Likewise.
2021-03-31Use bool in includeAlan Modra1-0/+14
* bfdlink.h: Replace bfd_boolean with bool throughout. * coff/ecoff.h: Likewise. * coff/xcoff.h: Likewise. * dis-asm.h: Likewise. * elf/mmix.h: Likewise. * elf/xtensa.h: Likewise. * opcode/aarch64.h: Likewise, and FALSE with false, TRUE with true. * opcode/arc.h: Likewise. * opcode/mips.h: Likewise. * opcode/tic6x-opcode-table.h: Likewise. * opcode/tic6x.h: Likewise.
2021-03-31Remove bfd_stdint.hAlan Modra1-0/+9
If we require C99 for binutils then stdint.h is available. bfd/ * .gitignore: Delete bfd_stdint.h entry. * Makefile.am (bfdinclude_HEADERS): Delete bfd_stdint.h. (BUILD_HFILES, LOCAL_H_DEPS): Likewise. * bfd-in.h: Include stdint.h in place of bfd_stdint.h. * configure.ac: Don't invoke GCC_HEADER_STDINT. * configure.com: Don't create bfd_stdint.h. * Makefile.in: Regenerate. * aclocal.m4: Regenerate. * bfd-in2.h: Regenerate. * config.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate. binutils/ * coffdump.c: Include stdint.h in place of bfd_stdint.h. * dwarf.c: Likewise. gas/ * config/tc-aarch64.c: Include stdint.h in place of bfd_stdint.h. * config/tc-crx.c: Likewise. * config/tc-nds32.h: Likewise. include/ * cgen/basic-modes.h: Include stdint.h in place of bfd_stdint.h. * elf/nfp.h: Likewise. * opcode/aarch64.h: Likewise. * opcode/cgen.h: Likewise. * opcode/nfp.h: Likewise. * opcode/ppc.h: Likewise. ld/ * elf-hints-local.h: Include stdint.h in place of bfd_stdint.h. * emultempl/nds32elf.em: Likewise. * testsuite/ld-elf/mbind2b.c: Likewise. * testsuite/ld-elf/pr18718.c: Likewise. * testsuite/ld-elf/pr18720a.c: Likewise. * testsuite/ld-elf/pr25749-1.c: Likewise. * testsuite/ld-elf/pr25749-1a.c: Likewise. * testsuite/ld-elf/pr25749-1b.c: Likewise. * testsuite/ld-elf/pr25749-1c.c: Likewise. * testsuite/ld-elf/pr25749-1d.c: Likewise. * testsuite/ld-elf/pr25749-2.c: Likewise. * testsuite/ld-elf/pr25754-1a.c: Likewise. * testsuite/ld-elf/pr25754-2a.c: Likewise. * testsuite/ld-elf/pr25754-3a.c: Likewise. * testsuite/ld-elf/pr25754-4a.c: Likewise. * testsuite/ld-elf/pr25754-5a.c: Likewise. * testsuite/ld-elf/pr25754-6a.c: Likewise. opcodes/ * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h. * aarch64-dis.h: Likewise. * aarch64-opc.c: Likewise. * avr-dis.c: Likewise. * csky-dis.c: Likewise. * nds32-asm.c: Likewise. * nds32-dis.c: Likewise. * nfp-dis.c: Likewise. * riscv-dis.c: Likewise. * s12z-dis.c: Likewise. * wasm32-dis.c: Likewise.
2021-03-29TRUE/FALSE simplificationAlan Modra1-0/+6
There is really no need to write code like "foo != 0 ? TRUE : FALSE" unless we had stupidly defined FALSE as something other than 0 or TRUE as something other than 1. The simpler "foo != 0" does just as well. Similarly "(condition == TRUE)" or "(condition == FALSE) can be simplified to "(condition)" and "(!condition)" respectively. I'll note that there is reason to use "integer_expression != 0" when assigning a bfd_boolean rather than the simpler "integer_expression", if you expect the variable to have 0 or 1 value. It's probably even a good idea to not rely on implicit conversion if bfd_boolean were _Bool. bfd/ * aoutx.h (aout_link_write_symbols): Don't cast boolean expression to bfd_boolean. * elf32-or1k.c (or1k_set_got_and_rela_sizes): Dont compare booleans against FALSE. * elf32-arc.c (name_for_global_symbol): Don't compare boolean to TRUE. (is_reloc_PC_relative): Don't use "boolean_condition ? TRUE : FALSE". (is_reloc_SDA_relative, is_reloc_for_GOT): Likewise. (is_reloc_for_PLT, is_reloc_for_TLS): Likewise. * elf32-arm.c (stm32l4xx_need_create_replacing_stub): Likewise. * elf32-nds32.c (insert_nds32_elf_blank): Likewise. * elf32-rx.c (rx_set_section_contents): Likewise. * elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Likewise. * elfxx-mips.c (_bfd_mips_elf_ignore_undef_symbol): Likewise. * mach-o.c (bfd_mach_o_read_command): Likewise. * targets.c (bfd_get_target_info): Likewise. binutils/ * dlltool.c (main): Don't use "boolean_condition ? TRUE : FALSE". * dwarf.c (read_and_display_attr_value): Likewise. (display_debug_str_offsets): Likewise. * objdump.c (dump_bfd): Likewise. * readelf.c (dump_section_as_strings): Likewise. (dump_section_as_bytes): Likewise. gas/ * atof-generic.c (FALSE, TRUE): Don't define. * config/obj-elf.h (FALSE, TRUE): Don't define. * config/obj-som.h (FALSE, TRUE): Don't define. * config/tc-hppa.h (FALSE, TRUE): Don't define. * config/tc-pdp11.c (FALSE, TRUE): Don't define. * config/tc-iq2000.h (obj_fix_adjustable): Delete. * config/tc-m32r.h (TC_FIX_ADJUSTABLE): Delete. * config/tc-mt.h (obj_fix_adjustable): Delete. * config/tc-nds32.h (TC_FIX_ADJUSTABLE): Delete. * config/tc-arc.c (parse_opcode_flags): Simplify boolean expression. (relaxable_flag, relaxable_operand, assemble_insn): Likewise. (tokenize_extregister): Likewise. * config/tc-csky.c (parse_opcode, get_operand_value): Likewise. (parse_operands_op, parse_operands, md_assemble): Likewise. * config/tc-d10v.c (build_insn): Likewise. * config/tc-score.c (s3_gen_insn_frag): Likewise. * config/tc-score7.c (s7_gen_insn_frag, s7_relax_frag): Likewise. * config/tc-tic6x.c (tic6x_update_features, md_assemble): Likewise. * config/tc-z80.c (emit_byte): Likewise. include/ * opcode/aarch64.h (alias_opcode_p): Simplify boolean expression. (opcode_has_alias, pseudo_opcode_p, optional_operand_p): Likewise. (opcode_has_special_coder): Likewise. ld/ * emultempl/aix.em (gld${EMULATION_NAME}_before_allocation): Simplify boolean expression. * lexsup.c (parse_args): Likewise. * pe-dll.c (pe_dll_id_target): Likewise. opcodes/ * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression. (fp_qualifier_p, get_data_pattern): Likewise. (aarch64_get_operand_modifier_from_value): Likewise. (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise. (operand_variant_qualifier_p): Likewise. (qualifier_value_in_range_constraint_p): Likewise. (aarch64_get_qualifier_esize): Likewise. (aarch64_get_qualifier_nelem): Likewise. (aarch64_get_qualifier_standard_value): Likewise. (get_lower_bound, get_upper_bound): Likewise. (aarch64_find_best_match, match_operands_qualifier): Likewise. (aarch64_print_operand): Likewise. * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise. (operand_need_sign_extension, operand_need_shift_by_two): Likewise. (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise. * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise. * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise. (print_insn_tic6x): Likewise.
2021-03-29opcodes int vs bfd_boolean fixesAlan Modra1-0/+4
cpu/ * frv.opc (frv_is_branch_major, frv_is_float_major), (frv_is_media_major, frv_is_branch_insn, frv_is_float_insn), (frv_is_media_insn, spr_valid): Correct prototypes. include/ * opcode/aarch64.h (aarch64_opcode_encode): Correct prototype. opcodes/ * arc-dis.c (extract_operand_value): Correct NULL cast. * frv-opc.h: Regenerate.
2021-03-25include: always do unsigned left-shift in CTF_SET_STIDNick Alcock1-0/+7
This turns into a signed left shift by 31 bits, otherwise. This is an offset and is always treated as unsigned in any case, so add an appropriate cast. include/ChangeLog 2021-03-25 Nick Alcock <nick.alcock@oracle.com> PR libctf/27628 * ctf-api.h: Fix some indentation. (CTF_SET_STID): Always do an unsigned shift, even if STID is signed.
2021-03-19elf: Rename EM_INTEL205 to EM_INTELGTH.J. Lu1-0/+5
Rename EM_INTEL205 to EM_INTELGT for Intel Graphics Technology. binutils/ * readelf.c (get_machine_name): Add EM_INTELGT. include/ * elf/common.h (EM_INTEL205): Renamed to ... (EM_INTELGT): This.
2021-03-16Fix a potential buffer overrun qwhen writing out PE aux entries.Nick Clifton1-0/+5
* peXXigen.c (_bfd_XXi_swap_aux_out): Avoid potential buffer overrun by using sizeof of the destination x_fname field as the limit for a memcpy. * coff/internal.h (struct internal_auxent): Fix a couple of typos in comment describing the x_fname field.
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