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2019-05-28libctf: mmappable archivesNick Alcock1-0/+14
2019-05-28libctf: openingNick Alcock1-0/+13
2019-05-28libctf: creation functionsNick Alcock1-0/+47
2019-05-28libctf: error handlingNick Alcock1-0/+5
2019-05-28libctf: lowest-level memory allocation and debug-dumping wrappersNick Alcock1-0/+5
2019-05-28include: new header ctf-api.hNick Alcock1-0/+4
2019-05-28include: new header ctf.h: file format descriptionNick Alcock1-0/+4
2019-05-24aarch64: add STO_AARCH64_VARIANT_PCS and DT_AARCH64_VARIANT_PCSSzabolcs Nagy1-0/+5
2019-05-24PowerPC relocations for prefix insnsAlan Modra1-0/+12
2019-05-24PowerPC add initial -mfuture instruction supportPeter Bergner1-0/+8
2019-05-23include: add elf/bpf.hJose E. Marchesi1-0/+4
2019-05-16[PATCH 1/57][Arm][GAS]: Add support for +mve and +mve.fpAndre Vieira1-0/+5
2019-05-09[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson1-0/+5
2019-05-09[binutils][aarch64] New sve_size_tsz_bhs iclass.Matthew Malcomson1-0/+5
2019-05-09[binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson1-0/+4
2019-05-09[binutils][aarch64] New sve_shift_tsz_bhsd iclass.Matthew Malcomson1-0/+5
2019-05-09[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson1-0/+6
2019-05-09[binutils][aarch64] New sve_size_013 iclass.Matthew Malcomson1-0/+4
2019-05-09[binutils][aarch64] New sve_size_bh iclass.Matthew Malcomson1-0/+4
2019-05-09[binutils][aarch64] New sve_size_sd2 iclass.Matthew Malcomson1-0/+4
2019-05-09[binutils][aarch64] New SVE_ADDR_ZX operand.Matthew Malcomson1-0/+4
2019-05-09[binutils][aarch64] New SVE_Zm3_11_INDEX operand.Matthew Malcomson1-0/+4
2019-05-09[binutils][aarch64] New iclass sve_size_hsd2.Matthew Malcomson1-0/+4
2019-05-09[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.Matthew Malcomson1-0/+4
2019-05-09[binutils][aarch64] SVE2 feature extension flags.Matthew Malcomson1-0/+7
2019-05-06Add load-link, store-conditional paired EVA instructionsFaraz Shahbazker1-0/+6
2019-05-01[BINUTILS, AArch64] Enable Transactional Memory ExtensionSudakshina Das1-0/+5
2019-04-26[MIPS] Add load-link, store-conditional paired instructionsAndrew Bennett1-0/+6
2019-04-25MIPS/include: opcode/mips.h: Update stale comment for CODE20 operandMaciej W. Rozycki1-0/+4
2019-04-15[binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_...Andre Vieira1-0/+4
2019-04-15[binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18Andre Vieira1-0/+4
2019-04-15[binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM...Andre Vieira1-0/+4
2019-04-15[binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLIAndre Vieira1-0/+9
2019-04-11[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructionsSudakshina Das1-0/+4
2019-04-08x86: Define GNU_PROPERTY_X86_ISA_1_AVX512_BF16H.J. Lu1-0/+4
2019-04-07Merge libiberty from gccAlan Modra1-0/+8
2019-04-06x86: Move x86-specific linker options to elf_linker_x86_paramsH.J. Lu1-0/+4
2019-04-01[GAS, Arm] CLI with architecture sensitive extensionsAndre Vieira1-0/+11
2019-03-28PR24390, Don't decode mtfsb field as a cr fieldAlan Modra1-0/+5
2019-03-25AArch64: Fix disassembler bug with out-of-order sectionsTamar Christina1-0/+4
2019-03-13[BFD, LD, AArch64, 3/3] Add --pac-plt to enable PLTs protected with PAC.Sudakshina Das1-0/+4
2019-03-13[BFD, LD, AArch64, 2/3] Add --force-bti to enable BTI and to select BTI enabl...Sudakshina Das1-0/+5
2019-03-13[BFD, LD, AArch64, 1/3] Add support for GNU PROPERTIES in AArch64 for BTI and...Sudakshina Das1-0/+6
2019-02-20AArch64: Add pauth core file sectionAlan Hayward1-0/+4
2019-02-15Use the correct name for various MACH-O based operating systems in comments.Saagar Jha1-0/+4
2019-02-12Fix splay tree KEY leak detected in GDB test gdb.base/macscp.exptromey1-0/+5
2019-01-31S/390: Implement instruction set extensionsAndreas Krebbel1-0/+5
2019-01-25AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte...Sudi Das1-0/+7
2019-01-22Include coff/sym.h from coff/ecoff.hTom Tromey1-0/+4
2019-01-19Add markers for 2.32 branch to NEWS and ChangeLog files.Nick Clifton1-0/+4