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AgeCommit message (Expand)AuthorFilesLines
2017-04-04Support ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXXH.J. Lu1-0/+7
2017-04-04RISC-V: Resurrect GP-relative disassembly hintsPalmer Dabbelt1-0/+4
2017-03-31RISC-V: Add physical memory protection CSRsAndrew Waterman1-0/+43
2017-03-30Add support for the WebAssembly file format and the wasm32 ELF conversion to ...Pip Cet1-0/+5
2017-03-29PowerPC -Mraw disassemblyAlan Modra1-0/+5
2017-03-27Add minimal support for WebAssembly backend to the BFD library.Pip Cet1-0/+4
2017-03-27Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.Rinat Zelig1-0/+4
2017-03-21S/390: Remove vx2 facility flagAndreas Krebbel1-0/+5
2017-03-21arc/nps400: Add cp16/cp32 instructions to opcodes libraryRinat Zelig1-0/+4
2017-03-16Add support for a GNU BUILD note type to record the enum size.Nick Clifton1-0/+5
2017-03-14Add DW_OP_GNU_variable_valueH.J. Lu1-0/+5
2017-03-13Sync libiberty sources with GCC.Nick Clifton1-0/+9
2017-03-13Rename R_AARCH64_TLSDESC_LD64_LO12_NC to R_AARCH64_TLSDESC_LD64_LO12 and R_AA...Nick Clifton1-0/+8
2017-03-10Add basic recognition of new EM_ ELF machine numbers.Nick Clifton1-0/+8
2017-03-08Properly dump NT_GNU_PROPERTY_TYPE_0H.J. Lu1-0/+8
2017-03-01Add support for displaying and merging GNU_BUILD_NOTEs.Nick Clifton1-0/+42
2017-02-28GDB: Add support for the new set/show disassembler-options commands.Peter Bergner1-0/+16
2017-02-28PowerPC addpcis fixAlan Modra1-0/+5
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford1-0/+7
2017-02-24[AArch64] Add a "compnum" featureRichard Sandiford1-0/+5
2017-02-24Add new counter-enable CSRsAndrew Waterman1-0/+7
2017-02-15Add SFENCE.VMA instructionAndrew Waterman1-0/+6
2017-02-14PowerPC register expression checksAlan Modra1-0/+6
2017-01-25Clarify that include/opcode/ files are part of GNU opcodesDimitar Dimitrov1-0/+9
2017-01-25Fix include/ChangeLog entry formatPedro Alves1-1/+1
2017-01-24[PATCH] Add NT_ARM_SVEAlan Hayward1-0/+4
2017-01-04[DWARF] Sync GCC dwarf.def change on AArch64Jiong Wang1-0/+10
2017-01-04[AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy1-0/+5
2017-01-03Add support for the Q extension to the RISCV ISA.Kito Cheng1-0/+4
2017-01-03Sync dwarf headers with master versions in gcc repository.Nick Clifton1-0/+37
2017-01-02Update year range in copyright notice of all files.Alan Modra1-0/+4
2017-01-02ChangeLog rotationAlan Modra1-829/+2
2016-12-31PRU BFD supportDimitar Dimitrov1-0/+7
2016-12-23MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki1-0/+5
2016-12-23MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki1-0/+5
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki1-0/+4
2016-12-21Remove high bit set charactersAlan Modra1-0/+5
2016-12-20MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki1-0/+4
2016-12-20Re-work RISC-V gas flags: now we just support -mabi and -marchAndrew Waterman1-0/+7
2016-12-20Rework RISC-V relocationsAndrew Waterman1-0/+5
2016-12-16Implement and document --gc-keep-exportedfincs1-0/+4
2016-12-14MIPS/opcodes: Also set disassembler's ASE flags from ELF structuresMaciej W. Rozycki1-0/+5
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li1-0/+8
2016-12-09MIPS16: Remove unused `>' operand codeMaciej W. Rozycki1-0/+4
2016-12-07MIPS/include: opcode/mips.h: Correct INSN_CHIP_MASKMaciej W. Rozycki1-0/+4
2016-12-07MIPS/include: opcode/mips.h: Add a comment for ASE_DSPR3Maciej W. Rozycki1-0/+4
2016-12-05[ARM] Add ARMv8.3 command line option and feature flagSzabolcs Nagy1-0/+5
2016-11-29[ARC] Add checking for LP_COUNT reg usage, improve error reporting.Claudiu Zissulescu1-0/+5
2016-11-22gas,opcodes: fix hardware capabilities bumping in the sparc assembler.Jose E. Marchesi1-0/+5
2016-11-22PR20744, Incorrect PowerPC VLE relocsAlan Modra1-0/+5
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