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AgeCommit message (Expand)AuthorFilesLines
2017-09-11nds32: Rename __BIT() to N32_BIT().Kuan-Lin Chen1-0/+4
2017-09-05Missing relocation R_PPC_VLE_ADDR20 and add VLE flag to details in readelfAlexander Fedotov-B556131-0/+5
2017-08-24[PowerPC VLE] Add SPE2 and EFS2 instructions supportAlexander Fedotov1-0/+10
2017-08-23compile: Add 'set compile-gcc'Jan Kratochvil1-0/+7
2017-08-23compile: set debug compile: Display GCC driver filenameJan Kratochvil1-0/+7
2017-08-21[PowerPC VLE] Add LSP (Lightweight Signal Processing) instruction supportAlexander Fedotov1-0/+5
2017-08-16Add new NT_PPC_* available since Linux 4.8Gustavo Romero1-0/+16
2017-08-06Treat common symbol as undefined for --no-define-commonH.J. Lu1-0/+5
2017-07-31Fix compile time error when using ansidecl.h with an old version of GCC.Nick Clifton1-0/+6
2017-07-19[ARC] Add SJLI instruction.Claudiu Zissulescu1-0/+4
2017-07-19[ARC] Add JLI support.John Eric Martin1-0/+6
2017-07-18Fix spelling typos.Yuri Chornovian1-0/+12
2017-07-14binutils/objdump: Fix disassemble for huge elf sectionsRavi Bangoria1-0/+5
2017-07-07Recognize the recently-added FreeBSD core dump note for LWP info.John Baldwin1-0/+4
2017-07-02Import include/+libiberty/ r249883 from upstream GCC.Jan Kratochvil1-0/+9
2017-06-30Add support for a __gcc_isr pseudo isntruction to the AVR assembler.Georg-Johann Lay1-0/+5
2017-06-30MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki1-0/+5
2017-06-29S390: Support guarded-storage core note sectionsAndreas Arnez1-0/+5
2017-06-28[AArch64] Add dot product support for AArch64 to binutilsTamar Christina1-0/+5
2017-06-28[ARM] Assembler and disassembler support Dot Product ExtensionJiong Wang1-0/+5
2017-06-28MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki1-0/+15
2017-06-26RISC-V: Use pc-relative relocation for FDE initial locationKuan-Lin Chen1-0/+4
2017-06-26Add pgste marker changelogAndreas Krebbel1-0/+4
2017-06-24[ARM] Add support for ARMv8-R in assembler and readelfThomas Preud'homme1-0/+11
2017-06-24[ARM] Remove ARMv6S-M special casingThomas Preud'homme1-0/+8
2017-06-22x86: Support Intel Shadow Stack with SHSTK propertyH.J. Lu1-0/+5
2017-06-22x86: Support Intel IBT with IBT property and IBT-enable PLTH.J. Lu1-0/+6
2017-06-21[ARM] Rework Tag_CPU_arch build attribute value selectionThomas Preud'homme1-0/+4
2017-06-16Rewrite __start and __stop symbol handlingAlan Modra1-0/+8
2017-06-14Don't use print_insn_XXX in GDBYao Qi1-0/+8
2017-06-06ld: Allow section groups to be resolved as part of a relocatable linkAndrew Burgess1-0/+5
2017-06-01PPC64_OPT_LOCALENTRYAlan Modra1-0/+4
2017-05-31Fix MinGW compilation warnings due to environ.hEli Zaretskii1-0/+4
2017-05-30[ARC] Add arc-cpu.def with processor definitionsAnton Kolesov1-0/+4
2017-05-24Move print_insn_XXX to an opcodes internal headerYao Qi1-0/+5
2017-05-24Refactor disassembler selectionYao Qi1-0/+4
2017-05-23[ARC] Update MAX_INSN_FLGS.claziss1-0/+4
2017-05-22x86: Add NOTRACK prefix supportH.J. Lu1-0/+4
2017-05-19binutils: support for the SPARC M8 processorJose E. Marchesi1-0/+26
2017-05-16Rename non_ir_ref to non_ir_ref_regularAlan Modra1-0/+5
2017-05-16non_ir_ref_dynamicAlan Modra1-0/+5
2017-05-15MIPS16e2: Add MIPS16e2 ASE supportMaciej W. Rozycki1-0/+10
2017-05-14Fix match and mask for 64-bit bb opcode.John David Anglin1-0/+4
2017-05-10[ARC] Object attributes.Claudiu Zissulescu1-0/+16
2017-04-20Handle symbol defined in IR and referenced in DSOH.J. Lu1-0/+5
2017-04-19Implement -z dynamic-undefined-weakAlan Modra1-0/+5
2017-04-11Reorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500Alan Modra1-0/+2
2017-04-11Bye bye PPC_OPCODE_HTM and -mhtmAlan Modra1-0/+1
2017-04-11Bye Bye PPC_OPCODE_VSX3Alan Modra1-0/+1
2017-04-11Bye bye PPC_OPCODE_ALTIVEC2Alan Modra1-0/+4
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