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2024-02-08x86-64: Add R_X86_64_CODE_6_GOTTPOFFH.J. Lu3-4/+47
For add %reg1, name@gottpoff(%rip), %reg2 and add name@gottpoff(%rip), %reg1, %reg2 add #define R_X86_64_CODE_6_GOTTPOFF 50 if the instruction starts at 6 bytes before the relocation offset. They are similar to R_X86_64_GOTTPOFF. Linker can covert GOTTPOFF to add $name@tpoff, %reg1, %reg2 Rewrite fx_tcbit, fx_tcbit2 and fx_tcbit3 usage to generate R_X86_64_GOTPCRELX, R_X86_64_REX_GOTPCRELX, R_X86_64_CODE_4_GOTPCRELX, R_X86_64_CODE_4_GOTTPOFF, R_X86_64_CODE_4_GOTPC32_TLSDESC and R_X86_64_CODE_6_GOTTPOFF. NB: There is no need to check BFD_RELOC_X86_64_CODE_4_GOTTPOFF in md_assemble since there is only BFD_RELOC_X86_64_GOTTPOFF at this stage, which will be converted to BFD_RELOC_X86_64_CODE_4_GOTTPOFF or BFD_RELOC_X86_64_CODE_6_GOTTPOFF in i386_validate_fix. 5 relocations: #define R_X86_64_CODE_5_GOTPCRELX 46 #define R_X86_64_CODE_5_GOTTPOFF 47 #define R_X86_64_CODE_5_GOTPC32_TLSDESC 48 #define R_X86_64_CODE_6_GOTPCRELX 49 #define R_X86_64_CODE_6_GOTPC32_TLSDESC 51 are added for completeness and they are unused. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX, R_X86_64_CODE_6_GOTTPOFF and R_X86_64_CODE_6_GOTPC32_TLSDESC. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX, R_X86_64_CODE_6_GOTTPOFF and R_X86_64_CODE_6_GOTPC32_TLSDESC. (elf_x86_64_check_tls_transition): Handle R_X86_64_CODE_6_GOTTPOFF. (elf_x86_64_tls_transition): Likewise. (elf_x86_64_scan_relocs): Handle R_X86_64_CODE_6_GOTTPOFF. Issue an error for R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX and R_X86_64_CODE_6_GOTPC32_TLSDESC. (elf_x86_64_relocate_section): Handle R_X86_64_CODE_6_GOTTPOFF. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_5_GOTPCRELX, BFD_RELOC_X86_64_CODE_5_GOTTPOFF, BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC, BFD_RELOC_X86_64_CODE_6_GOTPCRELX, BFD_RELOC_X86_64_CODE_6_GOTTPOFF and BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. elfcpp/ * x86_64.h (R_X86_64_CODE_5_GOTPCRELX): New. (R_X86_64_CODE_5_GOTTPOFF): Likewise. (R_X86_64_CODE_5_GOTPC32_TLSDESC): Likewise. (R_X86_64_CODE_6_GOTPCRELX): Likewise. (R_X86_64_CODE_6_GOTTPOFF): Likewise. (R_X86_64_CODE_6_GOTPC32_TLSDESC): Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. (md_assemble): Don't check BFD_RELOC_X86_64_CODE_4_GOTTPOFF. Allow "add %reg1, foo@gottpoff(%rip), %reg2". (output_disp): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. Rewrite setting fx_tcbitX bits for BFD_RELOC_X86_64_GOTTPOFF, BFD_RELOC_X86_64_GOTPC32_TLSDESC and BFD_RELOC_32_PCREL. (md_apply_fix): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. (i386_validate_fix): Rewrite fx_tcbitX bit checking for BFD_RELOC_X86_64_GOTTPOFF, BFD_RELOC_X86_64_GOTPC32_TLSDESC and BFD_RELOC_32_PCREL. (tc_gen_reloc): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. * testsuite/gas/i386/x86-64-gottpoff.d: Updated. * testsuite/gas/i386/x86-64-gottpoff.s: Add tests for "add %reg1, foo@gottpoff(%rip), %reg2" and "add foo@gottpoff(%rip), %reg, %reg2". gold/ * x86_64.cc (Target_x86_64::optimize_tls_reloc): Handle R_X86_64_CODE_6_GOTTPOFF. (Target_x86_64::Scan::get_reference_flags): Likewise. (Target_x86_64::Scan::local): Likewise. (Target_x86_64::Scan::global): Likewise. (Target_x86_64::Relocate::relocate): Likewise. (Target_x86_64::Relocate::relocate_tls): Likewise. (Target_x86_64::Relocate::tls_ie_to_le): Handle. R_X86_64_CODE_6_GOTTPOFF. * testsuite/x86_64_ie_to_le.s: Add tests for "add %reg1, foo@gottpoff(%rip), %reg2" and "add foo@gottpoff(%rip), %reg, %reg2". * testsuite/x86_64_ie_to_le.sh: Updated. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX, R_X86_64_CODE_6_GOTTPOFF and R_X86_64_CODE_6_GOTPC32_TLSDESC. ld/ * testsuite/ld-x86-64/tlsbindesc.s: Add R_X86_64_CODE_6_GOTTPOFF tests. * testsuite/ld-x86-64/tlsbindesc.d: Updated. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise.
2024-01-29Updated French translations for GOLD and LDNick Clifton1-158/+167
2024-01-22Updated Serbian translations for th bfd, gold and opcodes directoriesNick Clifton1-159/+167
2024-01-18Updated translations for various sub-directoriesNick Clifton2-323/+342
2024-01-15Change version to 2.42.50 and regenerate filesNick Clifton2-94/+98
2024-01-15Add markers for 2.42 branchNick Clifton1-0/+4
2024-01-05Enforce C++11 as a minimum for building gold [PR30867]Tamar Christina6-2/+1012
The attempt in 5e9091dab885 to correct gold for modern LLVM has broken gold for older compilers. This commit introduced C++11 types without changing the build system to require a C++ compiler. More importantly it depends on the compiler having at least C++11 as the default language. Older compilers which support C++11 but not as the default language needlessly break. Fix that. PR gold/30867 * configure.ac (AX_CXX_COMPILE_STDCXX): Require C++11. * Makefile.in: Regenerate. * aclocal.m4: Regenerate. * config.in: Regenerate. * configure: Regenerate. * testsuite/Makefile.in: Regenerate.
2024-01-04Update year range in copyright notice of binutils filesAlan Modra483-485/+485
Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out */po/*.pot which we don't update frequently.
2023-12-28Gold: Handle R_X86_64_CODE_4_GOTPC32_TLSDESC/R_X86_64_CODE_4_GOTTPOFFH.J. Lu7-37/+195
Handle R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC. Convert add name@gottpoff(%rip), %reg mov name@gottpoff(%rip), %reg to add $name@tpoff, %reg mov $name@tpoff, %reg and lea name@tlsdesc(%rip), %reg to mov $name@tpoff, %reg mov name@gottpoff(%rip), %reg if the instruction is encoded with the REX2 prefix when possible. elfcpp/ * x86_64.h (R_X86_64_CODE_4_GOTTPOFF): New. (R_X86_64_CODE_4_GOTPC32_TLSDESC): Likewise. gold/ * x86_64.cc (Target_x86_64::optimize_tls_reloc): Handle R_X86_64_CODE_4_GOTPC32_TLSDESC and R_X86_64_CODE_4_GOTTPOFF. (Target_x86_64::Scan::get_reference_flags): Likewise. (Target_x86_64::Scan::local): Likewise. (Target_x86_64::Scan::global): Likewise. (Target_x86_64::Relocate::relocate): Likewise. (Target_x86_64::Relocate::relocate_tls): Likewise. (Target_x86_64::Relocate::tls_desc_gd_to_ie): Handle R_X86_64_CODE_4_GOTPC32_TLSDESC. (Target_x86_64::Relocate::tls_desc_gd_to_le): Likewise. (Target_x86_64::Relocate::tls_ie_to_le): Handle. R_X86_64_CODE_4_GOTTPOFF. * testsuite/Makefile.am: Add x86_64_ie_to_le test. * testsuite/Makefile.in: Regenerated. * testsuite/x86_64_gd_to_le.s: Add R_X86_64_CODE_4_GOTPC32_TLSDESC test. * testsuite/x86_64_gd_to_le.sh: Check GDesc to LE conversion. * testsuite/x86_64_ie_to_le.s: New file. * testsuite/x86_64_ie_to_le.sh: Likewise.
2023-12-28gold: Handle R_X86_64_CODE_4_GOTPCRELXH.J. Lu7-9/+49
Handle R_X86_64_CODE_4_GOTPCRELX and convert mov name@GOTPCREL(%rip), %r31 to lea name@GOTPCREL(%rip), %r31 if the instruction is encoded with the REX2 prefix when possible. elfcpp/ * x86_64.h (R_X86_64_CODE_4_GOTPCRELX): New. gold/ * x86_64.cc (Target_x86_64::can_convert_mov_to_lea): Handle R_X86_64_CODE_4_GOTPCRELX. (Target_x86_64::Scan::get_reference_flags): Likewise. (Target_x86_64::Scan::local): Likewise. (Target_x86_64::Scan::possible_function_pointer_reloc): Likewise. (Target_x86_64::Scan::global): Likewise. (Target_x86_64::Relocate::relocate): Likewise. * testsuite/x86_64_mov_to_lea1.s: Add a test for R_X86_64_CODE_4_GOTPCRELX. * testsuite/x86_64_mov_to_lea2.s: Likewise. * testsuite/x86_64_mov_to_lea3.s: Likewise. * testsuite/x86_64_mov_to_lea4.s: Likewise. * testsuite/x86_64_mov_to_lea5.s: Likewise. * testsuite/x86_64_mov_to_lea.sh: Updated.
2023-12-11R_MICROMIPS_GPREL7_S2Alan Modra1-18/+64
This reloc is meant for the 16-bit LWGP instruction, 0x6400/0xfc00 match/mask encoding in `micromips_opcodes'. It is correctly specified to operate on a half-word by the howtos in elf32-mips.c, elfn32-mips.c and elf64-mips.c, but is incorrectly subject to shuffle/unshuffle in code like _bfd_mips_elf32_gprel16_reloc. Current behaviour when applying the reloc to .byte 0x11,0x22,0x33,0x44 is to apply the reloc to byte 0x22 when big-endian, and to byte 0x33 when little-endian. Big-endian behaviour is unchanged after this patch and little-endian correctly applies the reloc to byte 0x11. The patch also corrects REL addend extraction from section contents, and overflow checking. gold had all of the bfd problems with this reloc and additionally did not apply the rightshift by two. bfd/ * elfxx-mips.c (micromips_reloc_shuffle_p): Return false for R_MICROMIPS_GPREL7_S2. (mips_elf_calculate_relocation): Correct sign extension and overflow calculation for R_MICROMIPS_GPREL7_S2. (_bfd_mips_elf_relocate_section): Update small-data overflow message. gold/ * mips.cc (Mips_relocate_functions::should_shuffle_micromips_reloc): Return false for R_MICROMIPS_GPREL7_S2. (Mips_relocate_functions::mips_reloc_unshuffle): Update comment. (Mips_relocate_functions::relgprel): Remove R_MICROMIPS_GPREL7_S2 handling. (Mips_relocate_functions::relgprel7): New function. (Target_mips::Relocate::relocate): Adjust to suit. ld/ * testsuite/ld-mips-elf/reloc-4.d: Adjust expected error. * testsuite/ld-mips-elf/reloc-5.d: Likewise.
2023-11-17Gold/MIPS: Add targ_extra_size=64 for mips32 triplesYunQiang Su2-2/+8
2023-11-16Fix emit-relocs for aarch64 goldVladislav Khmelevsky1-0/+22
Fix relocation offsets values for the relaxed input sections the same way it was fixed for the sections in PR21430.
2023-11-15Finalized intl-update patchesArsen Arsenovi?7-111/+2185
* intl: Remove directory. Replaced with out-of-tree GNU gettext. * .gitignore: Add '/gettext*'. * configure.ac (host_libs): Replace intl with gettext. (hbaseargs, bbaseargs, baseargs): Split baseargs into {h,b}baseargs. (skip_barg): New flag. Skips appending current flag to bbaseargs. <library exemptions>: Exempt --with-libintl-{type,prefix} from target and build machine argument passing. * configure: Regenerate. * Makefile.def (host_modules): Replace intl module with gettext module. (configure-ld): Depend on configure-gettext. * Makefile.in: Regenerate. * src-release.sh: Remove references to the intl/ directory.
2023-11-10Gold/MIPS: Use EM_MIPS instead of EM_MIPS_RS3_LE for little endianYunQiang Su2-1/+6
2023-11-10MIPS: Change all E_MIPS_* to EF_MIPS_*Ying Huang1-84/+84
2023-09-06gold: Use char16_t, char32_t instead of uint16_t, uint32_t as character typesRoland McGrath4-6/+22
The std::basic_string template type is only specified for instantiations using character types. Newer (LLVM) libc++ implementations no longer allow non-character integer types to be used. gold/ * output.cc: Include <uchar.h>. (Output_section::add_merge_input_section): Use char16_t and char32_t for 2- and 4-byte entry size, respectively. * stringpool.cc: Include <uchar.h>. (Stringpool_template): Explicitly instantiate for char16_t, char32_t instead of uint16_t, uint32_t. * merge.cc (Output_merge_string): Likewise.
2023-08-30Revert "Gold: Add targ_extra_little_endian to configure.ac"Maciej W. Rozycki3-17/+1
This reverts commit cf8565fb2ea42579c50722cbaeafdf71c3d58c66. It was applied unapproved.
2023-08-30Revert "Gold/MIPS: Use EM_MIPS instead of EM_MIPS_RS3_LE for little endian"Maciej W. Rozycki1-1/+1
This reverts commit 39834263784567c306fbccb8230ddd1badca53fe. It was applied unapproved.
2023-08-30Revert "Gold/MIPS: Drop mips*le/mips*el* triple pattern"Maciej W. Rozycki1-1/+1
This reverts commit adb3ae2eba78b4b84d7b94342f6774b250190a98. It was applied unapproved.
2023-08-30Revert "Gold/MIPS: Add targ_extra_size=64 for mips32 triples"Maciej W. Rozycki1-2/+0
This reverts commit d6cdc0af2b880bb48dd16055f4cb3509c7a2da70. It was applied unapproved.
2023-08-30Revert "Gold/MIPS: Add mips64*/mips64*el triple support"Maciej W. Rozycki1-16/+0
This reverts commit 5c4cdba100b66e2924a25dad9b12d8e5b84d527f. It was applied unapproved.
2023-08-30Revert "MIPS: Use 64-bit a ABI by default for `mipsisa64*-*-linux*' targets"Maciej W. Rozycki1-2/+2
This reverts commit 025e84f93566c8ced594ef48ddee1dec7e5b4cdd. It was applied unapproved.
2023-08-27MIPS: Use 64-bit a ABI by default for `mipsisa64*-*-linux*' targetsYunQiang Su1-2/+2
Following the arrangement in GCC select a 64-bit ABI by default, either n32 or n64, rather than o32 for `mipsisa64*-*-linux*' targets, just as with the corresponding `mips64*-*-linux*' targets.
2023-08-27Gold/MIPS: Add mips64*/mips64*el triple supportYunQiang Su1-0/+16
Use targ_size=64 and targ_extra_size=32
2023-08-27Gold/MIPS: Add targ_extra_size=64 for mips32 triplesYunQiang Su1-0/+2
So we can enable 64bit ELF support for MIPS32 toolchain.
2023-08-27Gold/MIPS: Drop mips*le/mips*el* triple patternYunQiang Su1-1/+1
Only mips*el triples are supported by binutils. The mips*le or mips*el* may cause some problem with other components of binutils, since they will consider them as big endian.
2023-08-27Gold/MIPS: Use EM_MIPS instead of EM_MIPS_RS3_LE for little endianYunQiang Su1-1/+1
EM_MIPS_RS3_LE has been deprecated quite long ago, and in fact most of current LE ELF files are using EM_MIPS. This problem didn't make some trouble for us, is due to that gold is a linker, and all of the inputs to it has right EM values.
2023-08-27Gold: Add targ_extra_little_endian to configure.acYunQiang Su3-1/+17
This option will be used by architectures which is big endian by default, while little-endian support is also needed. Mips(eb) ports are the examples.
2023-08-25PR30794, PowerPC gold: internal error in add_output_section_to_loadAlan Modra1-22/+25
Caused by commit 5a97377e5513, specifically this code added to Target_powerpc::do_relax + if (parameters->options().output_is_position_independent()) + this->rela_dyn_size_ + = this->rela_dyn_section(layout)->current_data_size(); The problem here is that if .rela.dyn isn't already created then the call to rela_dyn_section creates it, and as this comment in Target_powerpc::do_finalize_sections says: // Annoyingly, we need to make these sections now whether or // not we need them. If we delay until do_relax then we // need to mess with the relaxation machinery checkpointing. We can't be creating sections in do_relax. PR 30794 * powerpc.cc (Target_powerpc::do_relax): Only set rela_dyn_size_ for size == 64, and assert that rela_dyn_ already exists. Tidy code setting plt_thread_safe, which also only needs to be set when size == 64 for ELFv1.
2023-08-02Revert "2.41 Release sources"Sam James6-22/+53
This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton6-53/+22
2023-07-28Revert "MIPS: support mips*64 as CPU and gnuabi64 as ABI"Maciej W. Rozycki1-14/+0
This reverts commit 32f1c80375ebe8ad25d9805ee5889f0006c51e59. It had two unrelated changes lumped together, one of which changed the meaning of the `mipsisa64*-*-linux*' target triplets, which was not properly evaluated.
2023-07-26[GOLD] reporting local symbol namesAlan Modra4-13/+49
get_symbol_name currently returns "" for the usual STT_SECTION symbols generated by gas. That's not very helpful, return the section name. Demangle local symbols too, fixing an inconsistency in issue_discarded_error where global symbols are demangled. * object.cc (Sized_relobj_file::get_symbol_name): Return a std::string. Return section name for STT_SECTION symbols with zero st_name. Sanity check st_name, and don't run off the end of an improperly terminated .strtab. Demangle sym names. * object.h (Sized_relobj_file::get_symbol_name): Update decl. * target-reloc.h (issue_discarded_error): Adjust. * powerpc.cc (Target_powerpc::Relocate::relocate): Report reloc type and symbol for relocation overflows.
2023-07-24Updated translations for bfd, gold and opcodesNick Clifton1-322/+330
2023-07-19[GOLD, PowerPC64] Debug info relocation overflowAlan Modra1-4/+13
It is possible to build huge binaries on powerpc64, where 32-bit addresses in debug info are insufficient to descibe locations in the binary. Help out the user, and only warn about debug overflows. * powerpc.cc (Target_powerpc::Relocate::relocate): Warn on relocation overflows in debug info.
2023-07-17PR10957, Missing option to really print section+offsetAlan Modra4-9/+9
Many of the reloc error messages have already been converted from using %C to using %H in ld.bfd, to print section+offset as well as file/line/function. This catches a few remaining, and changes gold to do the same. PR 10957 bfd/ * elf32-sh.c (sh_elf_relocate_section): Use %H in error messages. gold/ * object.cc (Relocate_info::location): Always report section+offset. * testsuite/debug_msg.sh: Adjust to suit. * testsuite/x32_overflow_pc32.sh: Likewise. * testsuite/x86_64_overflow_pc32.sh: Likewise. ld/ * emultempl/pe.em (read_addend): Use %H in error message. * emultempl/pep.em (read_addend): Likewise. * ldcref.c (check_reloc_refs): Likewise. * ldmain.c (warning_find_reloc, undefined_symbol): Likewise. * pe-dll.c (pe_create_import_fixup): Likewise. * testsuite/ld-cris/undef2.d: Adjust expected output to suit. * testsuite/ld-cris/undef3.d: Likewise. * testsuite/ld-elf/shared.exp: Likewise. * testsuite/ld-i386/compressed1.d: Likewise. * testsuite/ld-ia64/line.exp: Likewise. * testsuite/ld-plugin/lto.exp: Likewise. * testsuite/ld-undefined/undefined.exp: Likewise. * testsuite/ld-x86-64/compressed1.d: Likewise. * testsuite/ld-x86-64/line.exp: Likewise. * testsuite/ld-x86-64/pr27587.err: Likewise.
2023-07-07Udated Freach and Romainian translations for various sub-directoriesNick Clifton1-329/+331
2023-07-04Updated Ukranian, Romanian and German translations for various sub-directoriesNick Clifton2-645/+662
2023-07-03Change version number to 2.41.50 and regenerate filesNick Clifton2-397/+417
2023-07-03Add markers for the 2.41 branchNick Clifton1-0/+4
2023-06-28Updated French translation for the gold sub-directoryNick Clifton2-338/+359
2023-06-23[GOLD] PowerPC64 huge branch dynamic relocsAlan Modra1-61/+38
PowerPC64 gold and ld.bfd implement an indirect branch trampoline, used when the destination of a branch exceeds a bounce through another "b" instruction. When generating PIEs or shared libraries, the addresses need dynamic relocations. This was implemented in gold using a dedicated relocation section, but this means the relative relocations for these addresses are not sorted properly with other dynamic relative relocations: gold doesn't support merging relocation sections, then sorting. Instead we need to use a single .rela.dyn section. This is done by increasing the size of rela_dyn_ during do_relax to account for needed dynamic relocations, delaying adding the actual relocations until the end of relaxation once the layout has stabilised. * powerpc.cc (Target_powerpc): Add rela_dyn_size_; (update_current_size): New function. (Target_powerpc::do_relax): Capture the size of rela_dyn_ at the start of relaxation. Artifically increase its size during relaxation to account for needed indirect branches, and add those relocations at the end. (Output_data_brlt_powerpc::rel_, reset_brlt_sizes), (finalize_brlt_sizes, add_reloc, set_current_size): Delete. (Target_powerpc::make_brlt_section): Don't make reloc section.
2023-06-23[GOLD] Support setting DT_RELACOUNT lateAlan Modra11-16/+38
PowerPC gold adds relative dynamic relocs in do_relax. These aren't accounted for in the value set in add_target_dynamic_tags, which is called before do_relax. Provide a way of setting DT_RELCOUNT and DT_RELACOUNT at the point where .dynamic is written. * layout.cc (Layout::add_target_dynamic_tags): Add custom_relcount parameter. Emit DT_RELCOUNT/RELACOUNT as a custom target handled dynamic tag if set. * layout.h(Layout::add_target_dynamic_tags): Update prototype. * aarch64.cc (Target_aarch64::do_finalize_sections): Adjust add_target_dynamic_tags call. * arm.cc (Target_arm::do_finalize_sections): Likewise. * i386.cc (Target_i386::do_finalize_sections): Likewise. * mips.cc (Target_mips::do_finalize_sections): Likewise. * s390.cc (Target_s390::do_finalize_sections): Likewise. * sparc.cc (Target_sparc::do_finalize_sections): Likewise. * tilegx.cc (Target_tilegx::do_finalize_sections): Likewise. * x86_64.cc (Target_x86_64::do_finalize_sections): Likewise. * powerpc.cc (Target_powerpc::do_finalize_sections): Likewise. (Target_powerpc::do_dynamic_tag_custom_value): New function.
2023-06-23[GOLD] powerpc DT_RELACOUNTAlan Modra1-2/+7
DT_RELACOUNT was calculated incorrectly, and relative relocs not sorted as they should be to the start of .rela.dyn, due to adding one particular class of dynamic reloc using the wrong "add" method. * powerpc.cc (Target_powerpc::Scan::global): Add relative dyn relocs for ADDR64 and similar using add_global_relative.
2023-06-21PR30536, ppc64el gold linker produces unusable clang-16 binaryAlan Modra1-1/+9
In commit 0961e631575b, the fix for PR30217, make_lplt_section and make_brlt_section were changed to use rela_dyn_ rather than their own separate dynamic reloc sections. This fails miserably whenever brlt_ is needed for long branches, due to needing to iterate sizing and thus reset brlt_ sizes. PR 30536 PR 30217 * powerpc.cc (Target_powerpc::make_brlt_section): Don't use rela_dyn_.
2023-04-23MIPS: support mips*64 as CPU and gnuabi64 as ABIYunQiang Su1-0/+14
For MIPS64r6 ports, Debian as an example, `mipsisa64r6el` is used as the cpu name in triple. Let's recognize them by `mips*64*(el)`. For 64bit Ports, like Debian's mips64el and mips64r6el ports, `gnuabi64` is used as the abi section. Let's use N64 abi by default for the triple with gnuabi64.
2023-03-27Add an option to the gold linker to put its version string into the .comment ↵Nick Clifton3-10/+40
section. PR 30187 * options.h (class General_options): Add enable-linker-version. * layout.cc (Layout::create_gold_note): If linker-version is enabled put the version string into the .comment section.
2023-03-16PR30217, dynamic relocations using local dynamic symbolsAlan Modra1-24/+39
glibc's ld.so ignores local dynamic symbols. It's been that way forever. We therefore can't use them on dynamic relocations. Fixing that problem uncovered another problem in sorting of dynamic relocs, caused no doubt by copying make_iplt_section (where we don't want reloc sorting by the generic gold function, we want iplt relocs last) to make_lplt_section (where we do want sorting). PR 30217 * powerpc.cc (branch_needs_plt_entry): New function. (Target_powerpc::plt_off): Use it here.. (Target_powerpc::Scan::global): ..and here to correct PLT16 reloc handling for forced-local global symbols. (Output_data_plt_powerpc::add_entry): Rename "stash" parameter "is_local". Emit relative relocs for globals that are forced local, and don't set_needs_dynsym_entry. (Target_powerpc::make_lplt_section): Don't create a separate reloc section, use rela_dyn. (Target_powerpc::make_brlt_section): Likewise.
2023-02-27Updated Serbian translations for gold, gprof and opcodes sub-directoriesNick Clifton1-296/+312
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