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2017-08-30PowerPC TPREL16_HA/LO reloc optimizationAlan Modra1-0/+32
In the TLS GD/LD to LE optimization, ld replaces a sequence like addi 3,2,x@got@tlsgd R_PPC64_GOT_TLSGD16 x bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x R_PPC64_REL24 __tls_get_addr nop with addis 3,13,x@tprel@ha R_PPC64_TPREL16_HA x addi 3,3,x@tprel@l R_PPC64_TPREL16_LO x nop When the tprel offset is small, this can be further optimized to nop addi 3,13,x@tprel nop bfd/ * elf64-ppc.c (struct ppc_link_hash_table): Add do_tls_opt. (ppc64_elf_tls_optimize): Set it. (ppc64_elf_relocate_section): Nop addis on TPREL16_HA, and convert insn on TPREL16_LO and TPREL16_LO_DS relocs to use r13 when addis would add zero. * elf32-ppc.c (struct ppc_elf_link_hash_table): Add do_tls_opt. (ppc_elf_tls_optimize): Set it. (ppc_elf_relocate_section): Nop addis on TPREL16_HA, and convert insn on TPREL16_LO relocs to use r2 when addis would add zero. gold/ * powerpc.cc (Target_powerpc::Relocate::relocate): Nop addis on TPREL16_HA, and convert insn on TPREL16_LO and TPREL16_LO_DS relocs to use r2/r13 when addis would add zero. ld/ * testsuite/ld-powerpc/tls.s: Add calls with tls markers. * testsuite/ld-powerpc/tls32.s: Likewise. * testsuite/ld-powerpc/powerpc.exp: Run tls marker tests. * testsuite/ld-powerpc/tls.d: Adjust for TPREL16_HA/LO optimization. * testsuite/ld-powerpc/tlsexe.d: Likewise. * testsuite/ld-powerpc/tlsexetoc.d: Likewise. * testsuite/ld-powerpc/tlsld.d: Likewise. * testsuite/ld-powerpc/tlsmark.d: Likewise. * testsuite/ld-powerpc/tlsopt4.d: Likewise. * testsuite/ld-powerpc/tlstoc.d: Likewise.
2017-08-29[GOLD] PowerPC tls_get_addr_optimizeAlan Modra1-57/+306
This implements the special __tls_get_addr_opt call stub for powerpc gold that returns __thread variable addresses without actually making a call to __tls_get_addr in most cases. Shared libraries that are loaded at program load time (ie. dlopen is not used) have a known layout for their __thread variables, and thus DTPMOD64/DPTREL64 pairs describing those variables can be set up by ld.so for the __tls_get_addr_opt call stub fast exit. Ref https://sourceware.org/ml/libc-alpha/2015-03/msg00626.html I really, really wish I'd used a differently versioned __tls_get_addr symbol than the base symbol to indicate glibc support for the optimized call, rather than having glibc export __tls_get_addr_opt. A lot of the messing around here, flipping symbols from __tls_get_addr to __tls_get_addr_opt, is caused by that decision. About the only benefit is that a user can see at a glance that their disassembled code is calling __tls_get_addr via the fancy call stub.. Anyway, we need references to __tls_get_addr to seem like they were to __tls_get_addr_opt, and in cases like the tsan interceptor, a definition of __tls_get_addr to seem like one of __tls_get_addr_opt as well. That's the reason for Symbol::clear_in_reg and Symbol_table::clone, and why symbols are substituted in Scan::global and other places dealing with dynamic linking. elfcpp/ * elfcpp.h (DT_PPC_OPT): Define. * powerpc.h (PPC_OPT_TLS): Define. gold/ * options.h (tls_get_addr_optimize): New option. * symtab.h (Symbol::clear_in_reg, clone): New functions. (Sized_symbol::clone): New function. (Symbol_table::clone): New function. * resolve.cc (Symbol::clone, Sized_symbol::clone): New functions. * powerpc.cc (Target_powerpc::has_tls_get_addr_opt_, tls_get_addr_, tls_get_addr_opt_): New vars. (Target_powerpc::tls_get_addr_opt, tls_get_addr, is_tls_get_addr_opt, replace_tls_get_addr, set_has_tls_get_addr_opt, stk_linker): New functions. (Target_powerpc::Track_tls::maybe_skip_tls_get_addr_call): Add target param. Update callers. Compare symbols rather than names. (Target_powerpc::do_define_standard_symbols): Init tls_get_addr_ and tls_get_addr_opt_. (Target_powerpc::Branch_info::mark_pltcall): Translate tls_get_addr sym to tls_get_addr_opt. (Target_powerpc::Branch_info::make_stub): Likewise. (Stub_table::define_stub_syms): Likewise. (Target_powerpc::Scan::global): Likewise. (Target_powerpc::Relocate::relocate): Likewise. (add_3_12_2, add_3_12_13, bctrl, beqlr, cmpdi_11_0, cmpwi_11_0, ld_11_1, ld_11_3, ld_12_3, lwz_11_3, lwz_12_3, mr_0_3, mr_3_0, mtlr_11, std_11_1): New constants. (Stub_table::eh_frame_added_): Delete. (Stub_table::tls_get_addr_opt_bctrl_, plt_fde_len_, plt_fde_): New vars. (Stub_table::init_plt_fde): New functions. (Stub_table::add_eh_frame, replace_eh_frame): Move definition out of line. Init and use plt_fde_. (Stub_table::plt_call_size): Return size for tls_get_addr stub. Extract alignment code to.. (Stub_table::plt_call_align): ..this new function. Adjust all callers. (Stub_table::add_plt_call_entry): Set has_tls_get_addr_opt and tls_get_addr_opt_bctrl, and align after that. (Stub_table::do_write): Write out tls_get_addr stub. (Target_powerpc::do_finalize_sections): Emit DT_PPC_OPT PPC_OPT_TLS/PPC64_OPT_TLS bit. (Target_powerpc::Relocate::relocate): Don't check for or modify nop following bl for tls_get_addr stub.
2017-08-28[GOLD] Symbol flag for PowerPC64 localentry:0 trackingAlan Modra1-3/+20
This patch provides a flag for PowerPC64 ELFv2 use in class Symbol, and modifies Sized_target::resolve to return whether the symbol has been resolved. If not, normal processing continues. I use this for PowerPC64 ELFv2 to keep track of whether a symbol has any definition with non-zero localentry, in order to disable --plt-localentry for that symbol. PR 21847 * powerpc.cc (Target_powerpc::is_elfv2_localentry0): Test non_zero_localentry. (Target_powerpc::resolve): New function. (powerpc_info): Set has_resolve for 64-bit. * target.h (Sized_target::resolve): Return bool. * resolve.cc (Symbol_table::resolve): Continue with normal processing when target resolve returns false. * symtab.h (Symbol::non_zero_localentry, set_non_zero_localentry): New accessors. (Symbol::non_zero_localentry_): New flag bit. * symtab.cc (Symbol::init_fields): Init non_zero_localentry_.
2017-08-01[GOLD] PowerPC recreate eh_frame for stubs on each relax passAlan Modra1-18/+41
There is a very small but non-zero probability that a stub group contains stubs on one relax pass, but does not on the next. In that case we would get an FDE covering a zero length address range. (Actually, it's even worse. Alignment padding for stubs can mean the address for the non-existent stubs is past the end of the original section to which stubs are attached, and due to the way do_plt_fde_location calculates the length we can get a negative length.) Fixing this properly requires removing the FDE. Also, I have been implementing the __tls_get_addr_opt support for gold, and that stub needs something other than the default FDE. The necessary FDE will depend on the offset to the __tls_get_addr_opt stub, which of course can change during relaxation. That means at the very least, rewriting the FDE on each pass, possibly changing the FDE size. I think that is better done by completely recreating PLT eh_frame FDEs. * ehframe.cc (Fde::operator==): New. (Cie::remove_fde, Eh_frame::remove_ehframe_for_plt): New. * ehframe.h (Fde::operator==): Declare. (Cie::remove_fde, Eh_frame::remove_ehframe_for_plt): Likewise. * layout.cc (Layout::remove_eh_frame_for_plt): New. * layout.h (Layout::remove_eh_frame_for_plt): Declare. * powerpc.cc (Target_powerpc::do_relax): Remove old eh_frame FDEs. (Stub_table::add_eh_frame): Delete eh_frame_added_ condition. Don't add eh_frame for empty stub section. (Stub_table::remove_eh_frame): New.
2017-07-31[GOLD] PowerPC --no-tls-optimizeAlan Modra1-15/+25
This adds a --no-tls-optimize option for people who want to keep __tls_get_addr calls in an executable rather than optimizing such code sequences to IE/LE. Also tidy some formatting errors, rename a variable to better reflect its use, and tweak two functions that create pairs of GOT entries to first check whether the GOT entry already exists before potentially inserting the header via reserve(2). Without the check it is possible to waste one GOT entry. * options.h (no_tls_optimize): New powerpc option. * powerpc.cc (Target_powerpc::abiversion, set_abiversion): Formatting. (Target_powerpc::stk_toc): Formatting, fix comment. (Target_powerpc::Track_tls::tls_get_addr_state): Rename from tls_get_addr. (Target_powerpc::optimize_tls_gd, optimize_tls_ld, optimize_tls_ie): Return TLSOPT_NONE when !tls_optimize. (Target_powerpc::add_global_pair_with_rel): Check for existing reloc before reserving. (Target_powerpc::add_local_tls_pair): Likewise.
2017-07-31PR 21847, PowerPC64 --plt-localentry againAlan Modra1-0/+4
This makes ld warn about --plt-localentry if a version of glibc without the necessary ld.so checks is detected, and revises the documentation. bfd/ * elf64-ppc.c (ppc64_elf_tls_setup): Warn on --plt-localentry without ld.so checks. gold/ * powerpc.cc (Target_powerpc::scan_relocs): Warn on --plt-localentry without ld.so checks. ld/ * ld.texinfo (plt-localentry): Revise.
2017-07-29PR 21847, Don't default PowerPC64 to --plt-localentryAlan Modra1-2/+0
The big comment in ppc64_elf_tls_setup says why. I've also added some code to the bfd linker that catches the -lpthread -lc symbol differences and disable generation of optimized call stubs even when --plt-localentry is activated. Gold doesn't yet have that. PR 21847 bfd/ * elf64-ppc.c (struct ppc_link_hash_entry): Add non_zero_localentry. (ppc64_elf_merge_symbol): Set non_zero_localentry. (is_elfv2_localentry0): Test non_zero_localentry. (ppc64_elf_tls_setup): Default to --no-plt-localentry. gold/ * powerpc.cc (Target_powerpc::scan_relocs): Default to --no-plt-localentry. ld/ * ld.texinfo (plt-localentry): Document.
2017-07-23Correct eh_frame info for __glink_PLTresolveAlan Modra1-2/+2
My PPC64_OPT_LOCALENTRY patch of June 1, git commit f378ab099d, and the later gold change, git commit 7ee7ff7015, added an insn in __glink_PLTresolve which needs a corresponding adjustment in the eh_frame info for asynchronous exceptions to unwind correctly. It would have been OK for both ABIs to use +5 for the advance before restore of LR, since we can put the DW_CFA_restore_extended on any insn after the actual restore and before the r12/r0 copy is clobbered, but it's slightly better to delay as much as possible. There are then more addresses where fewer CFA program insns are executed. bfd/ * elf64-ppc.c (ppc64_elf_size_stubs): Correct advance to restore of LR. gold/ * powerpc.cc (glink_eh_frame_fde_64v2): Correct advance to restore of LR. (glink_eh_frame_fde_64v1): Advance to restore of LR at latest possible insn.
2017-07-18Fix spelling typos.Yuri Chornovian1-1/+1
2017-06-23[GOLD] PowerPC64 localentry:0 plt call optimizationAlan Modra1-11/+109
elfcpp/ * elfcpp.h (DT_PPC64_OPT): Define. * powerpc.h (PPC64_OPT_TLS, PPC64_OPT_MULTI_TOC, PPC64_OPT_LOCALENTRY): Define. gold/ * options.h (General_options): Add plt_localentry. * powerpc.cc (Target_powerpc::st_other): New function. (Target_powerpc::plt_localentry0_, plt_localentry0_init_, has_localentry0_): New vars. (Target_powerpc::plt_localentry0, set_has_localentry0, is_elfv2_localentry0): New functions. (Target_powerpc::Branch_info::mark_pltcall): Don't set tocsave or return true for localentry:0 calls. (Stub_table::Plt_stub_ent::localentry0_): New var. (Stub_table::add_plt_call_entry): Set localentry0_ and has_localentry0_. Don't set r2save_ for localentry:0 calls. (Output_data_glink::do_write): Save r2 in __glink_PLTresolve for elfv2. (Target_powerpc::scan_relocs): Default plt_localentry0_. (Target_powerpc::do_finalize_sections): Set DT_PPC64_OPT. (Target_powerpc::Relocate::relocate): Don't require nop following calls for localentry:0 plt calls, and don't change nop.
2017-06-23[GOLD] PowerPC64 tocsaveAlan Modra1-55/+224
This adds support to gold for the tocsave relocs already supported by ld.bfd. R_PPC64_TOCSAVE relocs are part of a scheme to move r2 saves to the prologue of a function rather than in each plt call stub. We don't want a compiler to always emit the r2 save, as this would be wasted if the calls turned out to be local. See the tocsave*.s in ld/testsuite/ld-powerpc/. * powerpc.cc (Target_powerpc::tocsave_loc_): New var. (Target_powerpc::mark_pltcall, add_tocsave, tocsave_loc): New functions. (Target_powerpc::Branch_info::tocsave_): New var. (Target_powerpc::Branch_info::mark_pltcall): New function. (Target_powerpc::Branch_info::make_stub): Pass tocsave_ to add_plt_call_entry. (Stub_table::Plt_stub_ent): Make public. Add r2save_. (Stub_table::add_plt_call_entry): Add bool tocsave_ param. Set r2save_. (Stub_table::find_plt_call_entry): Return Plt_stub_ent*. Adjust use throughout. (Stub_table::do_write): Conditionally output r2 save in plt stubs. (Target_powerpc::Scan::local): Handle R_PPC64_TOCSAVE. (Target_powerpc::Scan::global): Likewise. (Target_powerpc::Relocate::relocate): Skip r2 save in plt call stub with tocsave reloc. Replace header tocsave nop with r2 save. * symtab.h (struct Symbol_location_hash): Make public.
2017-06-21[GOLD] PowerPC move plt indx_ out of unordered map keyAlan Modra1-42/+53
I was lazy when adding indx_ to Plt_stub_ent. The field isn't part of the key, so ought to be part of the mapped type. Make it so. * powerpc.cc (Plt_stub_key): Rename from Plt_stub_ent. Remove indx_. (Plt_stub_key_hash): Rename from Plt_stub_ent_hash. (struct Plt_stub_ent): New. (Plt_stub_entries): Map from Plt_stub_key to Plt_stub_ent. Adjust use throughout file.
2017-06-20[GOLD] Avoid duplicate PLT stub symbols on ppc32James Clarke1-6/+12
If two objects are compiled with -fPIC or -fPIE and call the same function, two different PLT entries are created, one for each object, but the same stub symbol name is used for both. * powerpc.cc (Stub_table::define_stub_syms): Always include object's uniq_ value.
2017-05-23PR21503, Gold doesn't create linker stub symbols on ppc64Alan Modra1-27/+165
PR 21503 * options.h: Add --emit-stub-syms option. * powerpc.cc (object_id): New. (Powerpc_relobj): Add uniq_ and accessor. Sort variables for better packing. (Powerpc_dynobj): Sort variables for better packing. (Target_powerpc::define_local): New function. (Target_powerpc::group_sections): Pass stub table size to Stub_table constructor. (Target_powerpc::do_relax): Define stub and glink symbols. (Stub_table): Add uniq_ variable, and id param to constructor. (Stub_table::Plt_stub_ent): Add indx_ variable. (Stub_table::Branch_stub_entries): Move typedef earlier. (Stub_table::branch_stub_size): Replace "to" parameter with a Branch_stub_entries iterator. (Stub_table::add_long_branch_entry): Adjust to suit. (Stub_table::add_plt_call_entry): Set indx_. (Stub_table::define_stub_syms): New function.
2017-02-22PowerPC ld segfault on script discarding dynamic sectionsAlan Modra1-5/+9
bfd/ * elf64-ppc.c (ppc64_elf_finish_dynamic_sections): Don't segfault on .got or .plt output section being discarded by script. * elf32-ppc.c (ppc_elf_finish_dynamic_sections): Likewise. Move vxworks splt temp. gold/ * powerpc.cc (Target_powerpc::make_iplt_section): Check that output_section exists before attempting add_output_section_data. (Target_powerpc::make_brlt_section): Likewise.
2017-02-03[GOLD] PowerPC64 TOC indirect to TOC relative segfaultAlan Modra1-0/+6
* powerpc.cc (Powerpc_relobj::make_toc_relative): Don't crash when no .toc section exists.
2017-01-13Gold: Fix build with GCC 4.2H.J. Lu1-1/+1
PR gold/21040 * powerpc.cc (Powerpc_relobj<size, big_endian>::make_toc_relative): Cast 0x80008000 to uint64_t.
2017-01-11[GOLD] PowerPC64 TOC indirect to TOC relative code editingAlan Modra1-44/+517
Doesn't yet trim off the unused TOC entries. * powerpc.cc (class Powerpc_copy_relocs): New. (Powerpc_copy_relocs::emit): New function. (Powerpc_relobj::relatoc_, toc_, no_toc_opt_): New variables. (Powerpc_relobj::toc_shndx, set_no_toc_opt, no_toc_opt): New inlines. (Powerpc_relobj::do_relocate_sections): New function. (Powerpc_relobj::make_toc_relative): Likewise. (Powerpc_relobj::do_find_special_sections): Stash away .rela.toc and .toc too. (ok_lo_toc_insn): Move earlier, and handle more insns. (Target_powerpc::Scan::local): If optimizing toc accesses, set no_toc_opt for entries we can't edit. Check insn validity. Emit "toc optimization is not supported" warning, downgraded from error. (Target_powerpc::Scan::global): Likewise. (Target_powerpc::Relocate::relocate): Edit TOC indirect code to TOC relative. Don't emit "toc optimization is not supported" error here.
2017-01-10[GOLD] Add --secure-plt option for ppc32Alan Modra1-0/+38
Added just to accept, and ignore. gcc since 2015-10-21, when configured with --enable-secureplt passes this option to the linker. As powerpc gold cannot link --bss-plt code successfully, gold needs to accept the option or the gcc specs file needs to be changed. The patch also make gold detect --bss-plt code and error out rather than producing a binary that crashes. * options.h: Add --secure-plt option. * powerpc.cc (Target_powerpc::Scan::local): Detect and error on -fPIC -mbss-plt code. (Target_powerpc::Scan::global): Likewise.
2017-01-09[GOLD] Set sh_info of .rela.plt for powerpcAlan Modra1-0/+3
* powerpc.cc (Target_powerpc::make_plt_section): Point sh_info of ".rela.plt" at ".plt".
2017-01-07[GOLD] powerpc.cc tidiesAlan Modra1-38/+28
Plus some paranoia in symval_for_branch. We shouldn't get there with dynamic symbols, but if we ever did the static_cast to Powerpc_relobj would be wrong. * powerpc.cc: Use shorter equivalent elfcpp typedef for Reltype and reloc_size throughout. (Target_powerpc::symval_for_branch): Exclude dynamic symbols. (Target_powerpc::Scan::local): Use local var r_sym. (Target_powerpc::Scan::global: Likewise. (Target_powerpc::Relocate::relocate): Delete shadowing r_sym.
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-08[GOLD] Don't assert in powerpc stub_tableAlan Modra1-2/+2
A branch in a non-exec section that needs a stub can lead to this assertion. * powerpc.cc (Powerpc_relobj::stub_table): Return NULL rather then asserting.
2016-12-07[GOLD] PowerPC --stub-group-multiAlan Modra1-19/+30
Adds a new option, defaulting to off, that allows a group of stubs to serve multiple output sections. Prior to this patch powerpc gold allowed this unconditionally, which is a little unsafe with clever code that discards/reuses sections at runtime. * options.h (--stub-group-multi): New PowerPC option. * powerpc.cc (Stub_control): Add multi_os_ var and param to constructor. Sort start_ var later. Comment State. (Stub_control::can_add_to_stub_group): Heed multi_os_. (Target_powerpc::group_sections): Update.
2016-12-07[GOLD] powerpc64le-linux fails to link large Linux kernelAlan Modra1-76/+51
Gold attaches stubs to an existing section in contrast to ld.bfd which inserts a new section for stubs. If we want stubs before branches, then the stubs must be added to the previous section. Adding to the previous section is a disaster if there is a large gap between the previous section and the group. PR gold/20878 * powerpc.cc (Stub_control): Replace stubs_always_before_branch_ with stubs_always_after_branch_, group_end_addr_ with group_start_addr_. (Stub_control::can_add_to_stub_group): Rewrite to suit scanning sections by increasing address. (Target_powerpc::group_sections): Scan that way. Delete corner case. * options.h (--stub-group-size): Update help string.
2016-12-07[GOLD] PowerPC stub debugAlan Modra1-11/+27
Some more debug output, and a little hardening. * powerpc.cc (Stub_table_owner): Provide constructor. (Powerpc_relobj::set_stub_table): Resize fill with -1. (Target_powerpc::Branch_info::make_stub): Provide target debug output on returning false.
2016-12-01Fix internal error when relaxing branches to STT_SECTION symbols.Cary Coutant1-0/+2
gold/ PR gold/20807 * aarch64.cc (Target_aarch64::scan_reloc_section_for_stubs): Handle section symbols correctly. * arm.cc (Target_arm): Likewise. * powerpc.cc (Target_powerpc): Likewise.
2016-10-06[GOLD] two more fall-through commentsAlan Modra1-0/+1
* powerpc.cc (Target_powerpc::Relocate::relocate): Add fall through comment. * tilegx.cc (Target_tilegx::Relocate::relocate): Likewise.
2016-10-06[GOLD] -Wimplicit-fallthrough warning fixesAlan Modra1-2/+13
* aarch64.cc: Spell fall through comments as "// Fall through.". * arm.cc: Likewise. * mips.cc: Likewise. * powerpc.cc: Likewise. * s390.cc: Likewise. * sparc.cc: Likewise. * x86_64.cc: Likewise. * powerpc.cc (Target_powerpc::Relocate::relocate): Add missing fall through comments. * sparc.cc: (Target_sparc::Scan::global): Likewise. (Target_sparc::Relocate::relocate): Likewise. * tilegx.cc (Target_tilegx::Relocate::relocate): Likewise. * resolve.cc (symbol_to_bits): Add missing break.
2016-08-31[GOLD] Further tidy to powerpc can_add_to_stub_groupAlan Modra1-19/+20
This patch adds a little more debug output, and replaces two variables with one, tracking current max group size by group_size_ rather than by has14_. * powerpc.cc (class Stub_control): Delete stub14_group_size_ and has14_. Add group_size_. (Stub_control::can_add_to_stub_group): Adjust to suit. Print debug info when switching to adding sections before stubs.
2016-08-31[GOLD] Add debug output for powerpc section groupingAlan Modra1-0/+9
* debug.h (DEBUG_TARGET): New. (DEBUG_ALL): Add DEBUG_TARGET. (gold_debug): Delete FORMAT param. * powerpc.cc (Stub_control::can_add_to_stub_group): Print debug ourput.
2016-08-30[GOLD] correct grouping of stubsAlan Modra1-33/+70
This patch rewrites the rather obscure can_add_to_stub_group, fixing a problem with the handling of sections containing conditional external branches. When a section group contains any such section, the group size needs to be limited to a much smaller size than groups with only non-conditional external branches. PR 20523 * powerpc.cc (class Stub_control): Add has14_. Comment owner_. (Stub_control::can_add_to_stub_group): Correct grouping of sections containing 14-bit external branches. When returning false, set state_ to reflect the fact that we have one section for the next group. Rewrite most of function for clarity. Add and expand comments. (Target_powerpc::do_relax): Print stub group size retry in hex.
2016-08-28PR gold/20529 - relaxing loop never ends.Han Shen1-3/+24
gold/ChangeLog 2016-08-26 Han Shen <shenhan@google.com> * powerpc.cc (Stub_table::min_size_threshold_): New member to limit size. (Stub_table::set_min_size_threshold): New member function. (Stub_table::set_address_and_size): Add code to only allow size increase. (Target_powerpc::do_relax): Add code to record last size.
2016-02-04Fix "PowerPC64 ELFv2 entry code" for big-endianAlan Modra1-1/+1
bfd/ * elf64-ppc.c (ppc64_elf_relocate_section): Adjust last patch for big-endian. gold/ * powerpc.cc (relocate): Adjust last patch for big-endian.
2016-02-02PowerPC64 ELFv2 entry codeAlan Modra1-0/+1
This tightens the condition under which ld optimizes PIC entry code to non-PIC. bfd/ * elf64-ppc.c (ppc64_elf_relocate_section): Further restrict ELFv2 entry optimization. gold/ * powerpc.cc (relocate): Further restrict ELFv2 entry optimization.
2016-01-11Refactor gold to enable support for MIPS-64 relocation format.Cary Coutant1-22/+85
For MIPS-64, the r_info field in the relocation format is replaced by several individual fields, including r_sym and r_type. To enable support for this format, I've refactored target-independent code to remove almost all uses of the r_info field. (I've left alone a couple of routines used only for incremental linking, which I can update if/when the MIPS target adds support for incremental linking.) For routines that are already templated on a Classify_reloc class (namely, gc_process_relocs, relocate_section, and relocate_relocs), I've extended the Classify_reloc interface to include sh_type (which no longer needs to be a separate template parameter) as well as get_r_sym() and get_r_type() methods for extracting the r_sym and r_type fields. For scan_relocatable_relocs, I've extended the Default_scan_relocatable_relocs class by converting it to a class template with Classify_reloc as a template parameter. For the remaining routines that need to access r_sym, I've added a virtual Target::get_r_sym() method with an override for the MIPS target. In elfcpp, I've added Mips64_rel, etc., accessor classes and corresponding internal data structures. The MIPS target uses these new classes within its own Mips_classify_reloc class. The Mips64_ accessor classes also expose the r_ssym, r_type2, and r_type3 fields from the relocation. These changes should be functionally the same for all but the MIPS target. elfcpp/ * elfcpp.h (Mips64_rel, Mips64_rel_write): New classes. (Mips64_rela, Mips64_rela_write): New classes. * elfcpp_internal.h (Mips64_rel_data, Mips64_rela_data): New structs. gold/ * gc.h (get_embedded_addend_size): Remove sh_type parameter. (gc_process_relocs): Remove sh_type template parameter. Use Classify_reloc to access r_sym, r_type, and r_addend fields. * object.h (Sized_relobj_file::split_stack_adjust): Add target parameter. (Sized_relobj_file::split_stack_adjust_reltype): Likewise. * reloc-types.h (Reloc_types::copy_reloc_addend): (SHT_REL and SHT_RELA specializations) Remove. * reloc.cc (Emit_relocs_strategy): Rename and move to target-reloc.h. (Sized_relobj_file::emit_relocs_scan): Call Target::emit_relocs_scan(). (Sized_relobj_file::emit_relocs_scan_reltype): Remove. (Sized_relobj_file::split_stack_adjust): Add target parameter. Adjust all callers. (Sized_relobj_file::split_stack_adjust_reltype): Likewise. Call Target::get_r_sym() to get r_sym field from relocations. (Track_relocs::next_symndx): Call Target::get_r_sym(). * target-reloc.h (scan_relocs): Remove sh_type template parameter; add Classify_reloc template parameter. Use for accessing r_sym and r_type. (relocate_section): Likewise. (Default_classify_reloc): New class (renamed and moved from reloc.cc). (Default_scan_relocatable_relocs): Remove sh_type template parameter. (Default_scan_relocatable_relocs::Reltype): New typedef. (Default_scan_relocatable_relocs::reloc_size): New const. (Default_scan_relocatable_relocs::sh_type): New const. (Default_scan_relocatable_relocs::get_r_sym): New method. (Default_scan_relocatable_relocs::get_r_type): New method. (Default_emit_relocs_strategy): New class. (scan_relocatable_relocs): Replace sh_type template parameter with Scan_relocatable_relocs class. Use it to access r_sym and r_type fields. (relocate_relocs): Replace sh_type template parameter with Classify_reloc class. Use it to access r_sym and r_type fields. * target.h (Target::is_call_to_non_split): Replace r_type parameter with pointer to relocation. Adjust all callers. (Target::do_is_call_to_non_split): Likewise. (Target::emit_relocs_scan): New virtual method. (Sized_target::get_r_sym): New virtual method. * target.cc (Target::do_is_call_to_non_split): Replace r_type parameter with pointer to relocation. * aarch64.cc (Target_aarch64::emit_relocs_scan): New method. (Target_aarch64::Relocatable_size_for_reloc): Remove. (Target_aarch64::gc_process_relocs): Use Default_classify_reloc. (Target_aarch64::scan_relocs): Likewise. (Target_aarch64::relocate_section): Likewise. (Target_aarch64::Relocatable_size_for_reloc::get_size_for_reloc): Remove. (Target_aarch64::scan_relocatable_relocs): Use Default_classify_reloc. (Target_aarch64::relocate_relocs): Use Default_classify_reloc. * arm.cc (Target_arm::Arm_scan_relocatable_relocs): Remove sh_type template parameter. (Target_arm::emit_relocs_scan): New method. (Target_arm::Relocatable_size_for_reloc): Replace with... (Target_arm::Classify_reloc): ...this. (Target_arm::gc_process_relocs): Use Classify_reloc. (Target_arm::scan_relocs): Likewise. (Target_arm::relocate_section): Likewise. (Target_arm::scan_relocatable_relocs): Likewise. (Target_arm::relocate_relocs): Likewise. * i386.cc (Target_i386::emit_relocs_scan): New method. (Target_i386::Relocatable_size_for_reloc): Replace with... (Target_i386::Classify_reloc): ...this. (Target_i386::gc_process_relocs): Use Classify_reloc. (Target_i386::scan_relocs): Likewise. (Target_i386::relocate_section): Likewise. (Target_i386::scan_relocatable_relocs): Likewise. (Target_i386::relocate_relocs): Likewise. * mips.cc (Mips_scan_relocatable_relocs): Remove sh_type template parameter. (Mips_reloc_types): New class template. (Mips_classify_reloc): New class template. (Target_mips::Reltype): New typedef. (Target_mips::Relatype): New typedef. (Target_mips::emit_relocs_scan): New method. (Target_mips::get_r_sym): New method. (Target_mips::Relocatable_size_for_reloc): Replace with Mips_classify_reloc. (Target_mips::copy_reloc): Use Mips_classify_reloc. (Target_mips::gc_process_relocs): Likewise. (Target_mips::scan_relocs): Likewise. (Target_mips::relocate_section): Likewise. (Target_mips::scan_relocatable_relocs): Likewise. (Target_mips::relocate_relocs): Likewise. (mips_get_size_for_reloc): New function, factored out from Relocatable_size_for_reloc::get_size_for_reloc. (Target_mips::Scan::local): Use Mips_classify_reloc. (Target_mips::Scan::global): Likewise. (Target_mips::Relocate::relocate): Likewise. * powerpc.cc (Target_powerpc::emit_relocs_scan): New method. (Target_powerpc::Relocatable_size_for_reloc): Remove. (Target_powerpc::gc_process_relocs): Use Default_classify_reloc. (Target_powerpc::scan_relocs): Likewise. (Target_powerpc::relocate_section): Likewise. (Powerpc_scan_relocatable_reloc): Convert to class template. (Powerpc_scan_relocatable_reloc::Reltype): New typedef. (Powerpc_scan_relocatable_reloc::reloc_size): New const. (Powerpc_scan_relocatable_reloc::sh_type): New const. (Powerpc_scan_relocatable_reloc::get_r_sym): New method. (Powerpc_scan_relocatable_reloc::get_r_type): New method. (Target_powerpc::scan_relocatable_relocs): Use Powerpc_scan_relocatable_reloc. (Target_powerpc::relocate_relocs): Use Default_classify_reloc. * s390.cc (Target_s390::emit_relocs_scan): New method. (Target_s390::Relocatable_size_for_reloc): Remove. (Target_s390::gc_process_relocs): Use Default_classify_reloc. (Target_s390::scan_relocs): Likewise. (Target_s390::relocate_section): Likewise. (Target_s390::Relocatable_size_for_reloc::get_size_for_reloc): Remove. (Target_s390::scan_relocatable_relocs): Use Default_classify_reloc. (Target_s390::relocate_relocs): Use Default_classify_reloc. * sparc.cc (Target_sparc::emit_relocs_scan): New method. (Target_sparc::Relocatable_size_for_reloc): Remove. (Target_sparc::gc_process_relocs): Use Default_classify_reloc. (Target_sparc::scan_relocs): Likewise. (Target_sparc::relocate_section): Likewise. (Target_sparc::Relocatable_size_for_reloc::get_size_for_reloc): Remove. (Target_sparc::scan_relocatable_relocs): Use Default_classify_reloc. (Target_sparc::relocate_relocs): Use Default_classify_reloc. * tilegx.cc (Target_tilegx::emit_relocs_scan): New method. (Target_tilegx::Relocatable_size_for_reloc): Remove. (Target_tilegx::gc_process_relocs): Use Default_classify_reloc. (Target_tilegx::scan_relocs): Likewise. (Target_tilegx::relocate_section): Likewise. (Target_tilegx::Relocatable_size_for_reloc::get_size_for_reloc): Remove. (Target_tilegx::scan_relocatable_relocs): Use Default_classify_reloc. (Target_tilegx::relocate_relocs): Use Default_classify_reloc. * x86_64.cc (Target_x86_64::emit_relocs_scan): New method. (Target_x86_64::Relocatable_size_for_reloc): Remove. (Target_x86_64::gc_process_relocs): Use Default_classify_reloc. (Target_x86_64::scan_relocs): Likewise. (Target_x86_64::relocate_section): Likewise. (Target_x86_64::Relocatable_size_for_reloc::get_size_for_reloc): Remove. (Target_x86_64::scan_relocatable_relocs): Use Default_classify_reloc. (Target_x86_64::relocate_relocs): Use Default_classify_reloc. * testsuite/testfile.cc (Target_test::emit_relocs_scan): New method.
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-12-11Pass relocations to Target::do_calls_non_split.Cary Coutant1-1/+5
gold/ * target.h (Target::calls_non_split): Add prelocs, reloc_count parameters. (Target::do_calls_non_split): Likewise. * target.cc (Target::do_calls_non_split): Likewise. * reloc.cc (Sized_relobj_file::split_stack_adjust_reltype): Adjust call to Target::calls_non_split. * i386.cc (Target_i386::do_calls_non_split): Add prelocs, reloc_count parameters. * powerpc.cc (Target_powerpc::do_calls_non_split): Likewise. * x86_64.cc (Target_x86_64::do_calls_non_split): Likewise.
2015-12-09[GOLD] PowerPC style fixAlan Modra1-22/+27
* powerpc.cc (Target_powerpc::Relocate::relocate): New constant d_offset. Use throughout. (Target_powerpc::relocate_relocs): Likewise.
2015-12-09[GOLD] Edit PowerPC64 ELFv2 function entry codeAlan Modra1-2/+66
In an fixed position executable, the entry code does not need to be PIC and can thus lose a dependency on r12. * powerpc.cc (Target_powerpc::Relocate::relocate): Edit ELFv2 entry code. (Target_powerpc::relocate_relocs): Edit relocs to suit.
2015-12-09[GOLD] Relocate::relocate() paramsAlan Modra1-12/+9
Some linker code editing needs to change multiple insns. In some cases multiple relocations are involved and it is not sufficient to make the changes independently as relocations are processed, because doing so might lead to a partial edit. So in order to safely edit we need all the relocations available in relocate(). Also, to emit edited relocs corresponding to the edited code sequence we need some way to pass information from relocate() to relocate_relocs(), particularly if the edit depends on insns. We can't modify input relocs in relocate() as they are mmapped PROT_READ, nor it is particularly clean to write relocs to the output at that stage. So add a Relocatable_relocs* field to relinfo to mark edited relocs. Given that relocate is passed the raw reloc pointer, it makes sense to remove the rel/rela parameter and r_type too. However, that means the mips relocate() needs to know whether SHT_REL or SHT_RELA relocs are being processed. So add a rel_type for mips, which also has the benefit of removing relocate() overloading there. This patch adds the infrastructure without making use of it. Note that relinfo->rr will be NULL if not outputting relocations. * object.h (struct Relocate_info): Add "rr". * reloc.h (Relocatable_relocs::set_strategy): New accessor. * reloc.cc (Sized_relobj_file::do_relocate_sections): Init relinfo.rr for relocate_section and relocate_relocs. * powerpc.cc (relocate): Add rel_type and preloc parameters. Delete rela and r_type params, instead recalculate these from preloc. (relocate_relocs): Delete Relocatable_relocs* param, instead use relinfo->rr. * aarch64.cc: Likewise. * arm.cc: Likewise. * i386.cc: Likewise. * mips.cc: Likewise. * s390.cc: Likewise. * sparc.cc: Likewise. * target.h: Likewise. * tilegx.cc: Likewise. * x86_64.cc: Likewise. * testsuite/testfile.cc: Likewise. * target-reloc.h (relocate_section): Adjust to suit. (apply_relocation, relocate_relocs): Likewise.
2015-12-07[GOLD] R_PPC64_ENTRY supportAlan Modra1-0/+47
elfcpp/ * powerpc.h (R_PPC64_ENTRY): Define. gold/ * powerpc.cc (add_2_2_12, ld_2_12, lis_2): Define. (Target_powerpc::Scan::local, global): Handle R_PPC64_ENTRY. (Target_powerpc::Relocate::relocate): Edit code at R_PPC64_ENTRY.
2015-11-25[GOLD] Align PowerPC64 GOTAlan Modra1-1/+4
As done in a27e685f for bfd ld. * powerpc.cc (Output_data_got_powerpc::Output_data_got_powerpc): Align to 256 byte boundary.
2015-11-19[GOLD] PowerPC TOC16 and GOT16 relocs are relativeAlan Modra1-2/+1
* powerpc.cc (Target_powerpc::Scan::get_reference_flags): Correct GOT16 and TOC16 relocs to RELATIVE_REF.
2015-11-11Add assembler, disassembler and linker support for power9.Peter Bergner1-5/+64
include/opcode/ * ppc.h (PPC_OPCODE_POWER9): New define. (PPC_OPCODE_VSX3): Likewise. opcodes/ * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries. Add PPC_OPCODE_VSX3 to the vsx entry. (powerpc_init_dialect): Set default dialect to power9. * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1, extract_l1 insert_xtq6, extract_xtq6): New static functions. (insert_esync): Test for illegal L operand value. (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6, XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA, XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK, XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3, PPCVSX3): New defines. (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu, fcmpo, ftdiv, ftsqrt>: Use XBF_MASK. <mcrxr>: Use XBFRARB_MASK. <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq., bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc., cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first, cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx, lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll, lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw, modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last, rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx, stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx, subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh, vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh., vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd, vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d, vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx, vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq, vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd, vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait, xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp, xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp, xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz, xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp, xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp, xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo, xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo, xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo, xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp, xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp, xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp, xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw, xxinsertw, xxperm, xxpermr, xxspltib>: New instructions. <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9. <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands. include/elf/ * ppc.h (R_PPC_REL16DX_HA): New reloction. * ppc64.h (R_PPC64_REL16DX_HA): Likewise. bfd/ * elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_REL16DX_HA. (ppc_elf_reloc_type_lookup): Handle R_PPC_REL16DX_HA. (ppc_elf_addr16_ha_reloc): Likewise. (ppc_elf_check_relocs): Likewise. (ppc_elf_relocate_section): Likewise. (is_insn_dq_form): Handle lxv and stxv instructions. * elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_REL16DX_HA. (ppc64_elf_reloc_type_lookup): Handle R_PPC64_REL16DX_HA. (ppc64_elf_ha_reloc): Likewise. (ppc64_elf_check_relocs): Likewise. (ppc64_elf_relocate_section): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. * reloc.c (BFD_RELOC_PPC_REL16DX_HA): New. elfcpp/ * powerpc.h (R_POWERPC_REL16DX_HA): Define. gas/ * doc/as.texinfo (Target PowerPC): Document -mpower9 and -mpwr9. * doc/c-ppc.texi (PowerPC-Opts): Likewise. * config/tc-ppc.c (md_show_usage): Likewise. (md_assemble): Handle BFD_RELOC_PPC_REL16DX_HA. (md_apply_fix): Likewise. (ppc_handle_align): Handle power9's group ending nop. gas/testsuite/ * gas/ppc/altivec3.s: New test. * gas/ppc/altivec3.d: Likewise. * gas/ppc/vsx3.s: Likewise. * gas/ppc/vsx3.d: Likewise. * gas/ppc/power9.s: Likewise. * gas/ppc/power9.d: Likewise. * gas/ppc/ppc.exp: Run them. * gas/ppc/power8.s <lxvx, lxvd2x, stxvx, stxvd2x>: Add new tests. * gas/ppc/power8.d: Likewise. * gas/ppc/vsx.s: <lxvx, stxvx>: Rename invalid mnemonics ... <lxvd2x, stxvd2x>: ...to this. * gas/ppc/vsx.d: Likewise. gold/ * gold/powerpc.cc (Powerpc_relocate_functions::addr16_dq): New function. (Powerpc_relocate_functions::addr16dx_ha): Likewise. (Target_powerpc::Scan::local): Handle R_POWERPC_REL16DX_HA. (Target_powerpc::Scan::global): Likewise. (Target_powerpc::Relocate::relocate): Likewise. ld/testsuite/ * ld-powerpc/addpcis.d: New test. * ld-powerpc/addpcis.s: New test. * ld-powerpc/powerpc.exp: Run it.
2015-11-09Remove unnecessary target dependencies on relocation format.Cary Coutant1-1/+4
2015-11-09 Cary Coutant <ccoutant@gmail.com> Vladimir Radosavljevic <Vladimir.Radosavljevic@imgtec.com> gold/ * copy-relocs.h (Copy_relocs::copy_reloc): Replace reloc parameter with type, offset, addend. (Copy_relocs::save): Likewise. * copy-relocs.cc (Copy_relocs::copy_reloc): Likewise. (Copy_relocs::save): Likewise. * aarch64.cc (Target_aarch64::copy_reloc): Pass r_type, r_offset, and r_addend to Copy_relocs::copy_reloc. * arm.cc (Target_arm::copy_reloc): Likewise. * i386.cc (Target_i386::copy_reloc): Likewise. * mips.cc (Target_mips::copy_reloc): Likewise. * powerpc.cc (Target_powerpc::copy_reloc): Likewise. * s390.cc (Target_s390::copy_reloc): Likewise. * sparc.cc (Target_sparc::copy_reloc): Likewise. * tilegx.cc (Target_tilegx::copy_reloc): Likewise. * x86_64.cc (Target_x86_64::copy_reloc): Likewise.
2015-10-28Support 64-bit entry size in SHT_HASH (for s390).Marcin Kościelnicki1-4/+8
gold/ * dynobj.cc (Dynobj::create_elf_hash_table): Create hash table with target-specific entry size. (Dynobj::sized_create_elf_hash_table): Add size template parameter. * dynobj.h (Dynobj::sized_create_elf_hash_table): Likewise. * layout.cc (Layout::create_dynamic_symtab): Set entsize to hash_entry_size. * target.h (Target::hash_entry_size): New method. (Target::Target_info::hash_entry_size): New data member. * aarch64.cc (Target_aarch64::aarch64_info): Add hash_entry_size. * arm.cc (Target_arm::arm_info): Likewise. (Target_arm_nacl::arm_nacl_info): Likewise. * i386.cc (Target_i386::i386_info): Likewise. (Target_i386_nacl::i386_nacl_info): Likewise. (Target_iamcu::iamcu_info): Likewise. * mips.cc (Target_mips::mips_info): Likewise. (Target_mips_nacl::mips_nacl_info): Likewise. * powerpc.cc (Target_powerpc::powerpc_info): Likewise. * sparc.cc (Target_sparc::sparc_info): Likewise. * tilegx.cc (Target_tilegx::tilegx_info): Likewise. * x86_64.cc (Target_x86_64::x86_64_info): Likewise. (Target_x86_64_nacl::x86_64_nacl_info): Likewise. * testsuite/testfile.cc (Target_test::test_target_info): Likewise.
2015-09-02[GOLD] ppc64 out-of-line register save/restore functionsAlan Modra1-17/+69
Gold version of a4b6fadd. Don't emit long branch or plt branch stubs to save/restore functions. Copy them instead. PR 18878 * powerpc.cc (Target_powerpc): Add savres_section_ and accessor. (Target_powerpc::Branch_info::make_stub): Determine whether long branch stub is for save/restore function. (Branch_stub_ent): Add save_res_, and extra parm to constructor. (Stub_table): Add need_save_res_. (Stub_table:clear_stubs): Clear need_save_res_. (Stub_table:set_address_and_size): Add save/restore section size. (Stub_table::add_long_branch_entry): Add save_res param. Set need_save_res_, but don't add space for save/restore stubs. (Stub_table::find_long_branch_entry): Return offset to local copy of save/restore func. (Stub_table::do_write): Don't output save/restore stubs. Instead copy the save/restore functions. (Output_data_save_res:contents): New accessor. (Target_powerpc::define_save_restore_funcs): Set savres_section_.
2015-08-20gold --emit-relocsAlan Modra1-2/+4
A symbol value in an ELF final linked binary is absolute, in contrast to a relocatable object file where the value is section relative. For --emit-relocs it is therefore incorrect to use the value of a section symbol as the addend when adjusting relocs against input section symbols to output section symbols. PR gold/18846 * target-reloc.h (relocate_relocs <RELOC_ADJUST_FOR_SECTION_RELA>): Subtract os->address() from addend. * powerpc.cc (relocate_relocs): Likewise.
2015-05-16[GOLD] Add PowerPC64 -fsplit-stack supportAlan Modra1-2/+120
PowerPC64 ELFv1 requires a tweak to find_functions in order to return code addresses, rather than OPD entry addresses. * reloc.cc (Sized_relobj_file::find_functions): Use function_location. * powerpc.cc (Target_powerpc::do_calls_non_split): New function. (addi_12_1, addis_2_12, addis_12_1, cmpld_7_12_0): New constants. (lis_0): Rename from lis_0_0.
generated by cgit v1.1 at 2024-11-05 05:26:52 +0000